CN112416111B - State switching control method and device of PCIe (peripheral component interface express) equipment and related equipment - Google Patents
State switching control method and device of PCIe (peripheral component interface express) equipment and related equipment Download PDFInfo
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- CN112416111B CN112416111B CN202011347109.4A CN202011347109A CN112416111B CN 112416111 B CN112416111 B CN 112416111B CN 202011347109 A CN202011347109 A CN 202011347109A CN 112416111 B CN112416111 B CN 112416111B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/325—Power saving in peripheral device
- G06F1/3253—Power saving in bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The application discloses a method and a device for controlling state switching of PCIe (peripheral component interface express) equipment, electronic equipment and a computer readable storage medium, wherein the method is applied to the PCIe equipment and comprises the following steps: after entering the L1 state, judging whether the hardware circuit initiates an L1 sub-state entering flow; if yes, starting a timer which gives time after the preset time length; after the timer triggers the time tick, judging whether the PCIe device is still in the L1 state and does not enter the L1sub state; if so, the reference clock is switched to the internal clock of the PCIe device to enter the L1 substate. According to the method and the device, through means such as state detection and reference clock mode configuration, the problem that the PCIe device end cannot enter the L1 substate due to the fact that the PCIe host end does not strictly follow the PCIe protocol to evacuate the reference clock is effectively solved, the compatibility of the PCIe device end to the different PCIe host ends in low power consumption is enhanced, and the economic benefit of products is improved.
Description
Technical Field
The present disclosure relates to the field of electronic technologies, and in particular, to a method and an apparatus for controlling status switching of PCIe devices, an electronic device, and a computer-readable storage medium.
Background
PCIe (Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus, and is favored and widely applied in the fields of personal computers, servers, solid state disks, data centers, network cards and the like by the characteristics of high transmission speed (continuously meeting the increasing transmission bandwidth requirement), end-to-end reliable transmission, hot plug support, low power consumption management, quality of service and the like, so that the field is rapidly developed.
The PCIe protocol version 2.0 specifies PCIe Power Management as two modes, namely PCI-PM (Power Management) and ASPM (Active State Power Management). The ASPM power management states are divided into L0, L0s, L1, L2 and L3 states. Since the PCIe protocol version 3.0, the ASPM state is augmented with the L1 sub-state to better support low power consumption power management.
According to the pci 3.1a protocol, the L1 state includes L1.0, L1.1, and L1.2 sub-states, where the L1.0 sub-state is the conventional L1 state, and L1.1 and L1.2 both enter after a certain condition is satisfied on the basis of the L1.0 state: the L1.1 substate and the L1.2 substate are both entered and exited by a change in a bi-directional, open drain type clock request signal CLKREQ #, except that the power consumption and the services provided by the two substates are different. Under the L1.1 sub-state, the common mode voltage of the link still exists, and the electric idle exit detection circuits of the upstream port and the downstream port still work; in the L1.2 sub-state, the common mode voltage of the link has been turned off, as has the function of the electrical idle exit detection circuits of the upstream and downstream ports. The L1.2 substate is a deeper low power state and the exit latency is also greater than the L1.1 substate.
Although some researches on low power consumption of the PCIe have been made in the prior art, the applicant finds that there is a problem in the prior art that the PCIe device side cannot enter the L1 sub-state because the PCIe host side does not strictly follow the PCIe protocol to evacuate the reference clock. Therefore, it has become an important subject in the art to provide a solution to the above technical problems.
Disclosure of Invention
The application aims to provide a method and a device for controlling state switching of PCIe (peripheral component interface express) equipment, electronic equipment and a computer readable storage medium, so that the problem that the PCIe equipment end cannot enter an L1 substate due to the fact that the PCIe host end does not strictly follow a PCIe protocol to evacuate a reference clock is effectively solved, and the compatibility of the PCIe equipment end to different PCIe host ends in low power consumption is enhanced.
In order to solve the above technical problem, in a first aspect, the present application discloses a method for controlling state switching of a PCIe device, which is applied to the PCIe device, and the method includes:
after entering the L1 state, judging whether the hardware circuit initiates an L1 sub-state entering flow;
if yes, starting a timer which gives time after the preset time length;
after the timer triggers the time tick, judging whether the PCIe equipment is still in an L1 state and does not enter an L1 substate;
if so, the reference clock is switched to the internal clock of the PCIe device so as to enter the L1 substate.
Optionally, after the switching the reference clock to the internal clock of the PCIe device, the method further includes:
and when the hardware circuit initiates an L1 sub-state exit process, switching the reference clock to the external clock.
Optionally, during the starting of the timer, the method further includes:
continuously judging whether the hardware circuit initiates an L1 state exit flow;
if yes, closing the timer in advance and finishing the judgment.
Optionally, during the starting of the timer, the method further includes:
continuously determining whether the PCIe device has entered the L1 substate;
if yes, closing the timer in advance and finishing the judgment.
Optionally, the preset time period is 5 μ s.
On the other hand, the application also discloses a status switching control device of PCIe device, which is applied to the PCIe device, the device includes:
the judging module is used for judging whether the hardware circuit initiates an L1 sub-state entering process after entering the L1 state;
the starting module is used for starting a timer which gives time after a preset time length after judging that the hardware circuit initiates the L1 sub-state to enter the flow;
the processing module is used for judging whether the PCIe equipment is still in an L1 state and does not enter an L1 substate after the timer triggers the time tick; if so, the reference clock is switched to the internal clock of the PCIe device so as to enter the L1 substate.
Optionally, the processing module is further configured to:
after the reference clock is switched to the internal clock of the PCIe device, when the hardware circuit initiates an L1 substate exit process, the reference clock is switched to the external clock.
Optionally, the processing module is further configured to:
continuously judging whether the hardware circuit initiates an L1 state exit flow or not during the starting period of the timer; if yes, closing the timer in advance and finishing the judgment.
Optionally, the processing module is further configured to:
continuously determining whether the PCIe device has entered the L1 substate during the timer launch; if yes, closing the timer in advance and finishing the judgment.
Optionally, the preset time period is 5 μ s.
In another aspect, the present application also discloses an electronic device, including:
a memory for storing a computer program;
a processor for executing the computer program to implement the steps of any one of the above-described PCIe device stateful switchover control methods.
In yet another aspect, the present application further discloses a computer-readable storage medium, in which a computer program is stored, and the computer program is used for implementing the steps of any PCIe device status switching control method as described above when executed by a processor.
The state switching control method of the PCIe device provided by the application is applied to the PCIe device, and comprises the following steps: after entering the L1 state, judging whether the hardware circuit initiates an L1 sub-state entering flow; if yes, starting a timer which gives time after the preset time length; after the timer triggers the time tick, judging whether the PCIe equipment is still in an L1 state and does not enter an L1 substate; if so, the reference clock is switched to the internal clock of the PCIe device so as to enter the L1 substate.
The PCIe device state switching control method, the PCIe device state switching control device, the electronic device and the computer readable storage medium have the advantages that: according to the method and the device, through means such as state detection and reference clock mode configuration, the problem that the PCIe device end cannot enter the L1 substate due to the fact that the PCIe host end does not strictly follow the PCIe protocol to evacuate the reference clock is effectively solved, the compatibility of the PCIe device end to the low power consumption of different PCIe host ends is enhanced, and further the economic benefit of products is effectively improved.
Drawings
In order to more clearly illustrate the technical solutions in the prior art and the embodiments of the present application, the drawings that are needed to be used in the description of the prior art and the embodiments of the present application will be briefly described below. Of course, the following description of the drawings related to the embodiments of the present application is only a part of the embodiments of the present application, and it will be obvious to those skilled in the art that other drawings can be obtained from the provided drawings without any creative effort, and the obtained other drawings also belong to the protection scope of the present application.
Fig. 1 is a flowchart of a method for controlling a status switch of a PCIe device according to an embodiment of the present disclosure;
fig. 2 is a block diagram illustrating a configuration of a state switching control apparatus for PCIe devices according to an embodiment of the present disclosure;
fig. 3 is a block diagram of an electronic device according to an embodiment of the present disclosure.
Detailed Description
The core of the application is to provide a method and a device for controlling state switching of a PCIe device, an electronic device, and a computer-readable storage medium, so as to effectively solve the problem that the PCIe device cannot enter the L1 substate because the PCIe host does not strictly follow the PCIe protocol to evacuate a reference clock, and enhance the compatibility of the PCIe device with low power consumption of different PCIe host sides.
In order to more clearly and completely describe the technical solutions in the embodiments of the present application, the technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The PCIe protocol version 2.0 specifies PCIe Power Management as two modes, namely PCI-PM (Power Management) and ASPM (Active State Power Management). The ASPM power management states are divided into L0, L0s, L1, L2 and L3 states. Since the PCIe protocol version 3.0, the ASPM state is augmented with the L1 sub-state to better support low power consumption power management.
According to the pci 3.1a protocol, the L1 state includes L1.0, L1.1, and L1.2 sub-states, where the L1.0 sub-state is the conventional L1 state, and L1.1 and L1.2 both enter after a certain condition is satisfied on the basis of the L1.0 state: the L1.1 substate and the L1.2 substate are both entered and exited by a change in a bi-directional, open drain type clock request signal CLKREQ #, except that the power consumption and the services provided by the two substates are different. Under the L1.1 sub-state, the common mode voltage of the link still exists, and the electric idle exit detection circuits of the upstream port and the downstream port still work; in the L1.2 sub-state, the common mode voltage of the link has been turned off, as has the function of the electrical idle exit detection circuits of the upstream and downstream ports. The L1.2 substate is a deeper low power state and the exit latency is also greater than the L1.1 substate.
Although some researches on low power consumption of the PCIe have been made in the prior art, the applicant finds that there is a problem in the prior art that the PCIe device side cannot enter the L1 sub-state because the PCIe host side does not strictly follow the PCIe protocol to evacuate the reference clock. In view of this, the present application provides a status switching control scheme for PCIe devices, which can effectively solve the above problem.
Referring to fig. 1, an embodiment of the present application discloses a method for controlling state switching of a PCIe device, which is applied to the PCIe device, and the method mainly includes:
s101: after entering the L1 state, judging whether the hardware circuit initiates an L1 sub-state entering flow; if yes, the process proceeds to S102.
Specifically, when the CPU (Central Processing Unit) of the PCIe device receives the interrupt signal entering the L1 state, the CPU may enter S101 to start the subsequent program. It should be added that, after entering the L1 state, the CPU may first reset the interrupt status register indicating entry into the L1 state to zero for subsequent use.
As described above, the L1 substate is a state entered after entering the L1 state and satisfying a certain condition. When the hardware circuit initiates the L1 sub-state again to enter the flow under the L1 state, the corresponding register, i.e. app _ L1sub-dis register, will change its flag bit. In general, a 1 indicates that the L1 substate need not be entered, and a 0 indicates that the L1 substate needs to be entered.
S102: starting a timer which gives time after a preset time length; the process proceeds to S103.
If the hardware circuit has initiated the L1 substate entry flow, then, under normal circumstances, the PCIe device should switch smoothly into the L1 substate within a certain amount of time. In order to detect whether the PCIe device successfully completes the switching of the L1 sub-state, a timer with fixed timing duration as preset duration is provided.
Since the switching process of the L1 sub-state is normally completed for no more than 5 μ s, the preset time period may be 5 μ s as a preferred embodiment.
S103: after the timer triggers the time tick, judging whether the PCIe device is still in the L1 state and does not enter the L1sub state; if yes, the process proceeds to S104.
After the timing of the timer is over, if the PCIe device is still in the L1 state and has not switched to the L1 sub-state, it may be determined that the problem that the PCIe device side cannot enter the L1 sub-state has occurred.
S104: the reference clock is switched to the internal clock of the PCIe device to enter the L1 substate.
The applicant finds that the reason why the L1 sub-state cannot be switched smoothly is mainly that the PCIe host side withdraws the reference clock without strictly following the PCIe protocol, that is, the PCIe device side still uses the external clock which is not suitable for the L1 sub-state at this time. Therefore, the reference clock of the PCIe device end is switched to the internal clock, namely the clock of the chip, so that the problem can be effectively solved.
Specifically, the PCIe device side generally controls the clock mode through a corresponding register, which is a reference clock mode register. The CPU selects to use the corresponding reference clock mode by reading the value stored in the reference clock mode register. Generally, a value of 1 indicates that the internal mode of the reference clock is adopted; the value 0 indicates that the reference clock external mode is used.
Therefore, the method for controlling the state switching of the PCIe device effectively solves the problem that the PCIe device end cannot enter the L1 substate because the PCIe host end does not strictly follow the PCIe protocol to evacuate the reference clock through means of state detection, reference clock mode configuration and the like, enhances the compatibility of the PCIe device end to different PCIe host ends in low power consumption, and further effectively improves the economic benefit of products.
As a specific embodiment, the method for controlling state switching of a PCIe device provided in the embodiment of the present application, based on the foregoing, further includes, after switching a reference clock to an internal clock of the PCIe device: when the hardware circuit initiates the L1 substate exit flow, the reference clock is switched to the external clock.
Specifically, upon exiting the L1 substate, the PCIe device may resume using the external reference clock, thereby requiring the value of the reference clock mode register to be modified to 0. Similarly, when receiving the interrupt signal to exit the L1 state, the CPU may first reset the interrupt status register indicating the exit L1 state to zero for subsequent use.
As a specific embodiment, the method for controlling state switching of a PCIe device provided in the embodiment of the present application, based on the above, during the start of the timer, further includes: continuously judging whether the hardware circuit initiates an L1 state exit flow; if yes, closing the timer in advance and finishing the judgment.
Specifically, when the timer has not expired and the PCIe device has started exiting the L1 state, the L1 sub-state does not need to be entered, and therefore the timer can be turned off as it is without further processing. After the hardware circuit initiates an L1 State exit flow, it will trigger the LTSSM (Link Training and State Machine) to modify its value.
As a specific embodiment, the method for controlling state switching of a PCIe device provided in the embodiment of the present application, based on the above, during the start of the timer, further includes: continuously determining whether the PCIe device has entered the L1 substate; if yes, closing the timer in advance and finishing the judgment.
In addition, when the timing of the timer is not finished and the PCIe device has successfully switched to the L1 substate, it indicates that the situation is normal, so the timer may also be closed as it is, and no other processing is required.
Referring to fig. 2, an embodiment of the present application discloses a state switching control apparatus for PCIe devices, which is applied to the PCIe devices, and the apparatus mainly includes:
the determining module 201 is configured to determine whether the hardware circuit initiates an L1 sub-state entering process after entering the L1 state;
the starting module 202 is configured to start a timer that performs timing after a preset time duration after determining that the hardware circuit initiates the L1 sub-state to enter the process;
the processing module 203 is configured to, after the timer triggers the timeout, determine whether the PCIe device is still in the L1 state and does not enter the L1 substate; if so, the reference clock is switched to the internal clock of the PCIe device to enter the L1 substate.
Therefore, the state switching control device for the PCIe device disclosed in the embodiment of the present application effectively solves the problem that the PCIe device cannot enter the L1 substate because the PCIe host does not strictly follow the PCIe protocol to evacuate the reference clock through means such as state detection and reference clock mode configuration, enhances the compatibility of the PCIe device with low power consumption of different PCIe host sides, and further effectively improves the economic benefit of the product.
For the specific content of the PCIe device status switch control apparatus, reference may be made to the detailed description of the PCIe device status switch control method, which is not described herein again.
As a specific embodiment, in the state switching control apparatus for PCIe devices disclosed in the embodiments of the present application, on the basis of the foregoing content, the processing module 203 is further configured to:
after switching the reference clock to the internal clock of the PCIe device, the reference clock is switched to the external clock after the hardware circuit initiates the L1 substate exit flow.
As a specific embodiment, in the state switching control apparatus for PCIe devices disclosed in the embodiments of the present application, on the basis of the foregoing content, the processing module 203 is further configured to:
during the starting period of the timer, continuously judging whether the hardware circuit initiates an L1 state exit flow; if yes, closing the timer in advance and finishing the judgment.
As a specific embodiment, in the state switching control apparatus for PCIe devices disclosed in the embodiments of the present application, on the basis of the foregoing content, the processing module 203 is further configured to:
during the timer start, continuously determining whether the PCIe device has entered the L1 substate; if yes, closing the timer in advance and finishing the judgment.
As a specific embodiment, the state switching control apparatus for PCIe devices disclosed in the embodiments of the present application, based on the above contents, presets a duration of 5 μ s.
Referring to fig. 3, an embodiment of the present application discloses an electronic device, including:
a memory 301 for storing a computer program;
a processor 302 for executing the computer program to implement the steps of any of the above-described PCIe device stateful switchover control methods.
Further, the present application also discloses a computer-readable storage medium, in which a computer program is stored, and the computer program is used for implementing the steps of any PCIe device status switching control method as described above when executed by a processor.
For details of the electronic device and the computer-readable storage medium, reference may be made to the foregoing detailed description of the method for controlling the status switch of the PCIe device, and details thereof are not repeated here.
The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the equipment disclosed by the embodiment, the description is relatively simple because the equipment corresponds to the method disclosed by the embodiment, and the relevant parts can be referred to the method part for description.
It is further noted that, throughout this document, relational terms such as "first" and "second" are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Furthermore, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The technical solutions provided by the present application are described in detail above. The principles and embodiments of the present application are explained herein using specific examples, which are provided only to help understand the method and the core idea of the present application. It should be noted that, for those skilled in the art, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall into the protection scope of the present application.
Claims (10)
1. A state switching control method of a PCIe device is applied to the PCIe device, and the method comprises the following steps:
after entering the L1 state, judging whether the hardware circuit initiates an L1 sub-state entering flow;
if yes, starting a timer which gives time after the preset time length;
after the timer triggers the time tick, judging whether the PCIe equipment is still in an L1 state and does not enter an L1 substate;
if so, the reference clock is switched to the internal clock of the PCIe device so as to enter the L1 substate.
2. The stateful switchover control method of claim 1, wherein after the switching the reference clock to the internal clock of the PCIe device, further comprising:
and when the hardware circuit initiates an L1 sub-state exit process, switching the reference clock to the external clock.
3. The stateful switchover control method of claim 1, further comprising, during the timer starting period:
continuously judging whether the hardware circuit initiates an L1 state exit flow;
if yes, closing the timer in advance and finishing the judgment.
4. The stateful switchover control method of claim 1, further comprising, during the timer starting period:
continuously determining whether the PCIe device has entered the L1 substate;
if yes, closing the timer in advance and finishing the judgment.
5. The state switching control method according to any one of claims 1 to 4, wherein the preset time period is 5 μ s.
6. A status switch control apparatus for a PCIe device, applied to the PCIe device, the apparatus comprising:
the judging module is used for judging whether the hardware circuit initiates an L1 sub-state entering process after entering the L1 state;
the starting module is used for starting a timer which gives time after a preset time length after judging that the hardware circuit initiates the L1 sub-state to enter the flow;
the processing module is used for judging whether the PCIe equipment is still in an L1 state and does not enter an L1 substate after the timer triggers the time tick; if so, the reference clock is switched to the internal clock of the PCIe device so as to enter the L1 substate.
7. The stateful switchover control device of claim 6, wherein the processing module is further configured to:
after the reference clock is switched to the internal clock of the PCIe device, when the hardware circuit initiates an L1 substate exit process, the reference clock is switched to the external clock.
8. The stateful switchover control device of claim 6, wherein the processing module is further configured to:
continuously judging whether the hardware circuit initiates an L1 state exit flow or not during the starting period of the timer; if yes, closing the timer in advance and finishing the judgment.
9. An electronic device, comprising:
a memory for storing a computer program;
a processor for executing the computer program to implement the steps of the stateful switchover control for a PCIe device as defined in any one of claims 1 to 5.
10. A computer-readable storage medium, having stored thereon a computer program which, when executed by a processor, is adapted to carry out the steps of the stateful switchover control of a PCIe device as defined in any one of claims 1 to 5.
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| CN114374747B (en) * | 2022-01-11 | 2023-09-15 | 高拓讯达(北京)微电子股份有限公司 | Method and device for starting timer, electronic equipment and readable storage medium |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102662458A (en) * | 2012-04-18 | 2012-09-12 | 华为技术有限公司 | Dynamic energy-saving method and device for PCIE equipment and communication system of PCIE equipment |
| CN108713197A (en) * | 2016-03-15 | 2018-10-26 | 高通股份有限公司 | The adaptive quick peripheral assembly interconnecting chain way state saved for optimal performance and power is initiated |
| CN110419017A (en) * | 2017-03-03 | 2019-11-05 | 高通股份有限公司 | Asymmetric power rating on communication link |
| CN111124975A (en) * | 2019-12-27 | 2020-05-08 | 江苏芯盛智能科技有限公司 | PCIe device dynamic power consumption saving method and low-power consumption PCIe device |
| CN111221402A (en) * | 2018-11-26 | 2020-06-02 | 超威半导体(上海)有限公司 | Multi-layer low power states |
-
2020
- 2020-11-26 CN CN202011347109.4A patent/CN112416111B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102662458A (en) * | 2012-04-18 | 2012-09-12 | 华为技术有限公司 | Dynamic energy-saving method and device for PCIE equipment and communication system of PCIE equipment |
| CN108713197A (en) * | 2016-03-15 | 2018-10-26 | 高通股份有限公司 | The adaptive quick peripheral assembly interconnecting chain way state saved for optimal performance and power is initiated |
| CN110419017A (en) * | 2017-03-03 | 2019-11-05 | 高通股份有限公司 | Asymmetric power rating on communication link |
| CN111221402A (en) * | 2018-11-26 | 2020-06-02 | 超威半导体(上海)有限公司 | Multi-layer low power states |
| CN111124975A (en) * | 2019-12-27 | 2020-05-08 | 江苏芯盛智能科技有限公司 | PCIe device dynamic power consumption saving method and low-power consumption PCIe device |
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