CN112414548A

CN112414548A - APD digital avalanche signal extraction method with synchronous correlated sampling

Info

Publication number: CN112414548A
Application number: CN202110083524.1A
Authority: CN
Inventors: 黄大骏; 席鹏; 蒋荻
Original assignee: Zhejiang Qtec Information Technology Co ltd
Current assignee: Zhejiang Qtec Information Technology Co ltd
Priority date: 2021-01-21
Filing date: 2021-01-21
Publication date: 2021-02-26
Anticipated expiration: 2041-01-21
Also published as: CN112414548B

Abstract

A high-speed analog-to-digital converter (ADC) is used for directly sampling two peak noises in front of and behind, carrying out digital differential operation on sampling values in two periods in front of and behind to obtain a related sampling digital value, finding out the delay time with the largest fluctuation of the digital value, namely the position where an avalanche signal occurs, carrying out related sampling under the delay, and outputting the avalanche signal as an effective avalanche signal if the related sampling digital value exceeds a set digital threshold. Compared with the prior art, the method can automatically offset the spike noise by a correlated sampling and time-delay scanning method, not only can directly extract the avalanche signal, but also can offset the APD output signal change caused by the environmental temperature drift and the gate control change, improves the gate control frequency conversion capability of the APD, ensures that the extraction of the avalanche signal is stable and reliable, maintains stable detection efficiency, does not need to be repeatedly calibrated or calibrated, and has the characteristics of simplicity, high efficiency and stability.

Description

APD digital avalanche signal extraction method with synchronous correlated sampling

Technical Field

The invention relates to a single photon detector applied to the field of quantum communication, can also be applied to the situation that a gating mode is used in traditional optical communication based on APD, belongs to the field of single photon level infrared light intensity detection (G01J) and the technical field of core detectors for quantum secure communication (H04K), and particularly relates to an APD digital avalanche signal extraction method for synchronous correlated sampling.

Background

Near-infrared single photon detection can use InGaAs/InP avalanche diodes (APDs) operating in gated mode to achieve efficient single photon detection. However, the extraction of the avalanche signal of the APD in the gated mode is very difficult, because the gate signal has a large amplitude, a large spike noise signal is generated through the capacitive coupling of the diode junction of the APD, and how to extract the avalanche signal, the prior art provides the conventional method: for example, delay-based methods such as delay differentiation, delay coincidence, etc. are used; also, for example, a method based on filtering such as balance offset and direct filtering is provided; there are also comprehensive methods combining delay, balancing and filtering. However, these methods have the following problems:

1. the method for fixing the time delay based on the analog signal cannot ensure that the time delay is accurate and consistent with the working frequency, when the working frequency is changed, the time delay cannot be changed, and a product has no frequency conversion capability and has poor mass production consistency and applicability;

2. the method based on balance offset can not ensure the balance tube and the APD tube to be completely consistent, and any difference of link delay, attenuation and equivalent capacitance can directly influence the effect of balance offset;

3. in practical application, if the frequency or the pulse amplitude or width changes, the filtering output signal is greatly changed, which causes baseline drift of extraction of avalanche signals, and if the frequency or pulse amplitude or width changes, the APD detection efficiency is affected, and if the frequency or pulse amplitude or width changes, the APD avalanche signals are extracted.

The methods all belong to the analog extraction method of the avalanche signal, rely on analog signal delay and analog circuit filtering or analog circuit balancing technology, and the essence is to improve the signal-to-noise ratio of the avalanche analog signal, the signal-to-noise ratio needs to be at least more than 1, and the avalanche signal can be recovered through an analog comparator. In practical applications, the signal-to-noise ratio needs to be at least 10: 1, the avalanche signal can be extracted well, but in the specific implementation, because the delay of the analog circuit is not completely consistent, the filtering is not completely matched, the balance is not completely equivalent, the final noise is still very large, the signal-to-noise ratio needs to be improved by improving the APD high voltage, so that technical indexes such as dark count and post-pulse of the detector are sacrificed, the final signal-to-noise ratio changes along with the change of working conditions, such as environment temperature, and the change of gating characteristics (such as amplitude, width, frequency and the like), the waveform of the APD output signal changes, the baseline of the avalanche signal drifts, and the stability of the methods is deteriorated, so that the traditional method can not only not realize the optimal APD count dark and post-pulse performance, but also has various limitations on the environmental applicability, and needs to calibrate repeatedly when the use conditions change, the use is inconvenient, the performance is not stable enough, and the temperature drift and the failure risk exist.

Disclosure of Invention

The invention aims to provide an APD digital avalanche signal extraction method for synchronous correlated sampling, which aims to solve the problems in the existing avalanche signal extraction technology that: not only can the optimal APD dark count and the optimal back pulse performance be realized, but also when the environmental temperature and the gating characteristics (such as amplitude, width, frequency and the like) are changed, the calibration needs to be repeatedly calibrated, the use is inconvenient, the performance is not stable, and the technical defects of temperature drift, failure risk and the like exist.

The technical scheme of the invention is realized as follows:

an APD digital avalanche signal extraction method of synchronous correlated sampling comprises the following steps:

(1) the method comprises the steps that a gated clock signal is input and divided into two paths through clock fan-out, one path is used as a synchronous sampling clock of an ADC after program-controlled delay is carried out through a variable clock delay module, and the other path is an APD gated clock signal;

(2) the delayed clock is used as a synchronous sampling clock of an ADC (analog to digital converter), sampling and digitalizing the output of the APD signal through the ADC, and sampling only one point in each gating period to obtain a digitalized value X (i) of the APD signal, wherein i =0,1,2 …, and i represents a sampling serial number and corresponds to a corresponding gating period;

(3) performing correlated sampling, namely performing difference operation on digitized data of the previous period and the next period of X (i) to obtain correlated sampling values Y (i) = X (i) — X (i-1);

(4) determining the delay position of the avalanche signal through delay scanning;

(5) continuously carrying out correlated sampling at the time delay position to obtain a digitized avalanche signal;

(6) carrying out statistical analysis on the digitized avalanche signal, and determining an avalanche signal Digital Threshold (DTH) according to an avalanche signal digital threshold determination method;

(7) and comparing the related sampling value with an avalanche signal digital threshold DTH, and outputting the related sampling value as a valid avalanche signal detection count if the related sampling value Y (i) > DTH.

Preferably, the delay scanning specifically comprises:

(1) starting delay scanning, setting a delay scanning range and a delay scanning step length, and sequentially assigning values to delay through a system control and data processing module: delay = d (j), where j =0,1,2 …, j represents a scan number;

(2) starting related sampling under the current delay D (j), generating an APD related sampling digital value Y through a related sampling circuit, and generating a digital value Y in each sampling clock period;

(3) performing data statistical analysis on the set number N of related sampling digital values Y, and recording the maximum value Max (Y) in the sampling data under the current delay D (j);

(4) sequentially increasing delay amount according to the set delay scanning step length, enabling j = j +1, returning to the step (2) to perform correlated sampling again, and repeating the steps (2), (3) and (4) until all scanning of the set delay scanning range is completed, so that a Max (Y) is obtained under each delay amount;

(5) after the set delay scanning range is scanned, because the digital value of the relevant sampling at the avalanche position has the statistical fluctuation with the magnitude change relative to the previous period, namely, the corresponding delay D (k) with the maximum peak value in all Max (Y) is selected as the target delay, and the determination of the avalanche position delay is completed.

Preferably, the avalanche signal digital threshold determination method includes a direct method, specifically:

(1) firstly, adjusting APD bias voltage and closing avalanche of APD;

(2) carrying out correlated sampling for a period of time to obtain the maximum value of Y, namely the maximum value of the system noise signal;

(3) determining the avalanche signal digital threshold DTH = the maximum value + H of the system noise signal, H is a system adjustment allowance;

(4) and adjusting the bias voltage of the APD, recovering normal avalanche, and finishing the determination of the digital threshold value DTH of the avalanche signal.

Preferably, the avalanche signal digital threshold determination method includes a histogram method, specifically:

(1) carrying out histogram statistics on a large number of related sampled digital values Y to obtain different histogram statistical distribution maps of Y;

(2) the correlation sampling result of the periodic spike noise is the sampling background noise of the system ADC, the sampling background noise can present normal distribution with the average value of 0, and the distribution peak of an avalanche signal can appear in the region outside the normal distribution;

(3) adjusting the APD bias voltage high so that avalanche signal intensity appears in the histogram;

(4) when a valley bottom appears between an avalanche signal distribution peak and a normal distribution peak of noise, taking Y at a double-peak junction as a digital threshold value DTH;

(5) the determination of the avalanche signal digital threshold DTH is completed.

Preferably, the correlation sampling method is as follows:

ADC _ DCO is the accompanying clock of the DATA output by the ADC, which is synchronized with the sampling time, ADC _ DATA is the digitized APD output signal x (i),

ADC _ DCO is connected to the clock input ends of the first and second flip-flops, and X (i) is connected to the data input end of the first D flip-flop and the second input end of the digital subtracter, and the output end of the first D flip-flop is an APD digitalized signal X (i-1) of the previous sampling period and is connected to the first input end of the subtracter;

and obtaining output data of X (i) -X (i-1) through the operation of a subtracter, and connecting the output data to a data input end of a second trigger, wherein the data output end of the second trigger is data of Y (i-1) and is used for obtaining the related sampling digital value Y of the APD in the previous period.

Preferably, the system regulation margin is 10-100 ADU, and the ADU is the minimum digital unit of the ADC.

Preferably, the delay scanning range only covers the delay from the gating input signal to the output of the APD, and the delay is related to the actual line delay and unrelated to the gating period, and is 0-5 ns.

Preferably, the delay scanning step size should be considered comprehensively according to the avalanche signal characteristics and the scanning time, and the selection range of the delay scanning step size is 10-50 ps.

Compared with the prior art, the invention has the following beneficial effects:

1. according to the method, peak noise can be automatically offset by a correlated sampling and time-delay scanning method, avalanche signals can be directly extracted, temperature drift and APD output signal change caused by gating change can be offset, so that the temperature drift of detection efficiency can be restrained, the gating frequency conversion capability of APD is improved, the extraction of the avalanche signals is stable and reliable, the detection efficiency is maintained stable, repeated calibration or calibration is not needed, and the method has the characteristics of simplicity, high efficiency and stability;

2. the invention can recover the avalanche signal submerged in noise, realizes the signal extraction with the signal-to-noise ratio less than 1, does not need to improve the signal-to-noise ratio by improving the working voltage of the APD, and then can improve the working performance of the APD, such as improving the detection efficiency of the APD and reducing the dark count probability and the post-pulse probability of a system;

3. compared with direct waveform real-time digital sampling, the method utilizes correlated sampling, only one point is acquired in each peak noise period, the requirement of the system on high-speed sampling can be greatly reduced, the highest sampling frequency only needs to reach the gating highest frequency, more than twice signal bandwidth which meets the Nyquist sampling theorem requirement is not needed, and the cost of an analog-digital conversion circuit and the system design complexity can be greatly reduced.

Drawings

FIG. 1 is a schematic block diagram of an APD digital avalanche signal extraction system with synchronous correlated sampling;

FIG. 2 is a functional block diagram of a circuit of a correlated sampling digital differential module;

FIG. 3 is a flow chart of an APD digital avalanche signal extraction method with synchronous correlated sampling;

FIG. 4 is a timing diagram of a synchronous correlated sampling avalanche signal extraction method;

FIG. 5a is a flowchart of a time-lapse scan;

FIG. 5b is a schematic diagram of the result of the time-delay scan;

FIG. 6a is a flow chart of the digital avalanche threshold determination method 1 direct method;

FIG. 6b is a schematic diagram of the data results of the digital avalanche threshold determination method 1 direct method;

fig. 7a is a flow chart of a histogram method of the digital avalanche threshold determination method 2;

FIG. 7b is a schematic diagram of the histogram principle of the digital avalanche threshold determination method 2 direct method;

fig. 8 is an overall flowchart of the method for extracting the synchronous correlated sampling APD digital avalanche signal.

In the figure: the system comprises a synchronous signal clock generator 100, a clock fan-out module 200, a program-controlled clock delay module 300, an ADC (analog-to-digital converter) module 400, a system control and data processing module 500, a gate control generation module 600, an APD avalanche detection module 700 and an APD avalanche signal output module 800.

Detailed Description

The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown.

As shown in fig. 1, a digital avalanche signal extraction system using synchronous correlated sampling includes a gate-controlled input signal clock generator 100, a clock fan-out module 200, a program-controlled clock delay module 300, an ADC (analog-to-digital converter) module 400 (hereinafter referred to as ADC), a system control and data processing module 500, a gate control generation module 600, an APD avalanche detection module 700, and an APD avalanche signal output module 800, wherein the synchronous signal clock generator 100 is connected to an input of the clock fan-out module 200, an output of the clock fan-out module 200 is respectively connected to the program-controlled clock delay module 300 and an input of the gate control generation module 600, an output of the program-controlled clock delay module 300 is connected to the ADC (analog-to-digital converter) module 400, a control end of the program-controlled clock delay module 300 is connected to the system control and data processing module 500, and the gate control generation module 600 is sequentially connected to the APD, The APD avalanche signal output module 800 is connected to the output end of the APD avalanche signal output module 800 and the ADC (analog-to-digital converter) module 400, the output end of the ADC (analog-to-digital converter) module 400 is connected to the system control and data processing module 500, the system control and data processing module 500 is a circuit system control and data processing based on FPGA design, and includes a program control delay scanning module and an ADC sampling control module, the program control delay scanning module performs delay control and scanning on the program control clock delay module 300 and obtains avalanche signal delay, and the ADC sampling control module performs sampling control on the ADC (analog-to-digital converter) module 400.

A synchronous signal clock generator 100, the synchronous signal clock generator 100 emitting a synchronous clock and dividing the synchronous clock into two by a clock fan-out module 200;

a gate control generation module 600, which receives a synchronous clock signal and generates a gate control clock for generating APD;

the other path of clock signal is used as the input of the program-controlled clock delay module 300, and the program-controlled clock delay module 300 delays the input clock signal for a certain time according to the instruction and then outputs the delayed input clock signal;

an ADC (analog-to-digital converter) module 400, wherein an output of the programmable clock delay module 300 is connected to a clock input of the ADC (analog-to-digital converter) module 400, and is used as a delayed ADC sampling clock;

an APD avalanche detection module 700, wherein the APD signal output generated by the APD gated clock passing through the APD avalanche detection module 700 includes spike noise and avalanche signal (normally, the avalanche signal is submerged in the spike noise);

an APD avalanche signal output module 800, which outputs an APD signal (which may be an APD signal directly output or an APD signal processed by a conventional spike noise suppression method) containing an avalanche signal and a spike noise to an analog signal input end of the ADC (analog-to-digital converter) module 400 through the APD avalanche signal output module 800;

an ADC (analog-to-digital converter) module 400, wherein the ADC outputs data after being digitalized and is connected to the system control and data processing module 500;

and the system control and data processing module 500 controls the program control clock delay module 300 and performs related sampling circuit processing on the ADC data, and avalanche signal counting pulse output can be obtained by a delay scanning method and an avalanche signal extraction method.

As shown in fig. 2, an ADC (analog-to-digital converter) module 400 includes a specific data processing circuit for ADC digital correlated sampling, and the specific structure is as follows: the digital-to-analog converter comprises a first D trigger, a second D trigger and a digital subtracter, wherein ADC _ DCO is an accompanying clock of data output by an ADC, and the clock and sampling time are synchronous; ADC _ DATA is a digitized APD output signal X (i), ADC _ DCO is connected to clock input ends of a first D trigger and a second D trigger, X (i) is connected to a DATA input end of the first D trigger and a second input end of a digital subtracter, the output end of the first D trigger is an APD digitized signal X (i-1) of a previous sampling period and is connected to a first input end of the digital subtracter, output DATA obtained through operation of the digital subtracter are X (i) -X (i-1) and are connected to a DATA input end of the second D trigger, and DATA output end DATA of the second D trigger is Y (i-1) and is an APD related sampling digitized value of a previous period.

The invention also discloses an APD digital avalanche signal extraction method of synchronous correlated sampling, which directly samples front and back peak noises through a synchronous high-speed analog-to-digital converter (ADC), digitally differentiates two digital sampling values, firstly finds a position with larger fluctuation of a difference value through delay scanning, namely the time when the avalanche signal occurs, and outputs the avalanche signal as an effective avalanche signal through correlated sampling under the delay if the difference value exceeds a statistical distribution threshold.

The basic flow of the extraction method is as follows: the gate control clock is divided into two paths, one path is used for generating gate control, the other path is used as an ADC sampling clock after program control delay is carried out through a variable clock delay module, on the other side, signals output by APDs contain avalanche/spike noise synchronous with the gate control signals, the spike noise can be directly sent to the ADC for sampling through/without a traditional spike noise suppression technology, digital difference is carried out on the sampled data through a first-stage trigger and a second-stage trigger, then digitized related sampling signals can be obtained, delay parameters corresponding to the maximum fluctuation of the related sampling signals are obtained through delay scanning of the ADC sampling clock, namely the position of the avalanche signals is confirmed, then the digital threshold of the avalanche signals can be determined according to a statistical principle, and if the digital value of the related sampling signals is larger than the threshold, effective avalanche counting signals are output.

The APD digital avalanche signal extraction method with synchronous correlated sampling of the present invention, as shown in fig. 3 and 8, specifically includes the following steps:

As shown in fig. 4, a schematic diagram of the avalanche signal extraction method is shown, and since the APD spike noise is generated due to the gating applied to the APD and the junction capacitance of the APD, belonging to the gating-capacitance response signal, the spike noise is usually larger than the weak avalanche signal, so that the avalanche signal is buried in the spike noise. But because the spike noise is a gating-capacitance response signal, the spike noise is synchronously related to a gating clock and has the characteristic of periodicity; on the other hand, the avalanche signal is generated under the gate control induction, is related to the quantum efficiency of photon arrival and APD, and has no periodicity but certain randomness and sparseness although the clock time can also be gated. Therefore, the method can generate an ADC sampling clock synchronous with the gating clock through the delay unit, and the sampling clock can be aligned to the generation position of the avalanche signal under the delay. On the other hand, due to the randomness and the sparsity of the occurrence of the avalanche signal, the avalanche signal can be sampled through correlated sampling, namely the digital difference of two front and rear spike noises. This method of correlated sampling uses the difference between the two ADC digitized signals before and after, which is small when the delay is not aligned with the position of the avalanche signal due to the high correlation of the periods before and after the spike noise. When the time delay is aligned with the position of the avalanche signal, if avalanche occurs at the position, the waveform is sampled, and then the digital signal after related sampling is obviously increased.

As shown in fig. 5a, the specific method of the time-delay scanning is as follows:

In some preferred embodiments, the delay scanning range only covers a delay amount from the gating input signal to the APD output, and the delay amount is related to the actual line delay and is not related to the gating period, and the delay scanning range is 0-5 ns. The delay scanning step size should be considered comprehensively according to the avalanche signal characteristics and the scanning time; the selection range of the delay scanning step length is 10-50 ps, and the optimal delay scanning step length is 20 ps.

The scanning image of the Delay scanning method is shown in fig. 5b, in which the horizontal axis is the program-controlled Delay value Delay, and the vertical axis is the statistical maximum max (Y) of a certain number N of the related sampled digitized values Y under the corresponding Delay value.

The avalanche signal digital threshold determination method includes a direct method, as shown in fig. 6a, specifically:

(1) firstly, adjusting APD bias voltage and closing avalanche of APD;

As shown in fig. 6b, the horizontal axis represents the sample sequence number i, and the vertical axis represents the correlation sample value y (i).

As shown in fig. 7a, the avalanche signal digital threshold determination method includes a histogram method, which specifically includes:

The histogram result of the threshold determination is shown in fig. 7b, in which the horizontal axis represents the correlation sample value Y and the vertical axis represents the histogram count value hist (Y).

The specific method of correlated sampling is as follows:

the hardware circuit adopted by the correlated sampling comprises a first D trigger, a second D trigger and a digital subtracter.

During the delay scan, the set number N is greater than the longest interval between two avalanches divided by the gating period. In some preferred embodiments, the bias voltage value of the APD can be increased to open APD avalanches to ensure multiple avalanches within 100ms (e.g., the avalanche count per unit time is much greater than 10 cps), and the number N is set to 100 ms/minimum gating period, e.g., if the minimum gating period is 10ns (corresponding to 100MHz gating), then N is not less than 100ms/10ns =10^ 7.

The method can solve the problems of analog circuits such as inconsistent delay, mismatched filtering, ineffectiveness in balance and the like in actual operation of the traditional method for extracting the APD avalanche signal in the gating mode, and the problems can cause that the amplitude and the baseline of the spike noise suppressed by the traditional method are still influenced by gating repetition frequency, gating width, gating temperature drift and device temperature drift to form noise amplitude change and avalanche baseline drift, and further cause the problems of avalanche signal extraction failure such as APD photoelectric detection efficiency change, even counting saturation or no counting and the like. In practical application, the invention can ensure stable detection efficiency through a related sampling method, is not influenced by technical parameters such as time delay, filtering, balance and the like, can normally recover avalanche signals even if the gating frequency is changed or the gating width is changed or the gating amplitude is changed, does not cause the change of the detection efficiency or the detection failure, and does not need to repeatedly calibrate and calibrate. Another feature of the present invention is that an avalanche signal with a signal-to-noise ratio <1 can be recovered, and even if the avalanche signal is submerged in spike noise, effective recovery can be achieved by a correlated sampling digitization technique. In conclusion, the method overcomes the influence of the peak noise change or the avalanche signal baseline drift on the APD photoelectric detection efficiency, even if the amplitude, the frequency, the shape and the baseline of the peak noise change, the method can automatically offset the change, recover the submerged avalanche signal from the larger peak noise, ensure the stable detection efficiency and ensure the stable and reliable detection instrument.

Claims

1. A synchronous correlated sampling APD digital avalanche signal extraction method is characterized by comprising the following steps:

2. The method according to claim 1, wherein the delay scan comprises:

(5) and after the set delay scanning range is scanned, selecting a corresponding delay D (k) with the maximum peak value in all Max (Y) as a target delay, and finishing the determination of the avalanche position delay.

3. The APD digital avalanche signal extraction method of synchronous correlated sampling according to claim 1 or 2, characterized in that the avalanche signal digital threshold value determination method comprises a direct method, in particular:

(1) firstly, adjusting APD bias voltage and closing avalanche of APD;

4. The APD digital avalanche signal extraction method according to claim 1 or 2, characterized in that the avalanche signal digital threshold value determination method includes a histogram method, in particular:

5. The APD digital avalanche signal extraction method with synchronous correlated sampling according to claim 1 or 2, characterized in that the correlated sampling is as follows:

6. The method according to claim 3, wherein the system regulation margin is 10 to 100 ADU, and the ADU is the minimum digitization unit of the ADC.

7. The method according to claim 2, wherein the delay scan range is 0-5 ns.

8. The method according to claim 2, wherein the delay scan step is selected in a range of 10-50 ps.