CN112405337B

CN112405337B - Polishing pad and method for manufacturing semiconductor device

Info

Publication number: CN112405337B
Application number: CN202110086051.0A
Authority: CN
Inventors: 黄学良; 蔡长益; 邱瑞英; 桂辉辉; 刘敏; 罗乙杰; 杨佳佳; 张季平
Original assignee: Hubei Dinglong Co ltd; Hubei Dinghui Microelectronic Material Co ltd
Current assignee: HUBEI DINGHUI MICROELECTRONICS MATERIALS Co.,Ltd.; HUBEI DINGLONG Co.,Ltd.; Changxin Memory Technologies Inc
Priority date: 2021-01-22
Filing date: 2021-01-22
Publication date: 2021-04-09
Anticipated expiration: 2041-01-22
Also published as: CN112405337A

Abstract

The invention discloses a method for manufacturing a polishing pad and a semiconductor device, which comprises the steps of grinding the surface of a semiconductor wafer by using the polishing pad with a specific pattern and physical parameters; the invention also discloses a polishing pad, which comprises a polishing layer, wherein the hardness of the polishing layer is 40-70D, the density of the polishing layer is 0.6-0.9g/cm3, the polishing layer comprises a polishing surface and polishing units positioned on the polishing surface, one end of each polishing unit forms a contact surface, and the contact surface is directly contacted with the ground material; the plurality of polishing units respectively form a first part and a second part, the first part extends along a first direction and is uniformly spaced, and the second part extends along a direction parallel to the first direction and is uniformly spaced; and the surface of the contact surface of the polishing unit is provided with a channel and comprises a first channel and a second channel; the polishing pad has excellent comprehensive performance when the parameters such as the limited polishing unit area ratio, the effective area ratio and the like are combined with the limited physical property parameters of the polishing layer.

Description

Polishing pad and method for manufacturing semiconductor device

Technical Field

The present invention relates to the field of Chemical Mechanical Polishing (CMP) of semiconductors, and more particularly, to a polishing pad for polishing at least one of a magnetic substrate, an optical substrate, and a semiconductor substrate, and having well-designed physical parameters and a surface groove structure, and a method for manufacturing a semiconductor device polished using the polishing pad.

Background

In the fabrication of integrated circuits, other electronic devices, and optical materials, many processes involving polishing, thinning, or planarizing of the material are most commonly used chemical mechanical polishing. The action principle of chemical mechanical polishing is that on a fixed polishing machine, a grinding liquid acts on a polishing pad, the polishing pad is in contact with the surface of a ground material, chemical reaction can occur, meanwhile, the polishing pad and the ground material do rotary motion on the machine, mechanical action of shearing is generated, and the chemical action and the mechanical action polish the ground material together to form a desired pattern structure.

Therefore, the flow and distribution of the slurry, the distribution of the mechanical force generated by the grooves, and the like have a determining effect on the performance of the chemical mechanical polishing pad, and the effects of these factors have different requirements for different patterns and materials, and many attempts have been made to form the groove structure of the polishing pad.

EP0829328a2 of h.f. leinhardt et al discloses a surface structure of a polishing pad of concentric circles, grooves, spirals, rays, lattice to promote the flow of polishing liquid, but does not disclose the relation of specific parameters of the surface groove structure of the polishing pad to the polishing performance, or how to obtain a polishing effect having excellent overall performance.

US20060014477a1 of r.v. parrapabrus discloses a design with an oscillating structure in the radial direction, which has changed the residence time of the polishing liquid in different areas, but also does not disclose the relation of specific design parameters to the polishing performance.

JP2006167907A of g.p.malteni discloses a special structure having grooves spaced apart from each other in order to improve the flow rate of the slurry and thereby reduce the waste of slurry.

TW201904719A to j.v. raney et al discloses grooves of a non-isosceles trapezoid structure and illustrates that a concentric circular groove structure is the most popular groove pattern, and a polishing pad of a non-isosceles trapezoid structure is considered to have a better polishing effect.

The prior art discloses various groove structures, but the relation between a specific groove structure and polishing performance and how to optimize are not deeply researched, the research on the polishing performance as an experimental science has the influence relation among complex factors, the research on the polishing performance is not sufficient in theory, the design of a polishing pad is crucial to the polishing performance of the polishing pad, and the manufacturing process of a semiconductor device is directly influenced. Therefore, it is highly desirable to obtain the relationship between groove structure and polishing performance of the polishing pad, and to design a polishing pad having excellent overall polishing performance.

The polishing pad is provided with the polishing units which are arranged, small channels are designed on the polishing units, and the polishing pad with excellent comprehensive polishing performance is optimized through a large amount of experimental researches and can be used for chemical mechanical polishing of at least one of magnetic substrates, optical substrates and semiconductor substrates.

Disclosure of Invention

A first object of the present invention is to provide a method for manufacturing a semiconductor device, comprising a step of polishing a surface of a semiconductor wafer using a polishing pad comprising a polishing layer having a hardness of 40 to 70D and a density of 0.6 to 0.9g/cm³(ii) a The polishing layer comprises a polishing surface and polishing units positioned on the polishing surface, the polishing units form a polishing unit group, one end of the polishing unit group forms a contact surface, the contact surface is directly contacted with the ground material, and the projection of each polishing unit on the contact surface is a parallelogram;

a plurality of polishing elements constituting a first section, the polishing elements of the first section extending in a first direction and being uniformly spaced,

a plurality of polishing elements constituting a second section, the polishing elements of the second section extending in a direction parallel to the first direction and being uniformly spaced, the polishing elements of the first section being spaced at a spacing equal to the spacing of the polishing elements of the second section, the spacing distance in the first direction being W1;

the polishing unit is composed of a plurality of first portions and second portions which are equally spaced from each other by a distance W2 in the second direction; the surface of the contact surface of the polishing unit is provided with a channel which is a straight line and comprises a plurality of first channels and a plurality of second channels, wherein the first channels are parallel to the first direction, and/or the second channels are parallel to the second direction;

the contact surface of the polishing unit has an area S1, the sides of a parallelogram projected on the contact surface of the polishing unit in a first direction and a second direction are respectively L1 and L2, and the included angle between the first direction and the second direction is theta, as follows:

S1=L1*L2*sinθ

the projection of the channels on the contact surface of the polishing units has an area Sa, and on each polishing unit, the first channels are n in number, Waa in average width and L1 in length; the number of the second channels is m, the average width is Wab, the length is L2, the average depth of the channels is Da, wherein n and m are integers, m + n is not less than 1, and the number of intersection points Nb = m × n, as follows:

Sa=n*Waa*L1*sinθ+m*Wab*L2*sinθ-Nb*Waa*Wab*sinθ

the effective contact area Ss of the polishing unit is as follows:

Ss=S1-Sa=sinθ*(L1*L2- n*Waa*L1-m*Wab*L2+Nb*Waa*Wab)

the polishing layer effective contact area ratio RS3 is defined as follows:

RS3=Ss/((L1+W1)*(L2+W2)*sinθ)

(L1 × (L2-n × (Waa) × L1-m × (Wab) × (L2+ Nb × (Waa)/((L1 + W1) × (L2+ W2)), and RS3 is in the range of 50 to 85%;

the grinding area ratio RS1 is defined as follows:

RS1= L1 × L2/((L1+ W1) × (L2+ W2)), RS1 ranges from 0.60 to 0.92;

the effective contact area ratio RS2 of the polishing elements is defined as follows:

RS2= Ss/S1, RS2 ranging from 0.5-0.97.

It is another object of the present invention to provide a polishing pad for polishing of magnetic, optical and semiconductor substrates comprising a polishing layer having a hardness of 40 to 70D and a density of 0.6 to 0.9g/cm³；

The polishing layer comprises a polishing surface and polishing units positioned on the polishing surface, the polishing units form a polishing unit group, one end of the polishing unit group forms a contact surface, the contact surface is directly contacted with the ground material, and the projection of each polishing unit on the contact surface is a parallelogram;

S1=L1*L2*sinθ

Sa=n*Waa*L1*sinθ+m*Wab*L2*sinθ-Nb*Waa*Wab*sinθ

the effective contact area Ss of the polishing unit is as follows:

Ss=S1-Sa=sinθ*(L1*L2- n*Waa*L1-m*Wab*L2+Nb*Waa*Wab)

the polishing layer effective contact area ratio RS3 is defined as follows:

RS3=Ss/((L1+W1)*(L2+W2)*sinθ)

the grinding area ratio RS1 is defined as follows:

RS1= L1 × L2/((L1+ W1) × (L2+ W2)), RS1 ranges from 0.60 to 0.92;

RS2= Ss/S1, RS2 ranging from 0.5-0.97.

In one embodiment of the present disclosure, the polishing layer has a hardness of 50 to 65D and a density of 0.7 to 0.9g/cm³。

In one embodiment of the present disclosure, the polishing layer has a storage modulus E' at 40 ℃ of 150-300 MPa; the energy loss factor KEL is 200-450Pa^-1And tan delta is 0.05 to 0.15.

In one embodiment of the present disclosure, the polishing layer has a storage modulus E' of 180-240 MPa and a tan delta of 0.07-0.10 at 40 ℃.

In one embodiment of the present disclosure, the polishing elements have an average height D1, an effective channel width ratio RW4= (n × Waa + m × Wab)/(W1+ W2), RW4 is in a range of 0.1 to 3.75;

the effective channel volume ratio RV5= (Sa × Da)/(sin θ ((L1+ W1) — (L2+ W2) -L1 × L2) × D1), and RV5 ranges from 0.03 to 3.4.

In one embodiment of the present disclosure, the polishing units have L1 and L2 in the range of 10-20 mm.

In one embodiment of the present disclosure, the effective contact area ratio RS3 ranges from 60 to 70%.

In one embodiment of the disclosure, the first channels are uniformly distributed at intervals, and/or the second channels are uniformly distributed at intervals.

In one embodiment of the present disclosure, the polishing elements have the same or substantially the same height.

In one embodiment of the present disclosure, the channels have the same or substantially the same depth.

In one embodiment of the present disclosure, the average height D1 is 0.2-0.8 times the thickness of the polishing layer.

In one embodiment of the present disclosure, the average depth Da of the channels is 0.4 to 1 times the height D1 of the polishing elements.

In one embodiment of the present disclosure, Waa and Wab range from 0.15mm to 0.6 mm.

In one embodiment of the present disclosure, Waa and Wab range from 0.15mm to 0.4 mm.

In one embodiment of the present disclosure, the polishing units have W1 and W2 in the range of 0.5-5 mm.

In one embodiment of the present disclosure, the polishing units have W1 and W2 in the range of 0.8-3 mm.

In one embodiment of the disclosure, the number of the first channels is any one of 2 to 5, and/or the number of the second channels is any one of 2 to 5.

In one embodiment of the disclosure, the number of the first channels is any one of 3 to 5, and/or the number of the second channels is any one of 3 to 5.

The invention discloses an embodiment, wherein the projection of the polishing unit on the contact surface is rectangular.

The invention discloses an embodiment, wherein the projection of the polishing unit on the contact surface is square.

An embodiment of the present disclosure wherein W1 is the same or substantially the same as W2.

An embodiment of the present disclosure wherein L1 is the same or substantially the same as L2.

The invention discloses an embodiment, wherein the projection of the polishing unit on the contact surface is a diamond shape.

According to one embodiment of the invention, the polishing units are arranged in a square matrix on the polishing layer, and the center distances of the adjacent polishing units are equal.

In one embodiment of the present disclosure, the RS2 is in the range of 0.72 to 0.93.

In one embodiment of the present disclosure, the RW4 is in the range of 0.15 to 2.

In one embodiment of the present disclosure, the RV5 is in the range of 0.05-0.71.

In one embodiment of the present disclosure, the average depth Da of the channels is 0.4-0.8 times the polishing unit height D1.

In a disclosed embodiment, the polishing layer of the polishing pad of the invention optionally further comprises an endpoint detection window, preferably the detection window is an integrity window incorporated into the polishing layer.

The above-mentioned embodiments are only some specific explanations made on the technical idea of the present invention, and should not be construed as limiting the present invention to these embodiments.

The invention has the beneficial effects that:

the polishing pad with excellent comprehensive polishing performance is obtained through limited polishing layer materials and special groove design. .

Drawings

The above and other objects, features and advantages of the present invention will become more readily apparent from the following detailed description of the preferred embodiments of the present invention which proceeds with reference to the accompanying drawings, but which is not intended to represent the scale and dimensions of the present invention but is to be limited to the illustrative drawings.

FIG. 1 schematically illustrates a perspective view of a polishing pad according to a preferred embodiment of the present invention.

Fig. 2 is a partially enlarged view of a group of polishing units of the polishing pad shown in fig. 1.

Fig. 3 is a partially enlarged view of a polishing unit of the polishing pad shown in fig. 2.

Fig. 4 schematically illustrates a plan view of a polishing pad according to another preferred embodiment of the present invention.

FIG. 5 schematically illustrates a plan view of a polishing pad according to another preferred embodiment of the present invention.

FIG. 6 schematically illustrates a plan view of a polishing pad according to another preferred embodiment of the present invention.

Fig. 7 schematically illustrates a plan view of a polishing pad according to another preferred embodiment of the present invention.

Detailed Description

The technical solution of the present invention will be described in detail with reference to the accompanying drawings.

As used herein, the term "substantially" is used to describe and illustrate small variations. For example, two numerical values are considered to be "substantially" the same or equal if the difference between the two numerical values is less than or equal to ± 5% (such as less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%) of the mean of the values.

(1) Preparation of polishing layer

The polyurethane polishing layer can be prepared by adopting a known prepolymer method, a one-step method and other methods, and the method selected by the technical personnel of the invention according to the needs does not influence the conception and the protection scope of the invention, so long as the polishing pad related to the invention can be prepared. The polishing layer prepared by the method is prepared by different physical parameters such as hardness, density, DMA parameters (storage modulus, tan delta and KEL value) and the like through different contents of isocyanate, polyol, curing agent and microspheres. Microspheres manufactured by Akzo Nobel under the trademark Expancel 551DE40D42 were used in this example. The TDI, namely toluene diisocyanate, with different mass parts, the PTMEG, namely polytetramethylene ether glycol, with specific molecular weight, the MOCA, namely 3,3 '-dichloro-4, 4' -diaminodiphenylmethane, and the microspheres, which account for different mass fractions of the total polishing layer, in the table 1 are added into a casting head, rapidly mixed at a mixing speed of 5000rpm, cast into a mold to form a cylinder, then the cylinder is sliced to obtain a sheet, finally, grooving processing is performed on the sheet to obtain a polishing layer with a groove pattern, and the prepared polishing layer is about 2 mm. Examples are 1-12 and comparative examples are D1-D7. Table 1 shows polishing layers made with different formulations.

TABLE 1 formulation composition of polishing layers for examples and comparative examples

(2) Trench pattern

Embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Implementation mode one

Fig. 1 is a perspective view schematically showing a polishing pad according to a preferred embodiment of the present invention, and for convenience of explanation, one direction in fig. 1 is referred to as an a direction, the other direction is referred to as a B direction, and a thickness direction of the polishing pad, i.e., a direction perpendicular to a surface of the polishing pad is referred to as a Z direction.

In the first embodiment, the a direction is 90 degrees to the B direction. Referring to FIG. 1, the polishing pad of the present invention is suitable for polishing or planarizing at least one of semiconductor, optical, and magnetic substrates. The polishing layer 110 has a polishing surface 10 and a polishing unit group 20, the polishing unit group 20 is distributed on the polishing surface 10, and the surface of the polishing unit group 20 forms a contact surface directly contacting the material to be ground. The projection of each polishing unit on the contact surface is a quadrangle, preferably a parallelogram such as a rectangle and a rhombus; specifically, the polishing unit group 20 includes an embodiment-one first section 21 and an embodiment-one second section 22, wherein each of the embodiment-one first section 21 and the embodiment-one second section 22 includes at least one polishing unit 23, and the arrangement of the polishing unit group 20 and the size of the polishing unit directly affect the polishing performance of the polishing pad.

Referring to fig. 2, the polishing elements 23 of the first section 21 are uniformly distributed in a direction parallel to the a direction, and define a length of the polishing elements 23 in the a direction as L1 and a length of the polishing elements 23 in the B direction as L2. The interval in the a direction between adjacent polishing elements 23 is defined as W1; the polishing elements 23 of the second portion 22 are also uniformly distributed in a direction parallel to the a direction, and the interval between adjacent polishing elements 23 in the a direction is also W1. As shown in fig. 2, the interval referred to in the present invention means a spacing between adjacent faces of adjacent polishing elements, not a spacing between centers of adjacent polishing elements. The first portion 21 and the second portion 22 both extend along a direction parallel to the direction a and are uniformly distributed, and the distance between the second portion 22 and the first portion 21 in the direction B is defined as W2.

In view of the above dimensions, the preferred L1 range of 10-20 mm; for example, 10mm, 11mm, 12mm, 13mm, 14mm, 15mm, 16mm, 17mm, 18mm, 19mm, or 20mm may be used. Preferably, L2 is in the range of 10-20mm, for example, 10mm, 11mm, 12mm, 13mm, 14mm, 15mm, 16mm, 17mm, 18mm, 19mm, 20mm may be mentioned. Preferably, W1 is in the range of 0.5-5mm, more preferably 0.8-3mm, for example, 0.8mm, 1mm, 1.5mm, 1.6mm, 2mm, 2.5mm, 3mm may be mentioned. Preferably, W2 is in the range of 0.5-5mm, more preferably 0.8-3mm, for example, 0.8mm, 1mm, 1.5mm, 1.6mm, 2mm, 2.5mm, 3mm may be mentioned.

With further reference to fig. 3, polishing element 23 further includes channels 23a, 23B, and a single polishing element 23 has n channels 23a parallel to direction a and m channels 23B parallel to direction B, where m and n are integers, where m + n is greater than or equal to 1, and Nb = m × n if the number of intersections of channels 23a and channels 23B is defined as Nb. The width of the

channels

23a and 23b may be equal or different, and the average width of the channels 23a is defined as Waa, the average width of the channels 23b is defined as Wab, and the average width of the channels refers to the average of the widths of all the channels. Preferably Waa is in the range of 0.15 to 0.6mm, more preferably 0.15 to 0.4 mm. Preferably, the range of Wab is 0.15-0.6mm, more preferably 0.15-0.4 mm.

In the case where the size of the polishing unit 23 is defined as L1, and the interval between L2 and the adjacent polishing unit is defined as W1, W2, the lapping area ratio RS1= (L1 × L2)/((L1+ W1) × (L2+ W2)) is set, which can approximately represent the ratio of the total area of the polishing units 23 to the area of the polishing layer. The above dimensions satisfy the relationship: 0.6 ≦ (L1 × L2)/((L1+ W1) (L2+ W2)) 0.92.

As shown in fig. 3, the effective contact area of the polishing element is lower than the area of the polishing element due to the presence of the channels, and in the polishing element 23, the length of the channel 23a is L1 equal to the length of the polishing element in the a direction, and the length of the channel 23B is L2 equal to the length of the polishing element in the B direction, Waa, Wab, Nb as defined above, and the channel area of the polishing element is calculated as follows: sa = n × Waa × L1+ m × Wab × L2-Nb × Waa × Wab. The invention thus further defines the effective contact area Ss = L1 × L2- (n × Waa × L1+ m × Wab × L2-Nb × Waa × Wab) of the polishing elements.

The effective contact area ratio of the polishing unit 23 RS2= Ss/(L1L 2) sin θ, where θ is 90 °, that is, sin θ is 1, is defined as a ratio in the range of 0.5 to 0.97, preferably in the range of 0.72 to 0.93.

The ratio of the total effective contact area of the polishing layer to the area of the polishing layer was characterized using the effective contact area ratio Ss/((L1+ W1) (L2+ W2) × sin θ). The effective contact area ratio of the polishing layer affects the cooperative action of mechanical polishing and chemical polishing, and is very important to the abrasive performance of the polishing pad. The invention defines that the effective contact area ratio RS3 satisfies the relationship: 50% or more (L1L 2- (n x Waa L1+ m x Wab L2-Nb x Waa Wab))/((L1+ W1) (L2+ W2))/(L1 + W1) or more than 85%. Further, the ratio ranges more preferably from 60% to 70%, for example, ratios such as 62%, 63%, 64%, 65%, 66%, 67%, 68%, 69% and the like may be selected.

Referring to fig. 3, the average height D1 of the polishing elements 23 is defined as the average of the distances from the contact surfaces of the polishing elements 23 to the polishing surface 10 in the Z direction, the depth of the channels is defined as the distance from the channels to the contact surfaces of the polishing elements in the Z direction, and the average depth Da refers to the average depth of the

channels

23a and 23 b.

The width ratio and the volume ratio of the channels formed between the channels of the polishing layer and the polishing units are also important parameters affecting the polishing performance of the polishing pad, and the width ratio of the effective channels is defined as RW4= (n × Waa + m × Wab)/(W1+ W2), and the present invention limits the width ratio to a range of 0.1 to 3.75, more preferably 0.15 to 2. The invention preferably has a D1 range of 0.2 to 0.8 times the thickness of the polishing layer and a Da range of 0.4D1 to D1, more preferably a Da range of 0.4D1 to 0.8D 1. The present invention defines an effective channel volume ratio of RV5= (Sa × Da)/((L1 + W1) ((L2 + W2) -L1 × L2) × D1 × sin θ), which is limited to the range of 0.03 to 3.4, more preferably 0.05 to 0.71.

The number of channels n and m is preferably less than 6, for example n, m may be any one of 1,2,3,4, 5; more preferably, each is independently any of 2,3,4,5, and most preferably, each is independently any of 3,4, 5.

In the above-mentioned parameters of RS1, RS2, RS3, RW4 and RV5, and the preferred sizes, the first channel and the second channel may be uniformly spaced or non-uniformly spaced.

In a preferred embodiment of the present invention, the first channels and the second channels are uniformly distributed at intervals. Referring to fig. 3, the

channels

23a and 23b, which are uniformly spaced, may divide the polishing unit 23 into a plurality of sub-units having the same size. The length of the subunit along the B axis is defined as La, and similarly, the length of the subunit along the a axis is Lb, preferably La ranges from 2mm to 2mm, and preferably Lb ranges from 2mm to 2 mm.

FIG. 4 shows a polishing pad having non-uniform spacing between the first and second channels. Specifically, the first channel and the second channel divide the polishing unit 23 into a plurality of sub-units of different sizes, and under the condition that the sizes L1, L2, the intervals W1, W2, the widths and the numbers Waa, Wab, n, m, Da, D1 of the polishing units are the same as those in the example of fig. 3, the parameters RS1, RS2, RS3, RW4, RV5 are the same, and the polishing pad has good grinding performance as well within the preferred range of the present invention.

In a preferred embodiment of the present invention, the polishing unit is a rectangular parallelepiped or a cube.

In a preferred embodiment of the present invention, the polishing unit is a cube.

In a preferred embodiment of the present invention, the intervals W1 between the polishing units are equal to W2.

As a preferred embodiment of the invention, the polishing units are arranged in a square matrix on the polishing layer, and the center distances of the polishing units are equal, namely L1 is equal to L2, and W1 is equal to W2.

Second embodiment

Similar to the first embodiment, the direction a and the direction B are 90 degrees in the second embodiment. Also, the polishing layer has a polishing surface and polishing unit groups distributed on the polishing surface, and the surfaces of the polishing unit groups are in direct contact with the semiconductor, as shown in fig. 1.

Arrangement pattern of polishing elements of polishing layer referring to fig. 5, the polishing elements 43 of the second first section 41 and the second section 42 are alternately arranged. Preferably, the offset distance is half the side length of the grinding unit in the a direction.

This embodiment is one of the preferred embodiments of the present invention, and also, the polishing unit 43 includes channels thereon, and the size of the polishing unit, the size of the channels, and the number of channels in different directions are as defined in the first embodiment.

Specifically, the polishing elements 43 of the first partial polishing elements 41 are uniformly distributed in parallel to the a direction, defining a length of the polishing elements 43 in the a direction of L1, a length of the polishing elements 43 in the B direction of L2, preferably L1 in the range of 10-20 mm; for example, 10mm, 11mm, 12mm, 13mm, 14mm, 15mm, 16mm, 17mm, 18mm, 19mm, or 20mm may be used. Preferably, L2 is in the range of 10-20mm, for example, 10mm, 11mm, 12mm, 13mm, 14mm, 15mm, 16mm, 17mm, 18mm, 19mm, 20mm may be mentioned. The interval of the adjacent polishing units 43 in the A direction is defined as W1, preferably W1 is in the range of 0.5-5mm, more preferably in the range of 0.8-3mm, and for example, 0.8mm, 1mm, 1.5mm, 1.6mm, 2mm, 2.5mm, 3mm may be preferred. Although the polishing elements 43 are arranged in a staggered manner, the polishing elements of the second portion 42 are also distributed at intervals along the direction a uniformly, i.e. the first portion 41 and the second portion 42 are parallel to each other, so that the interval between the second portion 42 and the first portion 41 in the direction B is defined as W2, preferably as W2, within the range of 0.5-5mm, more preferably within the range of 0.8-3mm, and for example, preferably 0.8mm, 1mm, 1.5mm, 1.6mm, 2mm, 2.5mm, 3 mm.

Similarly, the polishing unit includes a first channel and a second channel, the number m, n and the dimensions Waa, Wab of the channels are defined, and the range of the relevant parameters is as follows:

defining the abraded area ratio RS1= (L1 × L2)/((L1+ W1) ((L2 + W2)), the ratio of the total area of the polishing elements 23 to the area of the polishing layer can be approximately characterized. The above dimensions satisfy the relationship: 0.6 ≦ (L1 × L2)/((L1+ W1) (L2+ W2)) 0.92.

The effective contact area ratio of the polishing unit RS2= Ss/S1, which is defined as a range of 0.5-0.97, more preferably 0.72-0.93.

The polishing layer effective contact area ratio RS3= Ss/((L1+ W1) (L2+ W2) × sin θ), the effective contact area ratio RS3 satisfies the relationship: 50% or more (L1L 2- (n x Waa L1+ m x Wab L2-Nb x Waa Wab))/((L1+ W1) (L2+ W2))/(L1 + W1) or more than 85%. Further, the ratio ranges more preferably from 60% to 70%, for example, ratios such as 62%, 63%, 64%, 65%, 66%, 67%, 68%, 69% and the like may be selected.

The width ratio of the effective channel is RW4= (n × Waa + m × Wab)/(W1+ W2), and the width ratio is limited to a range of 0.1 to 3.75, more preferably a range of 0.15 to 2.

The effective channel volume ratio is RV5= (Sa × Da)/((L1 + W1) × (L2+ W2) -L1 × L2) × D1 × sin θ), and the present invention limits the volume ratio to a range of 0.03 to 3.4, more preferably 0.05 to 0.71.

Other parameters, such as the number of channels: preferably less than 6, for example n, m may each independently be any of 1,2,3,4, 5; more preferably, each is independently any of 2,3,4, 5; most preferably, each is independently any of 3,4, 5; the height of the polishing element; the limiting range of parameters such as the depth of the channel is the same as that described in the first embodiment, and the polishing pad shown in fig. 5 has excellent polishing performance and service life within the limiting range.

In a preferred embodiment of the present invention, L1 of the polishing unit is equal to L2, and W1 is equal to W2.

Third embodiment

The direction a and the direction B may be perpendicular to each other, or may be at other angles, and in the third embodiment, the direction a and the direction B form an angle θ. In the first to second embodiments, the θ angle is 90 degrees; in the third embodiment, the θ angle may be any angle other than 90 degrees, for example, 10 degrees, 20 degrees, 30 degrees, 40 degrees, 45 degrees, 50 degrees, 60 degrees, 70 degrees, 80 degrees, 100 degrees, 110 degrees, 120 degrees, 130 degrees, 135 degrees, 140 degrees, 150 degrees, 160 degrees, 170 degrees, or the like.

Also, referring to fig. 1 in a perspective view, the polishing layer has a polishing surface and polishing unit groups distributed on the polishing surface, the surfaces of the polishing unit groups being in direct contact with the semiconductor.

Referring to fig. 6, the polishing element group includes the third embodiment first section 51 and the third embodiment second section 52, wherein each of the third embodiment first section 51 and the third embodiment second section 52 includes at least one polishing element 53. Fig. 6 shows an arrangement of polishing units 53 of the polishing layer.

The polishing unit includes a channel, and the dimensions of the polishing unit and the channel are defined in the same manner as in the first embodiment. Since the polishing unit is a parallelogram, the area thereof corresponds to:

with continued reference to FIG. 6, the polishing elements 53 are uniformly distributed parallel to the A direction and have a length L1 in the A direction, preferably L1 in the range of 10-20 mm; for example, 10mm, 11mm, 12mm, 13mm, 14mm, 15mm, 16mm, 17mm, 18mm, 19mm, or 20mm may be used. The length of the polishing unit 53 in the B direction is L2, preferably L2 is in the range of 10-20mm, for example, 10mm, 11mm, 12mm, 13mm, 14mm, 15mm, 16mm, 17mm, 18mm, 19mm, 20mm may be preferable. The interval between the adjacent polishing units 23 of the first section 51 and the second section 52 in the a direction is W1, preferably W1 is in the range of 0.5 to 5mm, more preferably in the range of 0.8mm to 3mm, and for example, 0.8mm, 1mm, 1.5mm, 1.6mm, 2mm, 2.5mm, 3mm may be preferred. The second partial polishing unit 52 is spaced apart from the first partial polishing unit 51 in the B direction by W2, and the distance W2 is in the range of 0.5 to 5mm, more preferably in the range of 0.8mm to 3mm, and may be, for example, 0.8mm, 1mm, 1.5mm, 1.6mm, 2mm, 2.5mm, or 3 mm.

Since the polishing unit 53 is a parallelogram, the grinding area S1= L1L 2 sin θ of the polishing unit; the grinding area ratio RS1= (L1 × L2 × sin θ)/((L1+ W1) (L2+ W2) × sin θ) = (L1 × L2)/((L1+ W1) ((L2 + W2)). The above dimensions satisfy the relationship: 0.6% or less (L1 × L2)/((L1+ W1) (L2+ W2)) or less than 0.92.

The number and size of the channels are defined as in the first embodiment, and since the angle between the a direction and the B direction is θ, the channels are also parallelogram. On each polishing element, the first channels have a number n, a width Waa that is the width of the first channel in the B direction, and a length L1; the second channels have the number of m, the width Wab is the width of the second channels in the direction A, the length is L2, the average depth Da, wherein n and m are integers, m + n is more than or equal to 1, the number of intersection points Nb = m n, as mentioned above, the angle between the direction A and the direction B is theta, the channels are also parallelogram, and the area of a single channel is Waa L1 sin theta or Wab L2 sin theta; the intersection point of the channels is also a parallelogram, and the area of the intersection point is Waa Wab sin theta. Therefore, the total area Sa = n × Waa × L1 × sin θ + m × Wab × L2 × sin θ -Nb × Waa × Wab sin θ of the channel.

The effective contact area Ss of the polishing unit is as follows:

Ss=S1-Sa=sinθ*(L1*L2- n*Waa*L1-m*Wab*L2+Nb*Waa*Wab)

the effective contact area ratio RS2= Ss/(L1 × L2) × sin θ = (L1 × L2-n × Waa × L1-m × Wab × L2+ Nb × Waa ×/(L1 × L2), and the present invention defines the ratio in the range of 0.5 to 0.97, more preferably 0.72 to 0.93.

The effective contact area ratio is defined as follows:

RS3=Ss/((L1+W1)*(L2+W2)*sinθ)

= sinθ*((L1*L2- n*Waa*L1-m*Wab*L2+Nb*Waa*Wab))/((L1+W1)*(L2+W2)*sinθ)

= (= L1 × L2-n × Waa × L1-m × Wab × L2+ Nb × Waa × Wab)/((L1+ W1) ((L2 + W2)). The invention defines that the effective contact area ratio RS3 satisfies the relationship: 50% or more (L1L 2- (n x Waa L1+ m x Wab L2-Nb x Waa Wab))/((L1+ W1) (L2+ W2))/(L1 + W1) or more than 85%. Further, the ratio ranges more preferably from 60% to 70%, for example, ratios such as 62%, 63%, 64%, 65%, 66%, 67%, 68%, 69% and the like may be selected.

The effective channel volume ratio is RV5= (Sa × Da)/((L1 + W1) × (L2+ W2) -L1 × L2) × D1 × sin θ) = ((n × Waa × L1 × sin θ + m × Wab × L2 × sin θ -Nb × Wab × sin θ) = Da)/(D1 × (L1+ W1) × (L2+ W2) -L1 × L2) = (n × wa × 1+ m × Wab × L2-Nb = (n × Waa =) × 1)/(363672) is within the range of the invention.

Other parameters, such as the number of channels: preferably less than 6, for example n, m may each independently be any of 1,2,3,4, 5; more preferably, each is independently any of 2,3,4, 5; most preferably, each is independently any of 3,4, 5; the height of the polishing element; the limitation range of parameters such as the depth of the channel is the same as that described in the first embodiment, and the polishing pad shown in fig. 6 has excellent polishing performance and service life within the limitation range.

In a preferred embodiment of the invention, the projection of the polishing elements onto the contact surface is rhomboid.

In a preferred embodiment of the invention, the a direction is at 45 degrees to the B direction.

Embodiment IV

In the fourth embodiment, the a direction and the B direction are at θ degrees, similarly to the third embodiment. The angle θ can be any angle other than 90 degrees, such as 10 degrees, 20 degrees, 30 degrees, 40 degrees, 45 degrees, 50 degrees, 60 degrees, 70 degrees, 80 degrees, 100 degrees, 110 degrees, 120 degrees, 130 degrees, 135 degrees, 140 degrees, 150 degrees, 160 degrees, 170 degrees, and the like. Also, referring to fig. 1 in a perspective view, the polishing layer has a polishing surface and polishing unit groups distributed on the polishing surface, the surfaces of the polishing unit groups being in direct contact with the semiconductor.

Referring to fig. 7, the polishing element group includes an embodiment fourth first section 61 and an embodiment fourth second section 62, wherein each of the embodiment fourth first section 61 and the embodiment fourth second section 62 includes at least one polishing element 63. Fig. 7 shows an arrangement of polishing units 63 of the polishing layer. The polishing units of the first part and the second part of the invention can be distributed in parallel or staggered. As shown in fig. 7, the polishing units 63 of the fourth first section 61 and the fourth second section 62 are staggered, preferably by a distance of half the side length of a diamond.

This embodiment is one of the preferred embodiments of the present invention, and also, the polishing unit 63 includes channels thereon, and the size of the polishing unit, the size of the channels, and the number of channels in different directions are as defined in the first embodiment.

Specifically, the polishing elements 63 of the first portion of polishing elements 61 are uniformly distributed in a direction parallel to the a direction, defining a length of the polishing elements 63 in the a direction of L1; the length of the polishing element 63 in the B direction is L2. The interval in the a direction between adjacent polishing elements 63 is defined as W1; although the polishing elements 63 are arranged in a staggered manner, the second portions 62 are also parallel to the a direction, and the polishing elements are uniformly spaced along the a direction, that is, the first portions 61 and the second portions 62 are parallel to each other, so that the spacing between the second portions 62 and the first portions 61 in the B direction is defined as W2. Preferred ranges of L1, L2, W1 and W2 are the same as in embodiment three.

The range of parameters such as the size, the interval, the size, the number, the area and the like of the polishing units is the same as that of the third embodiment. Therefore, the polished area of the polishing unit S1= L1 × L2 × sin θ, and the polished area ratio RS1= (L1 × L2 × sin θ)/((L1+ W1) (L2+ W2) = (L1 × L2)/((L1+ W1) (L2+ W2)). The above dimensions satisfy the relationship: 0.6 ≦ (L1 × L2)/((L1+ W1) (L2+ W2)) 0.92.

The effective contact area ratio RS2= Ss/(L1 × L2) × sin θ = (L1 × L2-n × Waa × L1-m × Wab × L2+ Nb × Waa ×/(L1 × L2), and the present invention defines the ratio in the range of 0.5 to 0.97, more preferably in the range of 0.72 to 0.93.

Effective contact area ratio Ss/((L1+ W1) ((L2 + W2) × sin θ)

= sinθ*((L1*L2- n*Waa*L1-m*Wab*L2+Nb*Waa*Wab))/((L1+W1)*(L2+W2)*sinθ)

=(L1*L2-n*Waa*L1-m*Wab*L2+Nb*Waa*Wab)/((L1+W1)*(L2+W2))。

The invention defines that the effective contact area ratio RS3 satisfies the relationship: 50% or more (L1L 2- (n x Waa L1+ m x Wab L2-Nb x Waa Wab))/((L1+ W1) (L2+ W2))/(L1 + W1) or more than 85%. Further, the ratio ranges more preferably from 60% to 70%, for example, ratios such as 62%, 63%, 64%, 65%, 66%, 67%, 68%, 69% and the like may be selected.

The width ratio of the effective channel is RW4= (n × Waa + m × Wab)/(W1+ W2), and the width ratio is limited to a range of 0.1 to 3.75, more preferably a range of 0.15 to 2. RV5= ((n × Waa × L1+ m × Wab) × L2-Nb × Waa × wb)/(D1 ((L1+ W1) × (L2+ W2) -L1 × L2)), the present invention limits the volume ratio to a range of 0.03 to 3.4, more preferably to a range of 0.05 to 0.71.

Other parameters, such as the number of channels: preferably less than 6, for example n, m may each independently be any of 1,2,3,4, 5; more preferably, each is independently any of 2,3,4, 5; most preferably, each is independently any of 3,4, 5; the height of the polishing element; the limitation range of parameters such as the depth of the channel is the same as that described in the first embodiment, and the polishing pad shown in fig. 7 has excellent polishing performance and service life within the limitation range.

For the above embodiments one to four, if the L1 or L2 value is less than 10mm, the contact area of the polishing unit is reduced, and the polishing rate is reduced, and if the L1 or L2 value is greater than 20mm, the contact area of the polishing unit is too large, which affects the distribution speed of the polishing liquid in the grooves, and causes scratches. A W1 or W2 value of more than 5mm may cause too fast a flow rate of a polishing liquid or decrease wettability of a polishing pad, and a W1 or W2 value of less than 0.5mm may cause removal of abraded residues inefficiently.

(3) Preparation of polishing pad

The polishing pad of the invention can also be a polishing layer as described above; may further comprise a bottom layer; or a bottom layer and one or more intermediate layers disposed between the polishing layer and the bottom layer. The chemical mechanical polishing of the semiconductor substrate is performed by a polishing layer, and the underlying layer or intermediate layer is not a limitation of the present invention.

It is noted that the polishing layer of the polishing pad of the invention optionally further comprises an endpoint detection window, preferably the detection window is an integrity window incorporated into the polishing layer.

The invention discovers through a great deal of experimental research that the polishing layer is provided with the grooves defined abovePattern with hardness of 40-70D and density of 0.6-0.9g/cm³The polishing pad not only has good polishing rate, defect rate and low non-uniformity, but also effectively reduces dishing and erosion of the wafer. In particular, the polishing layer has a DMA parameter of a storage modulus E' at 40 ℃ of 150-; the energy loss factor KEL is 200-450Pa^-1The overall properties are optimum when the tan delta is from 0.05 to 0.15, preferably from 0.07 to 0.70. The surface roughness Ra of the polishing pad is selected to be in the range of 1-5 um.

Further, different patterning processes were performed using the same material slice, and it was found that the polishing rate, defectivity and non-uniformity of the polishing pad were affected by the groove pattern as follows:

if Waa or Wab is less than 0.15mm, there may be a serious quality problem in the processing of the polishing pad, even scratching the wafer, and if Waa or Wab is more than 0.6mm, the flow rate of the polishing liquid may be too fast to adversely affect the defectivity and the polishing rate.

If the range of RS1 is not in the range of [0.60-0.92], defectivity is adversely affected.

If the RS2 range is not in the [0.5-0.97] range, defectivity and polishing non-uniformity may be adversely affected.

If RS3 is less than 50%, the grinding rate is so severely lost that it cannot be used well for production, and if RS3 is more than 85%, the grinding rate can satisfy the basic requirements, but the scratch problem is remarkably prominent.

The RW4 in the range of [0.1-3.75] can well balance the flow velocity of the large and small channels, thereby improving the distribution of the polishing liquid and the removal efficiency of the waste residue.

n or m is more than 5, which affects the processing quality of the groove and the rigidity of the groove and reduces the utilization capacity of the polishing solution, thereby reducing the grinding quality.

The RV5 is in the range of 0.03-3.4, the whole transport capacity of the polishing solution in the groove and the whole slag discharge capacity of the waste liquid can be reasonably balanced, and the polishing pad has excellent grinding performance.

A semiconductor device is manufactured through a process of polishing the surface of a semiconductor wafer using the polishing pad. The semiconductor wafer is generally a wafer in which a wiring metal and an oxide film are laminated on a silicon wafer. The method for manufacturing a semiconductor device of the present invention includes a step of polishing the surface of a semiconductor wafer using the polishing pad, and the polishing apparatus is not particularly limited.

In general, a polishing apparatus includes a polishing table for supporting a polishing pad, a supporting table for supporting a semiconductor wafer, a backing material for uniformly pressurizing the semiconductor wafer, and a supply mechanism for supplying a polishing liquid, wherein the polishing table and the supporting table are disposed so that the polishing pad supported by the polishing table and the semiconductor wafer to be polished face each other, and the polishing apparatus is configured to rotate the polishing table and the supporting table to press the semiconductor wafer against the polishing pad and to polish the surface of the semiconductor wafer by using the polishing pad while supplying the polishing liquid.

Examples

Code number explanation:

w1: interval length in the a-axis direction between polishing elements (parallelograms), unit: mm;

w2: interval length in the B-axis direction between polishing elements (parallelograms), unit: mm;

l1: length of polishing element (parallelogram) in a-axis direction, unit: mm;

l2: length of polishing element (parallelogram) in B-axis direction, unit: mm;

waa, Wab: the average widths of the first channel and the second channel in the B-axis direction and the A-axis direction respectively are in mm;

n, m: the number of channels in the polishing unit along the A-axis direction and the B-axis direction respectively;

nb: the number of intersections of the channels;

d1: average height of polishing elements in mm;

da: average depth of channels of polishing elements in mm;

RS1：L1*L2 /((L1+W1)*(L2+W2))

RS2： (L1*L2- n*Waa*L1-m*Wab*L2+Nb*Waa*Wab)/L1*L2

RS3： (L1*L2- n*Waa*L1-m*Wab*L2+Nb*Waa*Wab)/((L1+W1)*(L2+W2))

RW4：（n*Waa+m*Wab）/（W1+W2）

RV5：((n*Waa*L1+m*Wab*L2-Nb*Waa*Wab)*Da)/(((L1+W1)*(L2+W2)-L1*L2)*D1)

the method for measuring the physical property parameters comprises the following steps:

hardness (in Shore D scale) and density (g/cm)³) Measured according to astm d2240-05 and astm d1622, respectively. The storage modulus (E'), tan delta and the KEL value are measured by using a dynamic mechanical analyzer at 40 ℃ and 1HZ, the loss factor tan delta represents the damping performance of the material, and the value is the ratio of the loss modulus to the storage modulus; KEL is a function of tan δ and storage modulus (E'), defined as: KEL = tan δ 10¹²/[ E'*(1+ tanδ)]。

The physical property parameters of the different polishing layers in table 1 were measured according to the above measurement method, and the measurement results are shown in table 2:

TABLE 2 physical Properties of different polishing layers

The surface roughness of the polishing layers of all examples and comparative examples was 2.9 um.

Examples are 1-12 and comparative examples are D1-D7.

Grinding parameters and evaluation methods:

the polished wafer was a Cu 10K wafer and the slurry was a diluted (10 fold) solution of ANJI U3061A plus 1% wt H₂O₂The flow rate was 230ml/min, the dresser was a Saesol AK53 diamond disk, the pressure was 6lbf, the polishing head pressure was 2.7psi, the platen speed was 77rpm, the carrier speed was 71rpm, and the polishing time was 30 s.

For the 10 th and 100 th wafers, the polishing rate, polishing non-uniformity and defectivity were measured.

The lapping rate was calculated by measuring the lapping removal at various locations on the wafer over a polishing time using a Nano SpecII tool.

The polishing rate heterogeneity (Nu) was also calculated from the Nano SpecII.

The defectivity is a count of defects on the wafer measured using a KLA-Tencor SP2 analyzer.

Dishing and erosion of the wafer (erosion) were measured by a step profiler (model KLA P-7) and the parameters characterized were the average dishing at 100 x 100 μm line width, the average dishing at 50 x 50 μm line width and the average dishing at 10 x 10 μm line width and the average erosion at 1 x 1 μm line width.

The adhesive buffer layer used for the polishing pad is polyurethane impregnated non-woven fabric with the hardness of 74A, the compressibility of 7 percent and the density of 0.3 g/cm³。

Table 3 groove sample geometry data

Note: the projection surfaces of the contact surfaces of the polishing units of examples 1 to 9 and comparative examples 1 to 7 were rectangular, and the small grooves were uniformly distributed in the polishing unit; example 10, the grinding units are staggered, as shown in fig. 5; example 11, the projection plane of the grinding unit is diamond-shaped, as shown in fig. 6; example 12, the small grooves in the polishing units are unevenly distributed, as shown in fig. 4.

TABLE 4 polishing layer size calculation parameters

TABLE 5 evaluation of polishing Properties

As can be seen from examples 1 to 12, the polishing layers had a hardness of 40 to 70D and a density of 0.6 to 0.9g/cm, according to tables 2 to 5³The polishing pad has a better grinding rate (greater than 5500A/min), a lower defectivity (less than 100) at RS1 of 0.60-0.92, RS2 of 0.5-0.97, and RS3 of 50-85%And, along with lower polishing rate non-uniformity (less than 6%), an average recess (disching) at 100 x 100 μm line width is not higher than 650 a, an average recess (disching) at 50 x 50 μm line width is at and below 601 a, an average recess (disching) at 10 x 10 μm line width is not higher than 600 a; and erosion (oxidation) of 1 x 1 μm line width is within 80 a.

Both the material properties of the polishing layer and the trench pattern have a significant impact on the performance of the polishing pad of the invention, as can be seen from table 4, table 5, examples and comparative examples, the RS3 of comparative example 1 is below 50%, the polishing rate drops significantly, drops below 3000, is less uniform, and has recesses above 1000 a; comparative example 2 had an RS1 of 0.55 below the appropriate range of 0.6-0.92, an RS3 of less than 50%, defect levels rising to 462 (10 sheets) and 478 (100 sheets), with recesses exceeding 900 a. Comparative example 3, RS3 being higher than 85%, resulted in a defect level that was too high, rising to 503 (10 sheets) and 492 (100 sheets), recessed above 800 a. Comparative example 4 has no small channels, a defectivity of nearly 300 a and above, and poor uniformity (9%) with recesses above 700 a. Comparative example 5 has a hardness of 30D, less than the appropriate range of 40-70D, and a density of 0.58 g/cm³Less than the proper range of 0.6-0.9, and other geometric parameters satisfying 0.60-0.92 of RS1, 0.5-0.97 of RS2 and 50-85 of RS3, but the grinding rate, defectivity, dishing and erosion are all not ideal. Comparative example 7 has a hardness of 75D, a maximum value of 70D exceeding the appropriate range, and a density of 1 g/cm³Exceeding a suitable range of 0.9g/cm³The maximum value of (a), the polishing rate, the defectivity, dishing and erosion are all undesirable.

In summary, the polishing layer has a density in the range of 40-70D and a density of 0.6-0.9g/cm³The storage modulus is 150-300MPa, the tan delta is 0.05-0.15, the KEL is 200-450Pa^-1In combination with the preferred geometry described above, the resulting polishing pad performs better.

Through a plurality of experimental researches and creative labor, various factors are comprehensively considered, and the obtained polishing pad which meets the parameter range has the optimal polishing performance. The process of polishing the surface of a semiconductor wafer using the polishing pad and the method of manufacturing a semiconductor device including the process are also within the scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, comprising a step of polishing a surface of a semiconductor wafer with a polishing pad comprising a polishing layer having a hardness of 40 to 70D and a density of 0.6 to 0.9g/cm³(ii) a The polishing layer comprises a polishing surface and polishing units positioned on the polishing surface, the polishing units form a polishing unit group, one end of the polishing unit group forms a contact surface, the contact surface is directly contacted with the ground material, and the projection of each polishing unit on the contact surface is a parallelogram;

S1=L1*L2*sinθ

Sa=n*Waa*L1*sinθ+m*Wab*L2*sinθ-Nb*Waa*Wab*sinθ

the effective contact area Ss of the polishing unit is as follows:

Ss=S1-Sa=sinθ*(L1*L2- n*Waa*L1-m*Wab*L2+Nb*Waa*Wab)

the polishing layer effective contact area ratio RS3 is defined as follows:

RS3=Ss/((L1+W1)*(L2+W2)*sinθ)

the grinding area ratio RS1 is defined as follows:

RS1= L1 × L2/((L1+ W1) × (L2+ W2)), RS1 ranges from 0.60 to 0.92;

RS2= Ss/S1, RS2 ranging from 0.5-0.97.

2. A polishing pad for polishing magnetic, optical and semiconductor substrates, comprising a polishing layer having a hardness of 40 to 70D and a density of 0.6 to 0.9g/cm³(ii) a The polishing layer comprises a polishing surface and polishing units positioned on the polishing surface, the polishing units form a polishing unit group, one end of the polishing unit group forms a contact surface, the contact surface is directly contacted with the ground material, and the projection of each polishing unit on the contact surface is a parallelogram;

S1=L1*L2*sinθ

Sa=n*Waa*L1*sinθ+m*Wab*L2*sinθ-Nb*Waa*Wab*sinθ

the effective contact area Ss of the polishing unit is as follows:

Ss=S1-Sa=sinθ*(L1*L2- n*Waa*L1-m*Wab*L2+Nb*Waa*Wab)

the polishing layer effective contact area ratio RS3 is defined as follows:

RS3=Ss/((L1+W1)*(L2+W2)*sinθ)

the grinding area ratio RS1 is defined as follows:

RS1= L1 × L2/((L1+ W1) × (L2+ W2)), RS1 ranges from 0.60 to 0.92;

RS2= Ss/S1, RS2 ranging from 0.5-0.97.

3. The polishing pad of claim 2, wherein the polishing layer has a hardness of 50-65D and a density of 0.7-0.9g/cm³。

4. The polishing pad of claim 2, wherein the polishing layer has a storage modulus E' at 40 ℃ of 150-300 MPa; the energy loss factor KEL is 200-450Pa-1, and the loss factor tan delta is 0.05-0.15.

5. The polishing pad of claim 2, wherein the polishing layer has a storage modulus E' at 40 ℃ of 180-240 MPa and a loss factor tan δ of 0.07-0.10.

6. The polishing pad of claim 2, wherein the effective contact area ratio RS3 is in the range of 60-70%.

7. The polishing pad of claim 2, wherein the polishing elements have a range of L1 and L2 of 10-20 mm.

8. The polishing pad of claim 2, wherein Waa and Wab range from 0.15 to 0.6 mm.

9. The polishing pad of claim 2, wherein the polishing elements have a W1 and W2 in the range of 0.5-5 mm.

10. The polishing pad of claim 2, wherein the number of first channels is any one of 2-5, and/or the number of second channels is any one of 2-5.

11. The polishing pad of claim 2, wherein the polishing elements are arranged in a square matrix on the polishing layer, and the centers of adjacent polishing elements are equally spaced.