CN112398186B

CN112398186B - Charging circuit, charging chip, terminal and circuit control method

Info

Publication number: CN112398186B
Application number: CN201910758433.6A
Authority: CN
Inventors: 田晨
Original assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Current assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Priority date: 2019-08-16
Filing date: 2019-08-16
Publication date: 2023-01-03
Anticipated expiration: 2039-08-16
Also published as: CN112398186A; WO2021031842A1

Abstract

The application relates to a charging circuit, a charging chip, a terminal and a circuit control method, wherein at least two parallel transistor channels are adopted in a quick charging channel, so that the impedance of the whole quick charging channel can be reduced, the heat productivity of the quick charging channel is reduced, in addition, one switch control circuit is connected to each transistor channel in the charging circuit, before charging equipment to be charged, when one transistor channel in the quick charging channel is controlled to be independently conducted according to the working state of the switch control circuit, whether the transistor channel in the conducting state is normal or not is detected, then the working state of the quick charging channel is controlled according to the detection result, in this way, the heat of the quick charging channel is reduced, the state of the quick charging channel can be detected, the safety of quick charging is greatly improved, the quick charging of electronic equipment can be safely realized, and the heat generated in the charging process of the electronic equipment can also be reduced.

Description

Charging circuit, charging chip, terminal and circuit control method

Technical Field

The application relates to the technical field of quick charging, in particular to a charging circuit, a charging chip, a terminal and a circuit control method.

Background

With the development of electronic technology, electronic devices have become indispensable devices in people's lives, and in order to facilitate user experience, the functions of electronic devices are increasing.

For electronic devices, the more functions the more power is consumed, the faster the power is naturally consumed, and the continuous charging is required. However, busy life and high frequency use of electronic devices have led to higher and higher requirements for the charging time of electronic devices, for example, the charging time of electronic devices is shortened, and the electronic devices can be charged anytime and anywhere. Therefore, rapid charging is a development trend of charging technology. In the existing quick charging technology, various improvements can be made on the quick charging circuit in order to reduce the heating condition of the electronic equipment, but if the improved quick charging circuit has device cold joint or abnormal connection, the quick charging circuit is blocked, the heating condition of charging the electronic equipment is increased, and even danger can occur.

Therefore, how to safely and rapidly charge the electronic device and reduce the heat generated during the charging process of the electronic device is an urgent technical problem to be solved.

Disclosure of Invention

In view of the above, it is necessary to provide a charging circuit, a charging chip, a terminal and a circuit control method, which can solve the technical problems of how to safely and quickly charge an electronic device and reduce heat generation in the charging process of the electronic device.

In a first aspect, an embodiment of the present application provides a charging circuit, where the charging circuit includes: a quick charging path, a conduction control circuit and a switch control circuit; the quick charging path comprises at least two parallel transistor paths; each transistor channel is respectively connected with a switch control circuit; each of the transistor paths includes at least one transistor;

a first pole of a transistor in the transistor path is connected with an energy storage device of the equipment to be charged, and a second pole of the transistor in the transistor path is connected with the charging interface; the control electrode of the transistor in the transistor passage is respectively connected with the switch control circuit and the conduction control circuit;

and the conduction control circuit is used for controlling the conduction state of each transistor channel according to the switching state of the switching control circuit, detecting whether the transistor channel in the conduction state is normal or not when one transistor channel in the quick-charging channels is independently conducted, and controlling the working state of the quick-charging channel according to the detection result.

In one embodiment, the conduction control circuit provides a conduction voltage for the fast charge path when the switch control circuit is turned off, so that the charging current is transmitted to the energy storage device through the fast charge path when the fast charge path is in a conduction state.

In one embodiment, the conduction control circuit is used for controlling one transistor channel in the fast charging channel to be in a conduction state and other transistor channels to be in a cut-off state, detecting the current of the transistor channel in the conduction state, and determining whether the transistor channel in the conduction state is normal or not according to the current.

In one embodiment, the switch control circuit comprises a plurality of parallel switch control sub-circuits, each switch control sub-circuit being connected to a corresponding transistor path; and the conduction control circuit is used for controlling the conduction state of the corresponding transistor access according to the switching state of each switch control sub-circuit.

In one embodiment, the fast charging path includes a first transistor path and a second transistor path; the switch control circuit comprises a first switch control sub-circuit and a second switch control sub-circuit, and a first transistor passage is connected with the first switch control sub-circuit; the second transistor channel is connected with the second switch control sub-circuit;

the conduction control circuit is used for providing conduction voltage for the fast charging path when the first switch control sub-circuit and the second switch control sub-circuit are both switched off, and detecting a first current value passing through the fast charging path at present;

the conduction control circuit is used for providing conduction voltage for the first transistor channel when the first switch control sub-circuit is switched off and the second switch control sub-circuit is switched on, and acquiring a second current value which passes through the first transistor channel; the conduction control circuit is used for providing conduction voltage for the second transistor access when the first switch control sub-circuit is conducted and the second switch control sub-circuit is switched off, and acquiring a third current value passing through the second transistor access;

the conduction control circuit is used for determining that the first transistor channel is normal when the difference value between the first current value and the second current value is smaller than a preset current threshold value; and the conduction control circuit is used for determining that the second transistor is normal when the difference value between the first current value and the third current value is smaller than a preset current threshold value.

In one embodiment, the conduction control circuit is configured to control all transistor paths in the fast charge path to be conducted when each transistor path is normal; and when any one transistor path is abnormal, all the transistor paths in the fast charging path are controlled to be cut off.

In one embodiment, the input end of the conduction control circuit is connected with the charging interface and the clock signal interface, and the output end of the conduction control circuit is connected with the control electrode of the transistor in the transistor channel;

the input end of the switch control circuit is connected with a switch signal end, and the output end of the switch control circuit is connected with the control electrode of the transistor in the transistor channel;

and the conduction control circuit is used for providing conduction voltage for the transistor passage when each switch control circuit is turned off.

In one embodiment, the charging circuit includes a plurality of conduction control circuits, and different conduction control circuits are connected to different transistor paths.

In one embodiment, the conduction control circuit includes a charging signal input unit, a clock signal input unit, and a signal processing unit;

the input end of the charging signal input unit is connected with the charging interface, and the output end of the charging signal input unit is connected with the input end of the signal processing unit; the input end of the clock signal input unit is connected with the clock signal interface, and the output end of the clock signal input unit is connected with the input end of the signal processing unit; the output end of the signal processing unit is connected with the control electrode of the transistor in the transistor channel;

a charging signal input unit for inputting a charging signal to the signal processing unit;

a clock signal input unit for inputting a clock signal to the signal processing unit;

and the signal processing unit is used for providing a conducting voltage for the transistor channel according to the charging signal and the clock signal.

In one embodiment, the charging signal input unit includes a backflow prevention subunit and a filtering subunit; the backflow preventing subunit is used for preventing the charging voltage from flowing backwards; the filtering subunit is used for filtering noise signals entering along with the charging voltage.

In one embodiment, the charging circuit further comprises a protection circuit;

the input end of the protection circuit is connected with a charging interface of the power supply equipment, and the output end of the protection circuit is connected with a control electrode of a transistor in the transistor path;

and the protection circuit is used for preventing the transistor in the transistor path from entering negative voltage.

In one embodiment, the charging circuit further comprises a voltage reduction circuit;

the input end of the voltage reduction circuit is connected with a first electrode of a transistor in the transistor path, and the output end of the voltage reduction circuit is connected with an energy storage device of the equipment to be charged;

the voltage reduction circuit is used for reducing the voltage output by the transistor path.

In a second aspect, the present application provides a charging chip, where the charging chip includes the charging circuit provided in any one of the embodiments of the first aspect.

In a third aspect, the present application provides a terminal including the charging chip provided in the embodiment of the second aspect.

In one embodiment, the distance between the transistor paths in the fast charging path of the terminal is greater than a preset distance threshold.

In one embodiment, if the fast charging path includes a first transistor path and a second transistor path, the first transistor path is disposed on the circuit board main board region of the terminal, and the second transistor path is disposed on the circuit board cell region of the terminal.

In a fourth aspect, the present application provides a circuit control method, which is applied to the charging circuit in any one of the embodiments of the first aspect, and includes:

controlling the conduction state of each transistor channel according to the switching state of the switching control circuit, and detecting whether each transistor channel in the conduction state is normal or not when each transistor channel in one channel of the quick charging channels is independently conducted;

controlling the working state of the quick charging passage according to the detection result; the quick charging path at least comprises two parallel transistor paths, and each transistor path is respectively connected with the switch control circuit.

In one embodiment, the controlling the conduction state of each transistor path through the switch control circuit, and detecting whether each transistor path is normal when each transistor path is separately conducted includes:

and sequentially controlling one transistor channel in the quick charging channels to be switched on and the other transistor channels to be switched off, detecting the current passing through each transistor channel, and determining whether each transistor channel is normal or not according to the current.

then, sequentially controlling one of the transistor paths in the fast charging path to be switched on and the other transistor paths to be switched off, detecting the current passing through each transistor path, and determining whether each transistor path is normal according to the current, including:

when the first switch control sub-circuit and the second switch control sub-circuit are both turned off, providing a conducting voltage for the fast charging path, and detecting a first current value passing through the fast charging path at present;

when the first switch control sub-circuit is turned off and the second switch control sub-circuit is turned on, providing a turn-on voltage for the first transistor channel and acquiring a second current value passing through the first transistor channel; when the first switch control sub-circuit is switched on and the second switch control sub-circuit is switched off, providing a switching-on voltage for the second transistor access, and acquiring a third current value passing through the second transistor access;

when the difference value between the first current value and the second current value is smaller than a preset current threshold value, determining that the first transistor is normal in passage; and when the difference value between the first current value and the third current value is smaller than a preset current threshold value, determining that the second transistor is normal.

In one embodiment, the controlling the operating state of the fast charging path according to the detection result includes:

if all the transistor paths are normal, all the transistor paths in the quick charging path are controlled to be conducted;

and if any one transistor channel is abnormal, controlling all the transistor channels in the quick charge channel to be cut off.

According to the charging circuit, the charging chip, the terminal and the circuit control method, at least two parallel transistor paths are adopted in the quick charging path, so that the impedance of the whole quick charging path can be reduced, the heat productivity of the quick charging path is reduced, in addition, each transistor path is connected with one switch control circuit, before the equipment to be charged is charged, when one transistor path in the quick charging path is controlled to be independently conducted according to the working state of the switch control circuit, whether the transistor path in the conducting state is normal or not is detected, and then the working state of the quick charging path is controlled according to the detection result, so that the heat of the quick charging path is reduced, the state of the quick charging path can be detected, the safety of quick charging is greatly improved, the safe quick charging of the electronic equipment is realized, and the heat productivity of the electronic equipment in the charging process can be reduced.

Drawings

Fig. 1 is a block diagram of an application environment of a charging circuit according to an embodiment;

FIG. 2 is a schematic diagram of a charging circuit according to an embodiment;

FIG. 3 is a schematic diagram of a charging circuit according to an embodiment;

FIG. 3a is a diagram illustrating a general charging process according to an embodiment;

FIG. 4 is a schematic diagram of a charging circuit according to an embodiment;

FIG. 5 is a schematic diagram illustrating a testing process of a charging circuit according to an embodiment;

FIG. 6 is a schematic diagram of a charging circuit, according to one embodiment;

FIG. 7 is a schematic diagram of a charging circuit according to an embodiment;

FIG. 8 is a schematic diagram of a charging circuit according to an embodiment;

FIG. 9 is a schematic diagram of a charging circuit according to an embodiment;

fig. 10 is a block diagram of a terminal according to an embodiment;

fig. 11 is a block diagram of a charging system according to an embodiment;

FIG. 12 is a schematic diagram of a circuit control method according to an embodiment;

fig. 13 is a schematic diagram of a circuit control method according to an embodiment.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of and not restrictive on the broad application.

Fig. 1 shows a schematic circuit diagram of a conventional fast charging technology, which includes a Micro Control Unit (MCU) 01, an Application Processor (AP) 02, a battery 03, a MOS transistor 04, a driving circuit 05, a USB socket 06, a data line 07, and an adapter 08. The driving voltage generated by the driving circuit 05 in fig. 1 is the superposition of the voltage VBUS output by the adapter 08 and the voltage VCLK output by the MCU01, wherein the driving circuit 05 is controlled by the MCU01 to control the on/off of the MOS transistor 04, so as to realize the entry and exit of the fast charge. In order to reduce the heat generation of the existing fast charge path, a fast charge current can be shunted by increasing the fast charge path, so that the temperature rise of a path device is reduced, the design requirement on path impedance can be reduced, and the design difficulty is reduced, for example, the line width and the line diameter can be reduced. However, the way of increasing the fast charging paths is that each fast charging path is designed according to the standard of half of the total current, and once one fast charging path fails due to device cold joint or abnormal connection, all the current flows to the other remaining path, so that the other path heats seriously and even is in danger of overheating.

The present application thus provides an embodiment of a charging circuit, as shown in fig. 2, the charging circuit comprising: a quick charging path 10, a conduction control circuit 11 and a switch control circuit 12; the quick charging path 10 comprises at least two parallel transistor paths 101; each transistor path 101 is connected to the switch control circuit 12; each transistor path includes at least one transistor; a first pole of the transistor in the transistor path is connected with an energy storage device V1 of the equipment to be charged, and a second pole of the transistor in the transistor path is connected with a charging interface V2; the control electrodes of the transistors in the transistor paths are respectively connected with the switch control circuit 12 and the conduction control circuit 11; and the conduction control circuit 11 is configured to control the conduction state of each transistor path according to the switching state of the switch control circuit 12, detect whether the transistor path in the conduction state is normal when one of the transistor paths in the fast charging path is separately conducted, and control the working state of the fast charging path 10 according to the detection result.

In this embodiment, the device to be charged represents an electronic device that needs to be charged, for example, various personal computers, notebook computers, smart phones, tablet computers, portable wearable devices, and the like. The energy storage device V1 of the device to be charged represents an energy storage device of an electronic device that needs to be charged, such as a rechargeable battery of the electronic device or the like. The charging interface V2 is an interface that can be connected to a power supply device when the device to be charged is charged, where the power supply device may include a power adapter, a charger, and the like, which is not limited in this embodiment.

In the charging circuit, the charging circuit comprises a working state and a non-working state, wherein when the charging circuit is in the working state, the quick charging channel is required to be in a conducting state, and the charging of the equipment to be charged can be realized when the quick charging channel is in the conducting state. Optionally, a fast charging path conduction mode is provided, and the conduction control circuit 11 provides a conduction voltage for the fast charging path 10 when the switch control circuit 12 is turned off; when the quick charging path 10 is in a conducting state, after the power supply equipment is connected with the charging interface V2, the current is transmitted to the energy storage device through the quick charging path 10. In the embodiment, each transistor access is connected to the switch control circuit, and in practical application, a low level signal needs to be provided to the switch control circuit connected to the control electrode of the transistor access to turn off the switch control circuit, and at this time, the on control circuit can provide on voltage to each transistor access to enable each transistor access to be in an on state. In this way, the conduction control circuit can provide conduction voltage for the transistor paths connected with the switch control circuits when each switch control circuit is turned off, so that all the transistor paths in the quick charge path can be conducted under the conduction voltage of the conduction control circuit, the power supply equipment transmits current to the energy storage device through the quick charge path, and the charging of the equipment to be charged is completed.

Optionally, as shown in fig. 3, in order to include a first transistor M1 and a second transistor M2 in a transistor path, a first pole of the first transistor M1 is connected to the energy storage device V1 of the device to be charged, and a second pole of the first transistor M1 is connected to a second pole of the second transistor M2; a first electrode of the second transistor M2 is connected with a charging interface V2; the control electrode of the first transistor M1 and the control electrode of the second transistor M2 are connected to the switch control circuit 12.

Wherein each transistor path comprises a first transistor and a second transistor; then, when the fast charging path is turned on, all parallel transistor paths are required to be turned on, that is, the first transistor and the first transistor in each transistor path are required to be turned on, as shown in fig. 3, in each transistor path, a first pole of the first transistor is connected to the energy storage device of the device to be charged, and a second pole of the first transistor is connected to a second pole of the second transistor; the first electrode of the second transistor is connected with the charging interface; therefore, when the first transistor and the second transistor are turned on, a low-level signal needs to be provided to the switch control circuit connected with the control electrodes of the first transistor and the second transistor to turn off the switch control circuit.

Wherein, among this charging circuit, constitute the route of filling soon through parallelly connected transistor access, can reduce the impedance of the route of filling soon, and adopt at least two parallelly connected transistor access of way, also increased heat radiating area when having increased the quantity of transistor, make the heat reduction of the whole route of filling soon more, and then the heat that can reduce the complete machine greatly. For example, the impedance of a single transistor is R, and the impedance of one transistor path is 2 × R, then the impedance of two parallel transistor paths is R, which is equivalent to that the two parallel transistor paths are used in the fast charging path to replace the original one transistor path, so that the total heat generation amount of the fast charging path can be changed from I × 2 × R to I × R, and thus, the total heat generation amount is reduced to half of the previous one, and the heat amount of the whole fast charging path is reduced more.

Considering that if there is a transistor path abnormality in the fast charge path, that is, there is a situation that the transistor path cannot be turned on, at this time, the charging current of the fast charge path becomes abnormal, which causes serious heat generation of the fast charge path, and may even cause danger, in the charging circuit shown in fig. 3, the turn-on control circuit may detect whether each transistor path is normal by controlling the turn-on state of each transistor path, and control the operating state of the fast charge path according to the detection result. Optionally, the conduction control circuit is used for controlling the conduction of the quick charging path if each transistor path is normal; and if any one transistor channel is abnormal, controlling the quick charge channel to be cut off. Equivalently, when the conduction control circuit detects that all transistor channels in the quick charge channel are normal, the conduction control circuit provides conduction voltage for the quick charge channel, so that the quick charge channel is conducted to realize the charging of the equipment to be charged. If any transistor channel is abnormal in the fast charging channel, the fast charging channel is controlled to be cut off, and at this time, if the device to be charged needs to be charged, the device to be charged is switched to normal charging, for example, as shown in fig. 3a, a normal charging schematic diagram is provided, when the device to be charged is switched to normal charging, the output voltage is adjusted by controlling the switching duty ratio and the frequency of the transistor MOSFET1 and the transistor MOSFET2 through the controller, and the VBUS voltage is reduced to the VBAT voltage (where VBUS > VBAT), so as to achieve the purpose of charging the battery. Wherein, and this application fast charge route compares in this ordinary charging mode, does not set up transistor MOSFET2 and inductance L in the circuit diagram, then VBUS and VBAT just directly connect through transistor MOSFET1, and at this moment, VBUS approximately equals VBAT voltage, is equivalent to not stepping down VBUS voltage, and it is just not efficient loss not to have the step-down to improve charge efficiency.

The charging circuit provided by the embodiment can reduce the impedance of the whole quick charging path due to the fact that at least two parallel transistor paths are adopted in the quick charging path, and therefore the heat productivity of the quick charging path is reduced.

For a specific implementation manner of detecting whether each transistor path is normal, the present application provides an embodiment, where the conduction control circuit 11 is configured to control one of the transistor paths 101 in the fast charging path 10 to be in a conduction state, and the other transistor paths 101 are all in a cut-off state, detect a current of the transistor path 101 in the conduction state, and determine whether the transistor path 101 in the conduction state is normal according to the current.

When detecting whether each transistor channel is normal, the conduction control circuit can sequentially and respectively control one transistor channel to be conducted, and when other transistor channels are in an off state, the current passing through each transistor channel can determine whether the transistor channel corresponding to the current is normal or not according to the magnitude of the current.

A specific detection scheme is provided, as shown in fig. 4, optionally, in an embodiment, if the fast charging path 10 includes a first transistor path 101 and a second transistor path 102; the switch control circuit 12 comprises a first switch control sub-circuit 121 and a second switch control sub-circuit 122, the first transistor path 101 being connected to the first switch control sub-circuit 121; the second transistor path 102 is connected to the second switch control sub-circuit 122; the conduction control circuit 11 is configured to provide a conduction voltage for the fast charge path 10 when both the first switch control sub-circuit 121 and the second switch control sub-circuit 122 are turned off, and detect a first current value I1 currently passing through the fast charge path 10; the first current value I1 is less than or equal to the maximum bearing current of each transistor channel; the conduction control circuit 11 is configured to provide a conduction voltage for the first transistor path 101 when the first switch control sub-circuit 121 is turned off and the second switch control sub-circuit 122 is turned on, and obtain a second current value I2 currently passing through the first transistor 101 path; or, when the first switch control sub-circuit 121 is turned on and the second switch control sub-circuit 122 is turned off, the on-control circuit 11 provides an on-voltage for the second transistor path 102, and obtains a current value I3 of the third current passing through the second transistor path 102; when the difference value between the first current value I1 and the second current value I2 is smaller than a preset current threshold value, the conduction control circuit determines that the first transistor passage 101 is normal; alternatively, the conduction control circuit 11 determines that the second transistor path 102 is normal when the difference between the first current value I1 and the third current value I3 is smaller than the preset current threshold.

When the conduction control circuit starts to perform quick charging on the equipment to be charged, and the first switch control sub-circuit and the second switch control sub-circuit are both in an off state, the conduction control circuit respectively and simultaneously provides conduction voltages for the first transistor access and the second transistor access, namely, two transistor accesses in the quick charging access are both conducted at the moment, and the conduction control circuit detects a first current value passing through the quick charging access at present. It should be noted that, the magnitude of the on-voltage provided by the on-control circuit needs to be controlled, and after the on-voltage is applied to each transistor path, the first current value generated by each transistor path cannot be greater than the maximum current carried by each transistor path, so that it can be ensured that each transistor path is not burned out in the charging process.

For example, in practical applications, the turn-on control circuit may provide a smaller turn-on voltage for the first transistor path and the second transistor path, and then detect the current passing through each transistor path at that time, or detect the current passing through the entire fast-charging path at that time. After the conduction control circuit detects the first current value, when the first switch control sub-circuit is turned off and the second switch control sub-circuit is turned on, only the same conduction voltage is provided for the first transistor path, wherein the same conduction voltage indicates the same conduction voltage provided for the first transistor path and the second transistor path at the same time, and the second current value currently passing through the first transistor path is detected. And on the basis of the detected first current value and the second current value, the conduction control circuit calculates the difference value between the first current value and the second current value, and if the difference value between the first current value and the second current value is smaller than a preset current threshold value, the first transistor channel is determined to be normal. The preset current threshold represents a range of values, such as 0.2A and 0.5A, in which the current is allowed to vary, and may be determined according to actual situations. After the first transistor channel is detected, the second transistor channel is detected by the same method, namely when the first switch control sub-circuit is switched on and the second switch control sub-circuit is switched off, the same switching-on voltage is only provided for the second transistor channel, a third current value passing through the second transistor channel is detected, whether the difference value between the first current value and the third current value is smaller than a preset current threshold value or not is compared, and if the difference value is smaller than the preset current threshold value, the second transistor channel is normal. When the conduction control circuit switches the two transistor paths to one transistor path to be conducted, under normal conditions, the current of the transistor path and the current of the transistor paths should not change greatly, that is, the current and the current of the transistor paths can change slightly. For example, as shown in the flowchart of fig. 5, at each stage of fast charge and fast charge path opening, a small current (2A) is provided for the fast charge path to perform charging, then the transistor path 2 is closed, only the transistor path 1 is left to be opened, and whether the difference between the current charging current and the current charging current 2A is smaller than a preset current threshold value of 0.5 is determined, which is equivalent to determining whether the current charging current is smaller than 1.5, if smaller than 1.5, it indicates that the charging current of the fast charge path is much smaller after the transistor path 2 is closed, and the charging current is the current of the current transistor path 1, which indicates that the transistor path 1 is abnormal, and the fast charge is to be stopped to ensure safety; if the current is larger than 1.5, it means that the charging current of the fast charging path is not too small, and the variation is within the normal range, which means that the transistor path 1 is normal. Similarly, the transistor path 2 is continuously tested, and if the transistor path 1 and the transistor path 2 are both normal, the rapid charging is continuously carried out on the equipment to be charged. In the embodiment, the conduction control circuit is used for detecting the normality or abnormality of each transistor channel in the quick charge channel at the quick charge starting stage, the quick charge channel is indicated to be normal only under the condition that all the transistor channels are normal, otherwise, the quick charge channel is considered to be abnormal.

In the following description, the conduction control circuit in the above charging circuit is described, and it should be noted that the following embodiments each describe an example in which two transistors, i.e., a first transistor and a second transistor, are included in a transistor path. In one embodiment, as shown in fig. 6, the input terminal of the turn-on control circuit 11 is connected to the charging interface V2 and the clock signal interface SW, and the output terminal of the turn-on control circuit is connected to the control electrodes of the first transistor M1 and the second transistor M2 in the transistor path; the input end of the switch control circuit 12 is connected with a switch signal end SW, and the output end of the switch control circuit 12 is connected with the control electrodes of a first transistor M1 and a second transistor M2 in a transistor passage; and a turn-on control circuit 11 for providing a turn-on voltage to the transistor paths when each switch control circuit 12 is turned off.

In this embodiment, the clock signal interface and the switch signal interface may be both disposed on the controller of the device to be charged, and when the controller detects that the external power supply device charges the energy storage device through the charging interface, the controller outputs the clock signal from the clock signal interface, and outputs the switch signal from the switch signal end. The controller is a hardware device for providing a clock signal and a switch signal, the clock signal output by the controller is sent to the conduction control circuit, the switch signal output by the controller is sent to the switch control circuit, and the controller can be an existing controller in the device to be charged or a specially-arranged controller. The clock signal interface and the switch signal interface may also be disposed at other positions, which are not limited in the embodiments of the present application and may be set according to actual situations. When the charging circuit is in a non-working state, the switch control circuit receives a switch signal and is switched on, so that the control electrodes of the first transistor and the second transistor are grounded, at the moment, the grid voltage of the first transistor and the grid voltage of the second transistor are 0V, the first transistor and the second transistor are both switched off, namely, the transistor paths are switched off, each transistor path is formed by at least two parallel transistor paths, and at the moment, the whole quick-charging path is also in a switched-off state. When the charging circuit is in a working state, the switch control circuit receives the switch signal and is turned off, then the switch control circuit provides a switch-on voltage for the first transistor and the second transistor when the switch control circuit is turned off, the first transistor and the second transistor are both switched on, namely, the transistor is switched on, the whole quick charging circuit is also in a switch-on state, and then the external power supply equipment can charge the energy storage device through the quick charging circuit through the charging interface. In this embodiment, the parallel transistor paths can reduce the impedance of the whole fast charging path, so that the heat of the charging circuit can be reduced.

In addition, according to actual conditions, there is a scenario that an independent conduction control circuit may be connected to each transistor path in the fast charging path 10, so as to facilitate individual control of each transistor path. If different transistor paths are connected with different conduction control circuits, the connection mode is the same as that described above, namely the input end of each conduction control circuit is connected with the charging interface and the clock signal interface, and the output end of each conduction control circuit is connected with the control electrodes of the first transistor and the second transistor in the corresponding transistor paths, so that the transistor paths can be conveniently controlled.

Based on the above embodiments, the present application provides an internal embodiment of a conduction control circuit, and as shown in fig. 7, the conduction control circuit 11 includes a charging signal input unit 111, a clock signal input unit 112, and a signal processing unit 113; the input end of the charging signal input unit 111 is connected with the charging interface V2, and the output end is connected with the input end of the signal processing unit 113; the input end of the clock signal input unit 112 is connected with the clock signal interface CLK, and the output end is connected with the input end of the signal processing unit 113; the output terminal of the signal processing unit 113 is connected to the control electrodes of the first transistor M1 and the second transistor M2 in the transistor path 101; a charging signal input unit 111 for inputting a charging signal to the signal processing unit 113; a clock signal input unit 112 for inputting a clock signal to the signal processing unit 113; a signal processing unit 113 for providing the transistor path 101 with a turn-on voltage in dependence of the charging signal and the clock signal.

In this embodiment, when the charging circuit is in an operating state, the charging signal input unit receives the charging signal and then transmits the charging signal to the signal processing unit. When the charging circuit is in a non-working state, the external power supply equipment does not input a charging signal through the charging interface, and the charging signal input unit does not work. The charging circuit comprises a charging unit, a clock signal input unit, a signal processing unit and a charging circuit, wherein the input end of the clock signal input unit is connected with a clock signal interface, the output end of the clock signal input unit is connected with the input end of the signal processing unit, the clock signal input unit receives a clock signal and inputs the clock signal to the signal processing unit when the charging circuit is in a working state, and the clock signal input unit does not work when the charging circuit is in a non-working state. When the charging circuit is in a working state, the signal processing unit receives the charging signal and the clock signal, processes the charging signal and the clock signal, and inputs the processed signals to the control electrodes of the first transistor and the second transistor, so that on-state voltage is provided for the first transistor and the second transistor. When the charging circuit is in a non-working state, the signal processing unit does not receive the charging signal and the clock signal, and the signal processing unit does not work. In this embodiment, the transistor path in the fast charging path is controlled to be turned on and off by the charging signal input unit, the clock signal input unit, and the signal processing unit, so that the normal operation of the whole fast charging path is controlled, and the fast charging of the device to be charged is effectively realized.

The charging signal input unit comprises a backflow prevention subunit and a filtering subunit; the backflow preventing subunit is used for preventing the charging voltage from flowing backwards; the filtering subunit is used for filtering noise signals entering along with the charging voltage. The input end of the backflow preventing subunit is connected with the output end of the filtering subunit, and the output end of the backflow preventing subunit is connected with the input end of the signal processing unit; the input end of the filtering subunit is connected with the charging interface. Alternatively, as shown in fig. 8, the charging signal input unit 111 includes a first resistor R1, a first diode D1, and a first capacitor C1; one end of the first resistor R1 is connected with the charging interface V2, and the other end of the first resistor R1 is connected with the anode of the first diode D1 and one end of the first capacitor C1; the cathode of the first diode D1 is connected to the input terminal of the signal processing unit 113; the other end of the first capacitor C1 is grounded. Optionally, the clock signal input unit 112 includes a second capacitor C2; one end of the second capacitor C2 receives the clock signal, and the other end is connected to the input end of the signal processing unit 113. Optionally, the signal processing unit 113 includes a second diode D2, a second resistor R2, a third capacitor C3, and a third resistor R3; an anode of the second diode D2 is connected to the output terminal of the charging signal input unit 111 and the output terminal of the clock signal input unit 112, and a cathode thereof is connected to one end of the second resistor R2 and one end of the third capacitor C3; the other end of the second resistor R2 is connected with the control electrodes of the first transistor M1 and the second transistor M2; the other end of the third capacitor C3 is grounded; one end of the third resistor R3 is connected to the control electrodes of the first transistor M1 and the second transistor M2 in the transistor path 101, and the other end is grounded.

In this embodiment, when the charging circuit is in an operating state, the external power supply device inputs a charging voltage input through the charging interface from one end of the first resistor, and the charging voltage is added to the node J1 through the first diode, that is, a charging signal is input to the signal processing unit. The first diode D1 is used for preventing backflow, and the first resistor R1 and the first capacitor C1 form a filter circuit, so that noise signals input along with the charging voltage can be filtered. When the charging circuit is in an operating state, a clock signal is input from one end of the second capacitor C2, and the other end of the second capacitor C2 is applied to the node J1, that is, the clock signal is input to the signal processing subunit 1113. Wherein the second capacitor C2 functions as an energy storage filter. The anode of the second diode D2 is connected to the node J1, and the cathode is connected to one end of the second resistor R2 and one end of the second capacitor C2. When the charging circuit is in an operating state, the charging signal at the node J1 and the clock signal are input from the anode of the second diode D2 and are subjected to superposition processing, so as to obtain a processed signal. Then, the processed signal is applied to the node J2 through the second resistor R2, i.e., the first transistor M1 and the second transistor M2 are provided with a turn-on voltage, so that the first transistor M1 and the second transistor M2 are turned on. Through the charging circuit provided by the embodiment, the transistor channel can be effectively controlled to be switched on and switched off, and the quick charging of the equipment to be charged is realized.

The switch control circuit comprises a plurality of switch control sub-circuits connected in parallel, and each switch control sub-circuit is connected with a corresponding transistor access; the conduction control circuit is used for controlling the conduction state of the corresponding transistor access through each switch control sub-circuit; the internal structures of all the switch control sub-circuits are the same, and the switch control sub-circuits form a switch control circuit. With regard to the internal structure of each switch control sub-circuit, continuing to refer to fig. 8, the present application provides an embodiment wherein each switch control sub-circuit includes a third transistor M3 and a third diode D3; a control electrode of the third transistor M3 is connected to the switch signal end, a source electrode of the third transistor M3 is connected to an anode electrode of the third diode D3, and a drain electrode of the third transistor M3 is connected to control electrodes of the first transistor M1 and the second transistor M2 in a transistor path corresponding to the switch control sub-circuit; the cathode of the third diode D3 is grounded.

In this embodiment, the control electrode of the third transistor M3 is connected to the switch signal terminal SW. When the charging circuit is in a working state, the third transistor M3 is turned off by the switch signal output by the switch signal terminal SW, the conduction control unit 111 provides conduction voltage for the first transistor M1 and the second transistor M2, and after the first transistor M1 and the second transistor M2 are both turned on, the external power supply equipment starts to charge the energy storage device V1 through the charging interface V2. When the charging circuit is in a non-working state, the third transistor M3 is turned on by the switch signal output by the switch signal terminal SW, because the source of the third transistor M3 is grounded through the third diode D3, and the drain of the third transistor M3 is connected to the control electrode of the second transistor M2, when the third transistor M3 is turned on, the drain voltage of the third transistor M3 is 0V, the control voltages of the first transistor M1 and the second transistor M2 are 0V, that is, the first transistor M1 and the second transistor M2 are turned off, the quick charging circuit is turned off, and at this time, the external power supply device does not charge the energy storage device V1 through the charging interface V2. The charging circuit provided by the embodiment can effectively control the on and off of the quick charging path.

In one embodiment, as shown in fig. 9, the charging circuit further includes a protection circuit 13, wherein an input end of the protection circuit 13 is connected to the charging interface V2, and an output end is connected to control electrodes of the first transistor M1 and the second transistor M2 in the transistor path 101, for preventing transistors in the transistor path from entering a negative voltage. Optionally, as shown in fig. 9, the protection circuit 13 includes a fourth transistor M4, a fifth transistor M5, and a fourth resistor R4; a control electrode of the fourth transistor M4 is connected to a control electrode of the fifth transistor M5 and one end of the fourth resistor R4, a source electrode of the fourth transistor M4 is connected to the charging interface V2, and a drain electrode of the fourth transistor M4 is connected to a drain electrode of the fifth transistor M5; the source of the fifth transistor M5 is connected to the control electrodes of the first transistor M1 and the second transistor M2 in the transistor path 101; the other end of the fourth resistor R4 is grounded.

In this embodiment, the protection circuit is used to prevent the transistor in the transistor path from entering a negative voltage, that is, the protection unit 13 can prevent the negative voltage from being input to the first transistor M1 and the second transistor M2, and avoid damage to the first transistor M1 and the second transistor M2. Specifically, when the external power supply device inputs negative voltage through the charging interface V2, the fourth transistor M4 and the fifth transistor M5 are turned on, and the negative voltage is prevented from being input to the control electrode of the second transistor M2. Thus, the protection unit can protect the first transistor M1 and the second transistor M2, i.e., protect the whole fast charging path, and further protect the whole charging circuit.

In addition, the charging circuit further comprises a voltage reduction circuit; the input end of the voltage reduction circuit is connected with a first electrode of a transistor in the transistor passage, and the output end of the voltage reduction circuit is connected with an energy storage device of the equipment to be charged; the voltage reduction circuit is used for reducing the voltage output by the transistor path. For example, the architecture of the voltage reducing circuit may be a buck architecture circuit, and may also be a voltage reducing circuit of an LDO (Low dropout regulator) architecture, which is not limited in this embodiment.

The first pole and the second pole of the transistor mentioned in the above embodiments, the present application provides an embodiment, if the first pole of the first transistor M1 is the source, the second pole of the first transistor M1 is the drain; if the first pole of the second transistor M2 is the source, the second pole of the second transistor M2 is the drain. Optionally, in another embodiment, if the first pole of the first transistor M1 is the drain, the second pole of the first transistor M1 is the source; if the first pole of the second transistor M2 is the drain, the second pole of the second transistor M2 is the source. The drain of the first transistor M1 is connected to the energy storage device V1, the source of the first transistor M1 is connected to the source of the second transistor M2, and the drain of the second transistor M2 is connected to the charging interface V2; or the source of the first transistor M1 is connected to the energy storage device V1, the drain of the first transistor M1 is connected to the drain of the second transistor M2, and the source of the second transistor M2 is connected to the charging interface V2. The control circuit 11 provides a conduction voltage for the first transistor M1 and the second transistor M2, the first transistor M1 and the second transistor M2 are both turned on, and the external power supply equipment is charged for the energy storage device V1 through the first transistor M1 and the second transistor M2 through the charging interface V2. Optionally, as shown in fig. 1, the first transistor M1 and the second transistor M2 are both NMOS transistors.

Through the description of the above embodiments, it is understood that in the embodiments of the present application, by increasing the number of parallel paths of transistor paths and placing the parallel paths at different positions, the path impedance can be effectively reduced, and the problem of heat generation of electronic devices can be reduced. In addition, when the electronic heating is reduced, the conduction detection is carried out on each transistor channel in the quick charge channel at the conduction stage of the quick charge channel, so that the safe operation of quick charge is ensured.

Based on the charging circuit provided above, the present application further provides a charging chip, which includes the charging circuit provided in any of the above embodiments. That is, any one of the charging circuits provided in the above embodiments may be applied to the charging chip, where the charging chip may be applied to any electronic device, so as to implement fast charging of the electronic device.

As shown in fig. 10, an embodiment of the present application further provides a terminal 12, where the terminal 12 includes the charging circuit provided in the foregoing embodiment, or further includes a charging chip manufactured by the charging circuit, and optionally, a distance between transistor paths in a fast charging path of the terminal is greater than a preset distance threshold. Alternatively, if the fast charging path includes the first transistor path 101 and the second transistor path 102, the first transistor path 101 is disposed in a board main area 13 of the terminal, and the second transistor path 102 is disposed in a board sub-area 14 of the terminal, where the board main area 13 and the board sub-area 14 are located at different positions of the terminal, for example, the board main area may be a circuit board equipped with a core chip such as a processor and a communication module, and the small board may be a sub-board of the board, for example, the small board may be used to connect a speaker and a receiver to the board.

In practical applications, the charging circuit in the above embodiment may be manufactured as a chip and applied to any kind of terminal, where the terminal is an electronic device that needs to use electricity, and when the charging circuit is applied to the terminal, a distance between each transistor path in the fast charging path of the charging circuit may be greater than a preset distance threshold, and the distance between each transistor path is not limited in this embodiment, and may be a distance calculated by using a center point of each transistor path as a standard, or a distance calculated by using an edge as a standard, and may be determined according to practical applications, as long as it is ensured that each transistor path is dispersedly disposed in the terminal. Optionally, the quick charge path of the terminal is set to include two parallel transistor paths, that is, the quick charge path includes a first transistor path and a second transistor path, the first transistor path is disposed in the main board area of the circuit board of the terminal, and the second transistor path is disposed in the small main board area of the circuit board of the terminal, so that the transistor paths are dispersedly disposed in the terminal, heat generated by the quick charge path can be effectively dispersed, and heat of the terminal is further reduced.

As shown in fig. 11, in another embodiment, the present embodiment provides a charging system 15, the charging system 15 including a power adapter 17 and a terminal 12 as in the above embodiments; the power adapter charges the terminal through the USB port 121 of the terminal.

In this embodiment, the charging interface of the terminal is a USB port, and the first electrode of the second transistor M2 of the charging circuit may be connected to the power adapter through the USB port, so that the power adapter charges the terminal. The charging system comprises a terminal and a power adapter, wherein the power adapter charges the terminal through a USB port of the mobile terminal. Because the terminal can reduce the heat of the electronic equipment through the quick charging path and the dispersed arrangement mode, the problem that the whole charging system generates heat seriously when the power adapter charges the terminal is avoided.

Based on the charging circuit provided in the foregoing embodiment, an embodiment of the present application further provides a circuit control method, where the method is applied to the charging circuit provided in any of the foregoing embodiments, and it should be noted that, because the circuit detection method is a method applied in a working process of the charging circuit, a detailed process in the circuit detection method in this embodiment is the same as a detection process described in the charging circuit, and therefore, the detection process will not be described in detail in the embodiment of the circuit detection method in the present application, specifically, as shown in fig. 12, the method includes:

s101, controlling the conducting state of each transistor channel according to the switching state of the switching control circuit, and detecting whether the transistor channel in the conducting state is normal or not when one channel in the quick charging channel is independently conducted in each transistor channel.

S102, controlling the working state of the quick charging passage according to the detection result; the quick charging circuit at least comprises two parallel transistor circuits, and each transistor circuit is respectively connected with the switch control circuit.

The implementation principle and technical effects of the circuit control method provided by the above embodiment are similar to those of the embodiment in the charging circuit, and are not described again here.

In one embodiment, one implementation manner of the above S101 includes: and sequentially controlling one transistor channel in the quick charging channels to be switched on and the other transistor channels to be switched off, detecting the current passing through each transistor channel, and determining whether each transistor channel is normal or not according to the current.

In one embodiment, if the fast charging path includes a first transistor path and a second transistor path; the switch control circuit comprises a first switch control sub-circuit and a second switch control sub-circuit, and a first transistor passage is connected with the first switch control sub-circuit; the second transistor channel is connected with the second switch control sub-circuit; as shown in fig. 13, the implementation manner of S101 specifically includes:

s201, when the first switch control sub-circuit and the second switch control sub-circuit are both turned off, providing a conducting voltage for the fast charging path, and detecting a first current value passing through the fast charging path at present.

S202, when the first switch control sub-circuit is turned off and the second switch control sub-circuit is turned on, providing a conducting voltage for the first transistor channel, and acquiring a second current value passing through the first transistor channel; and the conduction control circuit provides conduction voltage for the second transistor access when the first switch control sub-circuit is conducted and the second switch control sub-circuit is switched off, and obtains a third current value passing through the second transistor access.

S203, when the difference value between the first current value and the second current value is smaller than a preset current threshold value, determining that the first transistor channel is normal; and when the difference value between the first current value and the third current value is smaller than a preset current threshold value, the conduction control circuit determines that the second transistor is normal in passage.

The implementation principle and technical effect of the circuit control method provided by the above embodiment are similar to those of the above embodiment of the charging circuit, and are not described herein again.

In one embodiment, the step S102 includes: if all the transistor paths are normal, controlling all the transistor paths in the quick charging path to be conducted; and if any one transistor channel is abnormal, controlling all the transistor channels in the quick charge channel to be cut off.

The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is specific and detailed, but not to be understood as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, and these are all within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims

1. A charging circuit, the circuit comprising: the fast charging circuit comprises a fast charging path, a conduction control circuit and a switch control circuit; the quick charging path comprises at least two parallel transistor paths; each transistor channel is respectively connected with the switch control circuit; each of said transistor paths including at least one transistor;

a first pole of a transistor in the transistor path is connected with an energy storage device of the equipment to be charged, and a second pole of the transistor in the transistor path is connected with a charging interface; the control electrodes of the transistors in the transistor channels are respectively connected with the switch control circuit and the conduction control circuit;

the conduction control circuit is used for controlling the conduction state of each transistor channel according to the switching state of the switching control circuit, and detecting whether the transistor channel in the conduction state is normal or not when one transistor channel in the quick charging channels is singly conducted;

the conduction control circuit is further configured to control all transistor paths in the at least two parallel transistor paths of the fast charge path to be conducted when each transistor path is normal; and when any one transistor path is abnormal, all the transistor paths in the at least two parallel transistor paths of the fast charging path are controlled to be cut off.

2. The charging circuit of claim 1, wherein the conduction control circuit provides a conduction voltage for the fast charging path when the switch control circuit is turned off, so that a charging current is transmitted to the energy storage device through the fast charging path when the fast charging path is in a conduction state.

3. The charging circuit according to claim 1 or 2, wherein the conduction control circuit is configured to control one of the transistor paths in the fast charging path to be in a conduction state, and the other transistor paths to be in an off state, detect a current of the transistor path in the conduction state, and determine whether the transistor path in the conduction state is normal according to the current.

4. The charging circuit of claim 3, wherein the switch control circuit comprises a plurality of parallel switch control sub-circuits, each of the switch control sub-circuits being connected to a corresponding transistor path;

and the conduction control circuit is used for controlling the conduction state of the corresponding transistor access according to the switching state of each switch control sub-circuit.

5. The charging circuit of claim 4, wherein the fast charge path comprises a first transistor path and a second transistor path; the switch control circuit comprises a first switch control sub-circuit and a second switch control sub-circuit, and the first transistor channel is connected with the first switch control sub-circuit; the second transistor channel is connected with a second switch control sub-circuit;

the conduction control circuit is used for providing conduction voltage for the quick charge path when the first switch control sub-circuit and the second switch control sub-circuit are both turned off, and detecting a first current value passing through the quick charge path at present;

the conduction control circuit is used for providing the conduction voltage for the first transistor channel when the first switch control sub-circuit is turned off and the second switch control sub-circuit is turned on, and acquiring a second current value passing through the first transistor channel; when the first switch control sub-circuit is switched on and the second switch control sub-circuit is switched off, the conduction control circuit provides the conduction voltage for the second transistor channel and obtains a third current value passing through the second transistor channel;

the conduction control circuit is used for determining that the first transistor channel is normal when the difference value between the first current value and the second current value is smaller than a preset current threshold value; the conduction control circuit is used for determining that the second transistor access is normal when the difference value between the first current value and the third current value is smaller than the preset current threshold.

6. The charging circuit according to claim 1 or 2, wherein an input terminal of the conduction control circuit is connected to the charging interface and the clock signal interface, and an output terminal of the conduction control circuit is connected to a control electrode of a transistor in the transistor path;

the input end of the switch control circuit is connected with a switch signal end, and the output end of the switch control circuit is connected with the control electrode of the transistor in the transistor passage;

the conduction control circuit is used for providing conduction voltage for the transistor channel when each switch control circuit is turned off.

7. The charging circuit of claim 6, wherein the charging circuit comprises a plurality of the conduction control circuits, different ones of the conduction control circuits being connected to different ones of the transistor paths.

8. The charging circuit according to claim 7, wherein the conduction control circuit includes a charging signal input unit, a clock signal input unit, and a signal processing unit;

the input end of the charging signal input unit is connected with the charging interface, and the output end of the charging signal input unit is connected with the input end of the signal processing unit; the input end of the clock signal input unit is connected with the clock signal interface, and the output end of the clock signal input unit is connected with the input end of the signal processing unit; the output end of the signal processing unit is connected with the transistor control electrode in the transistor passage;

the charging signal input unit is used for inputting a charging signal to the signal processing unit;

the clock signal input unit is used for inputting a clock signal to the signal processing unit;

the signal processing unit is used for providing a conducting voltage for the transistor path according to the charging signal and the clock signal.

9. The charging circuit of claim 8, wherein the charging signal input unit comprises a back-flow prevention subunit and a filtering subunit;

the input end of the backflow prevention subunit is connected with the output end of the filtering subunit, and the output end of the backflow prevention subunit is connected with the input end of the signal processing unit; the input end of the filtering subunit is connected with the charging interface;

the backflow preventing subunit is used for preventing the charging voltage from flowing backwards; the filtering subunit is used for filtering noise signals entering along with the charging voltage.

10. The charging circuit according to claim 1 or 2, wherein the charging circuit further comprises a protection circuit; the input end of the protection circuit is connected with the charging interface, and the output end of the protection circuit is connected with the control electrode of the transistor in the transistor passage;

the protection circuit is used for preventing the transistor in the transistor path from entering negative pressure.

11. The charging circuit according to claim 1 or 2, wherein the charging circuit further comprises a voltage-reducing circuit;

the input end of the voltage reduction circuit is connected with a first pole of a transistor in the transistor passage, and the output end of the voltage reduction circuit is connected with an energy storage device of the equipment to be charged;

12. A charging chip, characterized in that it comprises a charging circuit according to any one of claims 1 to 11.

13. A terminal, characterized in that the terminal comprises a charging circuit according to any one of claims 1-11.

14. The terminal of claim 13, wherein a distance between transistor paths in the fast charge path of the terminal is greater than a predetermined distance threshold.

15. A terminal as claimed in claim 13 or 14, wherein if the fast charging path comprises a first transistor path and a second transistor path, the first transistor path is disposed on a main board region of a circuit board of the terminal, and the second transistor path is disposed on a small board region of the circuit board of the terminal.

16. A circuit control method applied to the charging circuit according to any one of claims 1 to 11, the method comprising:

controlling the conduction state of each transistor channel according to the switching state of the switching control circuit, and detecting whether the transistor channel in the conduction state is normal or not when one transistor channel in the quick charging channel is independently conducted;

if all the transistor paths are normal, all the transistor paths in the at least two parallel transistor paths of the quick charging path are controlled to be conducted;

if any one transistor channel is abnormal, all transistor channels in the at least two parallel transistor channels of the fast charging channel are controlled to be cut off; the quick charging path at least comprises two parallel transistor paths, and each transistor path is respectively connected with the switch control circuit.

17. The method according to claim 16, wherein the controlling the conducting state of each transistor path according to the switching state of the switch control circuit, and detecting whether the transistor path in the conducting state is normal when one of the transistor paths in the fast charging path is separately conducted comprises:

18. The method of claim 16 or 17, wherein the fast charge path comprises a first transistor path and a second transistor path; the switch control circuit comprises a first switch control sub-circuit and a second switch control sub-circuit, and the first transistor channel is connected with the first switch control sub-circuit; the second transistor channel is connected with a second switch control sub-circuit;

sequentially controlling one transistor channel in the fast charging channels to be switched on and the other transistor channels to be switched off, detecting the current passing through each transistor channel, and determining whether each transistor channel is normal according to the current, wherein the steps of:

when the first switch control sub-circuit is turned off and the second switch control sub-circuit is turned on, providing the turn-on voltage for the first transistor channel, and acquiring a second current value passing through the first transistor channel at present; when the first switch control sub-circuit is switched on and the second switch control sub-circuit is switched off, providing the switching-on voltage for the second transistor access, and acquiring a third current value passing through the second transistor access;

when the difference value between the first current value and the second current value is smaller than a preset current threshold value, determining that the first transistor access is normal; and when the difference value between the first current value and the third current value is smaller than the preset current threshold value, determining that the second transistor is normal.