CN112395215B - DRAM-less solid state disk mapping table management method and device, computer equipment and storage medium - Google Patents
DRAM-less solid state disk mapping table management method and device, computer equipment and storage medium Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/0292—User address space allocation, e.g. contiguous or non contiguous base addressing using tables or multilevel address translation means
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- G—PHYSICS
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- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
- G06F12/0871—Allocation or management of cache space
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1009—Address translation using page tables, e.g. page table structures
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- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
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- G06F2212/1016—Performance improvement
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- G06F2212/10—Providing a specific technical effect
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- G06F2212/1044—Space efficiency improvement
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/21—Employing a record carrier using a specific recording technology
- G06F2212/214—Solid state disk
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The invention relates to a DRAM-less solid state disk mapping table management method, a device, computer equipment and a storage medium; wherein, the method comprises the following steps: converting the logical page number into a mapping table data page number; judging whether a page corresponding to the mapping table data page number is loaded into a memory or not; judging whether the mapping corresponding to the mapping table data page number is in the primary mapping table or not; loading the mapping corresponding to the mapping table data page number to form the mapping of the mapping table data page number; setting a current secondary mapping table update log page to be scanned as a latest secondary mapping table update log page; reading an update log page of the latest secondary mapping table; judging whether the mapping of the mapping table data page number is in the mapping directory of the mapping table data page number of the latest secondary mapping table update log page or not; loading a page corresponding to the mapping table data page number into a secondary mapping table cache; and inquiring the secondary mapping table cache to obtain the NAND address corresponding to the logical page number. The invention can reduce the requirement on the system RAM and the cost.
Description
Technical Field
The invention relates to the technical field of DRAM-less solid state disk mapping table management, in particular to a DRAM-less solid state disk mapping table management method, a device, computer equipment and a storage medium.
Background
The SSD user space mapping table (L2P table) is large, and typically two levels of tables are used to manage it: namely, the L2P table is sequentially addressed according to a fixed unit size (MP) to form a first-level mapping table (M2P table), the L2P table is called a second-level mapping table, and because the RAM space provided by a DRAM-less (high-speed nonvolatile) SSD system is extremely limited, the M2P resident RAM occupies more RAM space, and the RAM capacity provided by the system may not meet the requirement.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a method, a device, computer equipment and a storage medium for managing a DRAM-less solid state disk mapping table.
In order to achieve the above purpose, the present invention adopts the following technical scheme:
the DRAM-less solid state disk mapping table management method comprises the following steps:
converting the logical page number into a mapping table data page number;
judging whether a page corresponding to the mapping table data page number is loaded into a memory or not;
if not, judging whether the mapping corresponding to the mapping table data page number is in the primary mapping table or not;
if not, loading the mapping corresponding to the mapping table data page number to form mapping of the mapping table data page number;
setting a current secondary mapping table update log page to be scanned as a latest secondary mapping table update log page;
reading an update log page of the latest secondary mapping table;
judging whether the mapping of the mapping table data page number is in the mapping directory of the mapping table data page number of the latest secondary mapping table update log page or not;
if yes, loading a page corresponding to the mapping table data page number into a second-level mapping table cache;
and inquiring the secondary mapping table cache to obtain the NAND address corresponding to the logical page number.
The further technical scheme is as follows: after the step of determining whether the page corresponding to the mapping table data page number is loaded into the memory, the method further includes:
if the page corresponding to the mapping table data page number is loaded into the memory, the executing step inquires the second-level mapping table cache to obtain the NAND address corresponding to the logic page number.
The further technical scheme is as follows: after the step of determining whether the mapping corresponding to the mapping table data page number is in the primary mapping table, the method further includes:
if the mapping corresponding to the mapping table data page number is in the first-level mapping table, the executing step loads the page corresponding to the mapping table data page number into the second-level mapping table cache.
The further technical scheme is as follows: after the step of judging whether the mapping of the mapping table data page number is in the mapping catalog of the mapping table data page number of the latest secondary mapping table update log page, the method further comprises the following steps:
if the mapping of the mapping table data page number is not in the mapping directory of the mapping table data page number of the latest secondary mapping table update log page, setting the latest secondary mapping table update log page as the previous secondary mapping table update log page recorded in the reading page.
DRAM-less solid state disk mapping table management device includes: the device comprises a conversion unit, a first judging unit, a second judging unit, a loading forming unit, a first setting unit, a reading unit, a third judging unit, a loading unit and a query obtaining unit;
the conversion unit is used for converting the logical page number into a mapping table data page number;
the first judging unit is used for judging whether the page corresponding to the mapping table data page number is loaded into the memory or not;
the second judging unit is used for judging whether the mapping corresponding to the mapping table data page number is in the first-level mapping table or not;
the loading forming unit is used for loading the mapping corresponding to the mapping table data page number to form the mapping of the mapping table data page number;
the first setting unit is used for setting the current second-level mapping table update log page to be scanned as the latest second-level mapping table update log page;
the reading unit is used for reading the updated log page of the latest secondary mapping table;
the third judging unit is used for judging whether the mapping of the mapping table data page number is in the mapping directory of the mapping table data page number of the latest secondary mapping table update log page;
the loading unit is used for loading the page corresponding to the mapping table data page number into the secondary mapping table cache;
the query acquisition unit is used for querying the second-level mapping table cache to acquire the NAND address corresponding to the logical page number.
The further technical scheme is as follows: further comprises: and the second setting unit is used for setting the latest secondary mapping table update log page as a previous secondary mapping table update log page recorded in the read page.
The computer equipment comprises a memory and a processor, wherein the memory stores a computer program, and the processor realizes the DRAM-less solid state disk mapping table management method when executing the computer program.
A storage medium storing a computer program comprising program instructions which, when executed by a processor, implement a DRAM-less solid state disk map management method as described above.
Compared with the prior art, the invention has the beneficial effects that: the primary mapping table does not reside in the memory any more, so that the situation that the disk capacity increases along with the increase of the disk capacity is avoided, the primary mapping table occupies too much memory, and the primary mapping table snapshot stored in the NAND is used for assisting in scanning MP blocks to acquire the storage positions of the MP in the NAND, so that the requirement on the system RAM can be reduced, the cost is reduced, and the requirement can be better met.
The invention is further described below with reference to the drawings and specific embodiments.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of an application of address mapping relationships;
FIG. 2 is an application diagram of a mapping table layout in NAND;
FIG. 3 is a schematic flow chart of a method for managing a DRAM-less solid state disk mapping table according to an embodiment of the present invention;
FIG. 4 is a schematic block diagram of a DRAM-less solid state disk mapping table management device according to an embodiment of the present invention;
fig. 5 is a schematic block diagram of a computer device according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be understood that the terms "comprises" and "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be further understood that the term "and/or" as used in the present specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.
Referring to fig. 1 to 5, wherein referring to the application schematic diagram of the address mapping relationship shown in fig. 1, the relationship between the user address and the primary mapping table (M2P table) and the secondary mapping table (L2P table) is as follows: lpn=lbn/8, mpn=lpn/1024, and the L2P table records the mapping of LPN to NAND address; the M2P table records the mapping of MPNs to NAND addresses.
In a DRAM-less SSD, the L2P table is too large to be resident in RAM, loaded on demand to RAM, and the M2P table may be resident in RAM, but may occupy a larger RAM space, such as 1MB for a 1TB disk in the example, and the M2P table needs to occupy 1MB of space.
Wherein, the M2P does not reside in the RAM, and the storage position of the MP in the NAND is acquired by the M2P snapshot stored in the NAND assisted by the scanning of the Flush End Page of the MP Block; as shown in fig. 2, each time the flush procedure of the L2P table is a procedure of writing updated L2P Cache (secondary mapping table Cache) pages in the RAM into the NAND, which is an atomic operation, so a Log Page can be added at the end of the flush procedure: the Flush End Page records all MPNs written in the current Flush process, and is used for quickly acquiring NAND addresses corresponding to the MPNs from the Flush End Page when MPN mapping cannot be acquired from the M2P snapshot, and in addition, the Flush End Page also records the positions (2 in the figure) of a plurality of previous Flush End pages, so as to accelerate the scanning of the Flush End Page, and describe the data structure of the Flush End Page.
Wherein, because the M2P table in NAND is only a snapshot, the mapping is not necessarily up to date, so that a bitmap of M2P 00D needs to be maintained in RAM to indicate which MPNs need to acquire the mapping by scanning Flush End Page, and each Flush L2P procedure needs to set a corresponding bit of the M2P 00D bitmap for each MPN; after the M2P table is updated, the entire M2P 00D needs to be emptied.
The terms in fig. 1 to 2 are explained as follows:
LBN: logic Block Number, the basic unit is read and written by a user, and is commonly 512Bytes;
LPN: logic Page Number logical page number, user data mapping unit, usually 4KB;
MPN: map Page Number, map data management unit, commonly 256B/512B/4KB/.
PPN: physical Page Number physical page number, NAND page address;
USR SPACE: a user space;
USR PPN: the user corresponds to the NAND page number;
SEG1, 2: segments 1, 2;
flush End Page: updating a log page by the secondary mapping table;
M2P Table Snapshot after L P flush-1: a snapshot of the corresponding primary mapping table after the first flush of the secondary mapping table;
pre Flush End Page: updating a log page by the first-level mapping table;
MPN of first/second/third page: MPNs corresponding to the first page, the second page and the third page;
referring to FIG. 3, the invention discloses a DRAM-less solid state disk mapping table management method, which comprises the following steps:
s1, converting a logical page number into a mapping table data page number;
s2, judging whether a page corresponding to the mapping table data page number is loaded into a memory or not; if so, executing step S9;
s3, if not, judging whether the mapping corresponding to the mapping table data page number is in the primary mapping table; if yes, executing step S8;
s4, if not, loading the mapping corresponding to the mapping table data page number to form mapping of the mapping table data page number;
s5, setting the update log page of the current secondary mapping table to be scanned as the update log page of the latest secondary mapping table;
s6, reading an update log page of the latest secondary mapping table;
s7, judging whether the mapping of the mapping table data page numbers is in a mapping directory of the mapping table data page numbers of the latest secondary mapping table update log page;
s8, if yes, loading a page corresponding to the mapping table data page number into a second-level mapping table cache;
s9, inquiring the second-level mapping table cache to obtain the NAND address corresponding to the logical page number.
S10, if the mapping of the mapping table data page number is not in the mapping directory of the mapping table data page number of the latest secondary mapping table update log page, setting the latest secondary mapping table update log page as the previous secondary mapping table update log page recorded in the reading page.
Because the RAM space is limited, the M2P table may not be fully loaded into the RAM, so that a scheme of M2P table segment update is required, for each segment of M2P table, the M2P table is scanned, written into the MPN directory of the NAND F1ush End Page after being updated, the corresponding map in the M2P is updated, then the NAND is written, and after the M2P table is updated, the M2P bitmap after the M2P table is updated is emptied.
The M2P snapshot is updated after Flush 1, so that the Flush End pages (2-3 and 3-4) corresponding to Flush2 and Flush3 need to be scanned for this update of M2P.
According to the invention, the primary mapping table is not resident in the memory any more, the situation that the disk capacity increases with the increase of the disk capacity, the primary mapping table occupies too much memory is avoided, and the primary mapping table snapshot stored in the NAND is used for assisting in scanning MP blocks to acquire the storage positions of the MP in the NAND, so that the requirement on the system RAM can be reduced, the cost is reduced, and the requirement can be better met.
Referring to fig. 4, the invention also discloses a device for managing the mapping table of the DRAM-less solid state disk, which comprises: a conversion unit 10, a first judgment unit 20, a second judgment unit 30, a load formation unit 40, a first setting unit 50, a reading unit 60, a third judgment unit 70, a load unit 80, and a query acquisition unit 90;
the conversion unit 10 is configured to convert a logical page number into a mapping table data page number;
the first judging unit 20 is configured to judge whether a page corresponding to a mapping table data page number is loaded into the memory;
the second judging unit 30 is configured to judge whether the mapping corresponding to the mapping table data page number is in the first-level mapping table;
the loading forming unit 40 is configured to load a mapping corresponding to the mapping table data page number, and form a mapping of the mapping table data page number;
the first setting unit 50 is configured to set a current secondary mapping table update log page to be scanned as a latest secondary mapping table update log page;
the reading unit 60 is configured to read the latest secondary mapping table update log page;
the third judging unit 70 is configured to judge whether the mapping of the mapping table data page number is in the mapping directory of the mapping table data page number of the latest secondary mapping table update log page;
the loading unit 80 is configured to load a page corresponding to a mapping table data page number into a second-level mapping table cache;
the query obtaining unit 90 is configured to query the second-level mapping table to obtain the NAND address corresponding to the logical page number.
Wherein the apparatus further comprises: a second setting unit 100 for setting the latest secondary mapping table update log page as the past secondary mapping table update log page recorded in the read page.
It should be noted that, as those skilled in the art can clearly understand, the specific implementation process of the DRAM-less solid state disk mapping table management device and each unit may refer to the corresponding description in the foregoing method embodiment, and for convenience and brevity of description, the description is omitted here.
The DRAM-less solid state disk mapping table management apparatus described above may be implemented in the form of a computer program that may be run on a computer device as shown in fig. 5.
Referring to fig. 5, fig. 5 is a schematic block diagram of a computer device according to an embodiment of the present application; the computer device 500 may be a terminal or a server, where the terminal may be an electronic device with a communication function, such as a smart phone, a tablet computer, a notebook computer, a desktop computer, a personal digital assistant, and a wearable device. The server may be an independent server or a server cluster formed by a plurality of servers.
With reference to FIG. 5, the computer device 500 includes a processor 502, memory, and a network interface 505 connected by a system bus 501, where the memory may include a non-volatile storage medium 503 and an internal memory 504.
The non-volatile storage medium 503 may store an operating system 5031 and a computer program 5032. The computer program 5032 includes program instructions that, when executed, cause the processor 502 to perform a DRAM-less solid state disk map management method.
The processor 502 is used to provide computing and control capabilities to support the operation of the overall computer device 500.
The internal memory 504 provides an environment for the execution of a computer program 5032 in the non-volatile storage medium 503, which computer program 5032, when executed by the processor 502, causes the processor 502 to perform a DRAM-less solid state disk map management method.
The network interface 505 is used for network communication with other devices. Those skilled in the art will appreciate that the architecture shown in fig. 5 is merely a block diagram of a portion of the architecture in connection with the present application and is not intended to limit the computer device 500 to which the present application is applied, and that a particular computer device 500 may include more or fewer components than shown, or may combine certain components, or have a different arrangement of components.
It should be appreciated that in embodiments of the present application, the processor 502 may be a central processing unit (Central Processing Unit, CPU), the processor 502 may also be other general purpose processors, digital signal processors (Digital Signal Processor, DSPs), application specific integrated circuits (Application Specific Integrated Circuit, ASICs), off-the-shelf programmable gate arrays (Field-Programmable Gate Array, FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. Wherein the general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
Those skilled in the art will appreciate that all or part of the flow in a method embodying the above described embodiments may be accomplished by computer programs instructing the relevant hardware. The computer program comprises program instructions, and the computer program can be stored in a storage medium, which is a computer readable storage medium. The program instructions are executed by at least one processor in the computer system to implement the flow steps of the embodiments of the method described above.
Accordingly, the present invention also provides a storage medium. The storage medium may be a computer readable storage medium. The storage medium stores a computer program, wherein the computer program comprises program instructions that when executed by a processor implement the DRAM-less solid state disk mapping table management method described above.
The storage medium may be a U-disk, a removable hard disk, a Read-Only Memory (ROM), a magnetic disk, or an optical disk, or other various computer-readable storage media that can store program codes.
Those of ordinary skill in the art will appreciate that the elements and algorithm steps described in connection with the embodiments disclosed herein may be embodied in electronic hardware, in computer software, or in a combination of the two, and that the elements and steps of the examples have been generally described in terms of function in the foregoing description to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
In the several embodiments provided by the present invention, it should be understood that the disclosed apparatus and method may be implemented in other manners. For example, the device embodiments described above are merely illustrative. For example, the division of each unit is only one logic function division, and there may be another division manner in actual implementation. For example, multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed.
The steps in the method of the embodiment of the invention can be sequentially adjusted, combined and deleted according to actual needs. The units in the device of the embodiment of the invention can be combined, divided and deleted according to actual needs. In addition, each functional unit in the embodiments of the present invention may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.
The integrated unit may be stored in a storage medium if implemented in the form of a software functional unit and sold or used as a stand-alone product. Based on such understanding, the technical solution of the present invention is essentially or a part contributing to the prior art, or all or part of the technical solution may be embodied in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a terminal, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention.
The foregoing examples are provided to further illustrate the technical contents of the present invention for the convenience of the reader, but are not intended to limit the embodiments of the present invention thereto, and any technical extension or re-creation according to the present invention is protected by the present invention. The protection scope of the invention is subject to the claims.
Claims (8)
- A DRAM-less solid state disk mapping table management method is characterized by comprising the following steps:converting the logical page number into a mapping table data page number;judging whether a page corresponding to the mapping table data page number is loaded into a memory or not;if not, judging whether the mapping corresponding to the mapping table data page number is in the primary mapping table or not;if not, loading the mapping corresponding to the mapping table data page number to form mapping of the mapping table data page number;setting a current secondary mapping table update log page to be scanned as a latest secondary mapping table update log page;reading an update log page of the latest secondary mapping table;judging whether the mapping of the mapping table data page number is in the mapping directory of the mapping table data page number of the latest secondary mapping table update log page or not;if yes, loading a page corresponding to the mapping table data page number into a second-level mapping table cache;and inquiring the secondary mapping table cache to obtain the NAND address corresponding to the logical page number.
- 2. The method for managing the mapping table of the DRAM-less solid state disk according to claim 1, wherein after the step of determining whether the page corresponding to the mapping table data page number is loaded into the memory, further comprising:if the page corresponding to the mapping table data page number is loaded into the memory, the executing step inquires the second-level mapping table cache to obtain the NAND address corresponding to the logic page number.
- 3. The method for managing the mapping table of the DRAM-less solid state disk according to claim 1, wherein after the step of determining whether the mapping corresponding to the data page number of the mapping table is in the primary mapping table, further comprising:if the mapping corresponding to the mapping table data page number is in the first-level mapping table, the executing step loads the page corresponding to the mapping table data page number into the second-level mapping table cache.
- 4. The method for managing a mapping table of a DRAM-less solid state disk according to claim 3, wherein the step of determining whether the mapping of the mapping table data page number is in the mapping directory of the mapping table data page number of the latest secondary mapping table update log page further comprises:if the mapping of the mapping table data page number is not in the mapping directory of the mapping table data page number of the latest secondary mapping table update log page, setting the latest secondary mapping table update log page as the previous secondary mapping table update log page recorded in the reading page.
- A DRAM-less solid state disk mapping table management device is characterized by comprising: the device comprises a conversion unit, a first judging unit, a second judging unit, a loading forming unit, a first setting unit, a reading unit, a third judging unit, a loading unit and a query obtaining unit;the conversion unit is used for converting the logical page number into a mapping table data page number;the first judging unit is used for judging whether the page corresponding to the mapping table data page number is loaded into the memory or not;the second judging unit is used for judging whether the mapping corresponding to the mapping table data page number is in the first-level mapping table or not;the loading forming unit is used for loading the mapping corresponding to the mapping table data page number to form the mapping of the mapping table data page number;the first setting unit is used for setting the current second-level mapping table update log page to be scanned as the latest second-level mapping table update log page;the reading unit is used for reading the updated log page of the latest secondary mapping table;the third judging unit is used for judging whether the mapping of the mapping table data page number is in the mapping directory of the mapping table data page number of the latest secondary mapping table update log page;the loading unit is used for loading the page corresponding to the mapping table data page number into the secondary mapping table cache;the query acquisition unit is used for querying the second-level mapping table cache to acquire the NAND address corresponding to the logical page number.
- 6. The DRAM-less solid state disk mapping table management apparatus of claim 5, further comprising: and the second setting unit is used for setting the latest secondary mapping table update log page as a previous secondary mapping table update log page recorded in the read page.
- 7. A computer device, characterized in that the computer device comprises a memory and a processor, wherein the memory stores a computer program, and the processor implements the DRAM-less solid state disk mapping table management method according to any of claims 1-4 when executing the computer program.
- 8. A storage medium storing a computer program comprising program instructions which, when executed by a processor, implement the DRAM-less solid state disk mapping table management method of any of claims 1-4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011409618.5A CN112395215B (en) | 2020-12-03 | 2020-12-03 | DRAM-less solid state disk mapping table management method and device, computer equipment and storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011409618.5A CN112395215B (en) | 2020-12-03 | 2020-12-03 | DRAM-less solid state disk mapping table management method and device, computer equipment and storage medium |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112395215A CN112395215A (en) | 2021-02-23 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20140027596A (en) * | 2012-07-24 | 2014-03-07 | 삼성전자주식회사 | Memory system and security method of memory system |
| CN106354658A (en) * | 2016-08-29 | 2017-01-25 | 成都三零嘉微电子有限公司 | Method for reducing memory resource occupation of mapping tables in hybrid mapping algorithm |
| CN106502928A (en) * | 2016-09-29 | 2017-03-15 | 华为技术有限公司 | A kind of storage system power-off protection method, storage control and electronic equipment |
| CN112559386A (en) * | 2020-12-22 | 2021-03-26 | 深圳忆联信息系统有限公司 | Method and device for improving SSD performance, computer equipment and storage medium |
-
2020
- 2020-12-03 CN CN202011409618.5A patent/CN112395215B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20140027596A (en) * | 2012-07-24 | 2014-03-07 | 삼성전자주식회사 | Memory system and security method of memory system |
| CN106354658A (en) * | 2016-08-29 | 2017-01-25 | 成都三零嘉微电子有限公司 | Method for reducing memory resource occupation of mapping tables in hybrid mapping algorithm |
| CN106502928A (en) * | 2016-09-29 | 2017-03-15 | 华为技术有限公司 | A kind of storage system power-off protection method, storage control and electronic equipment |
| CN112559386A (en) * | 2020-12-22 | 2021-03-26 | 深圳忆联信息系统有限公司 | Method and device for improving SSD performance, computer equipment and storage medium |
Non-Patent Citations (3)
| Title |
|---|
| A Hash-Based Space-Efficient Page-Level FTL for Lage-Capacity SSDs;Fan Ni .etc;《2017 International Conference on Networking，Architecture，and Storage》;1-6 * |
| 一种优化的闪存地址映射方法;张琦等;《软件学报》;1-12 * |
| 基于NAND闪存的固态盘关键技术研究;杜晨杰;《中国优秀硕士学位论文全文数据库》;I137-6 * |
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