CN112395040A

CN112395040A - Memory data transmission method, system and server

Info

Publication number: CN112395040A
Application number: CN201910765290.1A
Authority: CN
Inventors: 张扬; 罗犇
Original assignee: Alibaba Group Holding Ltd
Current assignee: Alibaba Group Holding Ltd
Priority date: 2019-08-19
Filing date: 2019-08-19
Publication date: 2021-02-23

Abstract

The invention discloses a memory data transmission method and system, a source end server and a destination end server. Wherein, the method comprises the following steps: the source end configures a source address to the source end FPGA through a first driver of the source end, wherein the source address is a virtual machine memory virtual address of memory data to be transmitted in a source end virtual machine; the source end sends a source address to the destination end, the source address is used for the destination end to determine a destination address of memory data to be transmitted in a destination end virtual machine through a destination end first driver, and the destination address is configured to a destination end FPGA, wherein the destination address is a virtual machine memory virtual address of the memory data to be transmitted in the destination end virtual machine; the source end directly copies the memory data from the source address to the destination address through the source end FPGA and the destination end FPGA. The invention solves the technical problems of low efficiency and high resource occupation of a pure software mode for copying the memory data in the related technology.

Description

Memory data transmission method, system and server

Technical Field

The present invention relates to the field of data transmission, and in particular, to a method and a system for transmitting memory data, a source server, and a destination server.

Background

At present, the live migration iterative copy uses a host network card to send data in a pure software mode. In this process, the memory data needs to be copied from the user space to the kernel space and sent out through the kernel network protocol stack. After receiving the data, the network card of the destination terminal needs to be unpacked through a kernel protocol stack, and then the data is copied to a user space. The memory copy and the protocol stack analysis are carried out for many times, the calculation power of a CPU is consumed, and meanwhile, the data transmission time is also increased. The increase of the data transmission time of each iteration copy also causes more dirty pages to be generated, and the time consumption of the hot migration and the condition of the service quality reduction of the virtual machine are aggravated. Therefore, the time for copying the memory data is prolonged, the efficiency is reduced, and the problem of high resource occupation is solved.

In view of the above problems, no effective solution has been proposed.

Disclosure of Invention

The embodiment of the invention provides a memory data transmission method and system, a source end server and a destination end server, which are used for at least solving the technical problems of low efficiency and high occupied resource in a mode of copying memory data in a pure software mode in the related technology.

According to an aspect of the embodiments of the present invention, there is provided a memory data transmission method, including: the source end configures a source address to a source end FPGA through a source end first driver, wherein the source address is a virtual machine memory virtual address of memory data to be transmitted in a source end virtual machine; the source end sends the source address to a destination end, and the source end is used for determining a destination address of the memory data to be transmitted in a destination end virtual machine through a destination end first driver and configuring the destination address to a destination end FPGA, wherein the destination address is a virtual machine memory virtual address of the memory data to be transmitted in the destination end virtual machine; and the source end directly copies the memory data from the source address to the destination address through the source end FPGA and the destination end FPGA.

According to another aspect of the embodiments of the present invention, there is also provided a memory data transmission method, including: a destination terminal receives a source address sent by a source terminal, wherein the source address is a virtual machine memory virtual address of memory data to be transmitted in a source terminal virtual machine, and the source address is configured in a source terminal FPGA through a source terminal first drive; the destination terminal converts the source address into a destination address through a destination terminal first driver and configures the destination address to a destination terminal FPGA, wherein the destination address is a virtual machine memory virtual address of the memory data to be transmitted in a destination terminal virtual machine; and the destination terminal directly copies the memory data from the source address to the destination address through the source terminal FPGA and the destination terminal FPGA.

According to another aspect of the embodiments of the present invention, there is also provided a memory data transmission method, including: the source end configures a source address to a source end FPGA through a source end first driver, wherein the source address is a virtual machine memory virtual address of memory data to be transmitted in a source end virtual machine; the source end sends the source address to a destination end; the destination terminal converts the source address into a destination address through a destination terminal first driver, and configures the destination address to a destination terminal FPGA, wherein the destination address is a virtual machine memory virtual address of the memory data to be transmitted in a destination terminal virtual machine; and the source end initiates data copying to the destination end, and directly copies the memory data from the source address to the destination address through the source end FPGA and the destination end FPGA.

According to another aspect of the embodiments of the present invention, there is also provided a memory data transmission method, including: a source end FPGA receives a source address configured by a first driver of a source end, wherein the source address is a virtual machine memory virtual address of memory data to be transmitted in a source end virtual machine; under the condition that the destination address of the memory data to be transmitted in the destination virtual machine is configured to the destination FPGA, the source FPGA communicates with the destination FPGA to directly copy the memory data from the source address to the destination address, wherein the destination address is the virtual machine memory virtual address of the memory data to be transmitted in the destination virtual machine.

According to another aspect of the embodiments of the present invention, there is also provided a memory data transmission method, including: the method comprises the steps that a destination end FPGA receives a destination address configured by a destination end first driver, wherein the destination address is a virtual machine memory virtual address of memory data to be transmitted in a destination end virtual machine, the destination address is obtained by converting a source address, the source address is a virtual machine memory virtual address of the memory data to be transmitted in a source end virtual machine, and the source address is configured in a source end FPGA through a source end first driver; and the destination FPGA communicates with the source FPGA and directly copies the memory data from the source address to the destination address.

According to another aspect of the embodiments of the present invention, there is also provided a source server, including: the configuration module is used for configuring a source address to the source end FPGA through a source end first driver, wherein the source address is a virtual machine memory virtual address of memory data to be transmitted in a source end virtual machine; the sending module is used for sending the source address to a destination, and is used for the destination to determine a destination address of the memory data to be transmitted in a destination virtual machine through a destination first driver and configure the destination address to a destination FPGA, wherein the destination address is a virtual machine memory virtual address of the memory data to be transmitted in the destination virtual machine; and the first copying module is used for directly copying the memory data from the source address to the destination address through the source end FPGA and the destination end FPGA.

According to another aspect of the embodiments of the present invention, there is also provided a destination server, including: the first receiving module is used for receiving a source address sent by a source end, wherein the source address is a virtual machine memory virtual address of memory data to be transmitted in a source end virtual machine, and the source address is configured in a source end FPGA through a source end first driver; the conversion module is used for converting the source address into a destination address through a destination first driver and configuring the destination address to a destination FPGA (field programmable gate array), wherein the destination address is a virtual machine memory virtual address of the memory data to be transmitted in a destination virtual machine; and the second copying module is used for directly copying the memory data from the source address to the destination address through the source end FPGA and the destination end FPGA.

According to another aspect of the embodiments of the present invention, there is also provided a memory data transmission system, including: the source end is used for configuring a source address to the source end FPGA through a first driver of the source end and sending the source address to the destination end, wherein the source address is a virtual machine memory virtual address of memory data to be transmitted in a source end virtual machine; the destination is used for converting the source address into a destination address through a first driver of the destination and configuring the destination address to the destination FPGA, wherein the destination address is a virtual machine memory virtual address of the memory data to be transmitted in a virtual machine of the destination; the source end is further configured to initiate data copying to the destination end, and directly copy the memory data from the source address to the destination address through the source end FPGA and the destination end FPGA.

According to another aspect of the embodiments of the present invention, there is also provided a memory data transmission device, including: the second receiving module is used for the source end FPGA to receive a source address configured by a first driver of the source end, wherein the source address is a virtual machine memory virtual address of memory data to be transmitted in a source end virtual machine; and the third copying module is configured to, under the condition that a destination address of the memory data to be transmitted in the destination virtual machine is configured to the destination FPGA, communicate with the destination FPGA, and directly copy the memory data from the source address to the destination address, where the destination address is a virtual machine memory virtual address of the memory data to be transmitted in the destination virtual machine.

According to another aspect of the embodiments of the present invention, there is also provided a memory data transmission device, including: a third receiving module, configured to receive, by a destination FPGA, a destination address configured by a destination first driver, where the destination address is a virtual machine memory virtual address of memory data to be transmitted in a destination virtual machine, the destination address is obtained by converting a source address, the source address is a virtual machine memory virtual address of the memory data to be transmitted in a source virtual machine, and the source address is configured in a source FPGA through the source first driver; and the fourth copying module is used for the destination FPGA to communicate with the source FPGA and directly copying the memory data from the source address to the destination address.

According to another aspect of the embodiments of the present invention, a storage medium is further provided, where the storage medium includes a stored program, and when the program runs, a device where the storage medium is located is controlled to execute any one of the above memory data transmission methods.

In the embodiment of the invention, a source end is adopted to configure a source address to a source end FPGA through a source end first drive, wherein the source address is a virtual machine memory virtual address of memory data to be transmitted in a source end virtual machine; the source end sends a source address to the destination end, the source address is used for the destination end to determine a destination address of memory data to be transmitted in a destination end virtual machine through a destination end first driver, and the destination address is configured to a destination end FPGA, wherein the destination address is a virtual machine memory virtual address of the memory data to be transmitted in the destination end virtual machine; the source end directly copies the memory data from the source address to the destination address through the source end FPGA and the destination end FPGA, and the purpose of directly copying the memory data from the source end to the destination end through the field programmable gate arrays at the source end and the destination end is achieved through the hardware logic, so that the technical effect of directly transmitting the memory data from the source end to the destination end by using the hardware logic of the field programmable gate arrays is achieved, multiple copying at the source end is not needed, and multiple copying processes at the destination end are not needed, and further, the technical problems of low efficiency and high resource occupation of a pure software mode copying memory data in the related technology are effectively solved.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without limiting the invention. In the drawings:

fig. 1 shows a hardware structure block diagram of a computer terminal (or mobile device) for implementing a memory data transmission method;

fig. 2 is a flowchart of a memory data transmission method according to embodiment 1 of the present invention;

fig. 3 is a flowchart of another memory data transmission method according to embodiment 2 of the present invention;

fig. 4 is a flowchart of another memory data transmission method according to embodiment 3 of the present invention;

fig. 5 is a flowchart of another memory data transmission method according to embodiment 4 of the present invention;

fig. 6 is a flowchart of another memory data transmission method according to embodiment 5 of the present invention;

fig. 7 is a schematic diagram of a conventional method for transferring a hot migration memory according to embodiment 6 of the present invention;

fig. 8 is a schematic diagram of a point-to-point live migration memory transfer method based on an FPGA according to embodiment 6 of the present invention;

fig. 9 is a schematic diagram of a method for applying a point-to-point conventional live migration memory transfer based on FPGA to a system architecture according to embodiment 6 of the present invention;

fig. 10 is a schematic diagram of a source server according to embodiment 7 of the present invention;

fig. 11 is a schematic diagram of a destination server according to embodiment 8 of the present invention;

fig. 12 is a schematic diagram of a memory data transmission system according to embodiment 9 of the present invention;

fig. 13 is a schematic diagram of a memory data transmission apparatus according to embodiment 10 of the present invention;

fig. 14 is a schematic diagram of a memory data transmission apparatus according to embodiment 11 of the present invention;

fig. 15 is a block diagram of a computer terminal according to embodiment 12 of the present invention.

Detailed Description

In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

First, some terms or terms appearing in the description of the embodiments of the present application are applicable to the following explanations:

RDMA: remote Direct Memory Access, traditional live-migration Memory iterative copy: the direct transmission of memory data via ethernet packets, called remote direct data access, is generated to solve the delay of server-side data processing in network transmission. RDMA transfers data directly to a computer's storage area over a network, quickly transferring data from one system to a remote system memory, and without operating system involvement in the transfer process, thus not requiring excessive CPU utilization. It eliminates the overhead of memory copy and context switch, thus freeing up memory bandwidth and CPU cycles for improved application system performance.

And (3) hot migration memory iterative copying: in order to reduce the service interruption time of the virtual machine, the virtual machine is still running during the process of copying the memory, so a new dirty page is generated. And the newly generated dirty pages need to initiate a new round of copying and transmitting to the destination end, so that the dirty pages are continuously copied, which is called iterative copying, until the number of the dirty pages can be transmitted to the destination end within an acceptable time period, at this time, the operation of the virtual machine is stopped, and the last copying is executed.

FPGA: the Field-Programmable Gate Array is a product developed on the basis of Programmable devices such as PAL, GAL and CPLD. The digital integrated circuit can change and configure the internal connection structure and the logic unit through a software means to complete the set design function.

FIFO: first Input First Output, First in First out memory, is a First in First out double-port buffer, the First data entering into it is the First to be shifted out, wherein, one port is the Input port of the memory, another port is the Output port of the memory, it has two structures mainly: a trigger guide structure and a zero guide transmission structure. The FIFO of the trigger oriented structure is formed by a register array, and the FIFO of the zero oriented transmission structure is formed by a double-buckle RAM with read and write address pointers.

Example 1

There is also provided, in accordance with an embodiment of the present invention, a method embodiment of a memory data transfer method, it should be noted that the steps illustrated in the flowchart of the accompanying drawings may be performed in a computer system such as a set of computer-executable instructions, and that, although a logical order is illustrated in the flowchart, in some cases, the steps illustrated or described may be performed in an order different than here.

The method provided by the first embodiment of the present application may be executed in a mobile terminal, a computer terminal, or a similar computing device. Fig. 1 shows a hardware structure block diagram of a computer terminal (or mobile device) for implementing the memory data transmission method. As shown in fig. 1, the computer terminal 10 (or mobile device 10) may include one or more (shown as 102a, 102b, … …, 102 n) processors 102 (the processors 102 may include, but are not limited to, a processing device such as a microprocessor MCU or a programmable logic device FPGA), and memory 104 for storing data. Besides, the method can also comprise the following steps: a transmission module, a display, an input/output interface (I/O interface), a Universal Serial Bus (USB) port (which may be included as one of the ports of the I/O interface), a network interface, a power source, and/or a camera. It will be understood by those skilled in the art that the structure shown in fig. 1 is only an illustration and is not intended to limit the structure of the electronic device. For example, the computer terminal 10 may also include more or fewer components than shown in FIG. 1, or have a different configuration than shown in FIG. 1.

It should be noted that the one or more processors 102 and/or other data processing circuitry described above may be referred to generally herein as "data processing circuitry". The data processing circuitry may be embodied in whole or in part in software, hardware, firmware, or any combination thereof. Further, the data processing circuit may be a single stand-alone processing module, or incorporated in whole or in part into any of the other elements in the computer terminal 10 (or mobile device). As referred to in the embodiments of the application, the data processing circuit acts as a processor control (e.g. selection of a variable resistance termination path connected to the interface).

The memory 104 may be used to store software programs and modules of application software, such as program instructions/data storage devices corresponding to the memory data transmission method in the embodiment of the present invention, and the processor 102 executes various functional applications and data processing by running the software programs and modules stored in the memory 104, that is, implementing the memory data transmission method of the application program. The memory 104 may include high speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include memory located remotely from the processor 102, which may be connected to the computer terminal 10 via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

The transmission module is used for receiving or sending data through a network. Specific examples of the network described above may include a wireless network provided by a communication provider of the computer terminal 10. In one example, the transmission module includes a Network adapter (NIC) that can be connected to other Network devices through a base station to communicate with the internet. In one example, the transmission module may be a Radio Frequency (RF) module, which is used for communicating with the internet in a wireless manner.

The display may be, for example, a touch screen type Liquid Crystal Display (LCD) that may enable a user to interact with a user interface of the computer terminal 10 (or mobile device).

Fig. 1 shows a block diagram of a hardware structure, which may be taken as an exemplary block diagram of not only the computer terminal 10 (or the mobile device) but also the server, and in an alternative embodiment, fig. 2 shows a block diagram of an embodiment, such as a sending end, a receiving end, and the like, using the computer terminal 10 (or the mobile device) shown in fig. 1. As shown in fig. 2, the computer terminal 10 (or mobile device) may be connected or electronically connected via a data network to one or more servers, such as a security server, resource server, game server, or the like. In an alternative embodiment, the computer terminal 10 (or mobile device) may be any mobile computing device or the like. The data network connection may be a local area network connection, a wide area network connection, an internet connection, or other type of data network connection. The computer terminal 10 (or mobile device) may execute to connect to a network service executed by a server (e.g., a secure server) or a group of servers. A web server is a network-based user service such as social networking, cloud resources, email, online payment, or other online applications.

In the process of virtual machine live migration, the memory of the virtual machine needs to be copied from the source server to the destination server. The total time consumption and the service interruption time (the last time of copying) of virtual machine migration are directly influenced by the memory copying and the transmission speed, the two times of copying can influence the user experience, the migration instantaneity cannot be guaranteed due to the overlong migration time, and the method is also an important factor influencing the wide use of the hot migration technology in cloud computing resource scheduling. Therefore, optimizing copy transfer between the source and destination is key to improving the performance and availability of the live migration technique.

RDMA techniques are created to account for server-side data processing delays in network transmissions. RDMA transfers data directly to a computer's storage area over a network, quickly transferring data from one system to a remote system memory, and without operating system involvement in the transfer process, thus not requiring excessive CPU utilization. It eliminates the overhead of memory copy and context switch, thus freeing up memory bandwidth and CPU cycles for improved application system performance.

The memory transmission speed can be optimized by using the RDMA technology, but the method is only used for accelerating the data transmission of the universal Ethernet network and cannot be used in the environment which is not suitable for the Ethernet. Moreover, RDMA technology relies on RDMA-capable network cards, which otherwise cannot be used. Under some server architectures which cannot adopt the traditional RDMA technology, the network connection in the traditional sense is not between the computing node and the management and control node, and the virtual machine is on the computing node. The computing node is connected with the managing node through a private channel, and the private channel has no RDMA capability and needs other hardware or software (at the cost of consuming the computing power of a CPU) to realize the memory compression and decompression in the iterative copy process.

Under the above operating environment, the present application provides a memory data transmission method as shown in fig. 2. Fig. 2 is a flowchart of a memory data transmission method according to embodiment 1 of the present invention, and as shown in fig. 2, the method includes the following steps.

Step S202, a source end configures a source address to a source end FPGA through a source end first drive, wherein the source address is a virtual machine memory virtual address of memory data to be transmitted in a source end virtual machine;

as an optional embodiment, the source may be a source server, a source memory, a source device, or a source module for storing memory data.

As an alternative embodiment, the structure of the virtual space of the virtual machine of the source end depends on the operating system of the source end, and different operating systems may have different virtual spaces, for example, the virtual space of the source end may include a source end user space and a source end kernel space, the source end user space may be accessible by a user, and the memory data stored in the source end user space may be accessible by the user, so as to facilitate a service user to perform a corresponding service. The source kernel space cannot be accessed by a user, but the source kernel space can perform data interaction with the source user space, which is equivalent to that the source kernel space and the source kernel space can perform data interaction inside a source.

As an optional embodiment, the source address is an address of memory data to be transmitted, which is stored in a virtual space in the source virtual machine, and the memory data can be acquired through the address to perform operations such as transmission and call.

As an alternative embodiment, the source virtual machine may be disposed in a source, for example, a source user space of a source server, and used by a user. When a source end server fails, a source end user space of the source end server cannot be accessed by a user, and memory data of a virtual machine in the source end user space of the source end server needs to be migrated to a memory virtual space of a virtual machine in a destination end user space of a destination end server which can be accessed by the user, so that the interruption time of the source end server is reduced, and the user experience is improved.

As an optional embodiment, the source-side FPGA is also a source-side field programmable gate array, and the source-side FPGA can change and configure an internal connection structure and a logic unit by a software means to complete a digital integrated circuit with a given design function. The source end FPGA directly utilizes FPGA hardware resources to realize data hardware compression and transmission, so that the data size of a source address of the source end memory data is reduced, the occupied bandwidth for transmitting the source address is reduced, and the bandwidth utilization rate is improved.

As an optional embodiment, in the processing process of the source-end FPGA, a CPU of a source-end server is required to participate, the source-end FPGA may be an external device, and when a system performs migration configuration, a related driver is required, for example, the first driver may be a driver that drives the source-end FPGA in a kernel space, or a driver that drives the source-end FPGA in a user space.

Step S204, the source end sends the source address to the destination end, and the source address is used for the destination end to determine the destination address of the memory data to be transmitted in the destination end virtual machine through the first driver of the destination end and configure the destination address to the FPGA of the destination end, wherein the destination address is the virtual machine memory virtual address of the memory data to be transmitted in the destination end virtual machine;

as an optional embodiment, after the source end performs processing, for example, compression, on the source address through the source end FPGA, the source end sends the source address of the processed memory data to the destination end.

As an alternative embodiment, the destination may be a destination server, a destination memory, a destination device, or a destination module for storing memory data.

As an alternative embodiment, the destination may have the same structure as the source, the structure of the virtual space of the virtual machine of the destination depends on an operating system of the destination, and different operating systems may have different virtual spaces, for example, the virtual space of the destination may include a destination user space and a destination kernel space, the destination user space may be accessed by a user, and the memory data stored in the destination user space may be accessed by the user, so that the service user performs corresponding services. The destination kernel space is not accessible to the user, but the destination kernel space can perform data interaction with the destination user space, which is equivalent to that the destination user space and the destination kernel space can perform data interaction inside the destination.

As an optional embodiment, the destination FPGA is also a destination field-editable gate array, the source FPGA establishes a spatial data connection with the source kernel, obtains a source address of memory data output from a host memory virtual address, processes the source address, for example, translates the source address into a corresponding virtual memory virtual address, and sends the virtual memory virtual address to the destination FPGA, and the destination FPGA can decompress data processed and compressed by the source FPGA, so as to obtain the source address of the memory data. The memory data can be obtained through the source address.

As an optional embodiment, the destination FPGA is connected to the destination kernel space, and after obtaining the source address of the processed memory data, the destination FPGA performs inverse processing on the data, for example, converting the virtual machine memory virtual address into a corresponding source address, where it is noted that in the conversion process, the virtual machine memory virtual address of the source address of the memory data may be converted into a destination host machine memory virtual address of the destination virtual machine of the source address, and the destination host machine memory virtual address is sent to the destination kernel space, and the destination kernel space sends the destination address of the memory data to the destination user space, so that the user may recover access to the stored data in the destination user space.

As an optional embodiment, a destination virtual machine may be set in the destination user space, and is configured to store the memory data, and the structures of the destination and the source may be the same, so as to achieve the purpose of replacing the source with the destination for a user to access.

Step S206, the source end directly copies the memory data from the source address to the destination address through the source end FPGA and the destination end FPGA.

As an optional embodiment, the source FPGA and the destination FPGA may be transmitted through an ethernet or through a customized data transmission channel.

As an optional embodiment, the source FPGA and the destination FPGA may copy memory data of the virtual machine in the user space of the source from a source address to a destination address.

As an optional embodiment, the source end copies the memory data from the source address to the destination address, and may also implement backup of the memory data, where the memory data is stored in both the source address and the destination address, so as to implement backup of the memory data, and any one of the source address and the destination address may successfully call and access the memory data.

As an optional embodiment, the above steps may be applied to a virtual machine live migration process, and a peer-to-peer access from a source server to a destination server may be performed on the virtual machine live migration, which has an obvious acceleration effect compared to a data access manner of virtual machine live migration in the related art. In addition, the steps can also be applied to other cross-server data interaction access tasks, and data transmission can be performed on different servers and/or different addresses in a point-to-point manner.

Through the steps, a source end is adopted to configure a source address to a source end FPGA through a source end first drive, wherein the source address is a virtual machine memory virtual address of memory data to be transmitted in a source end virtual machine; the source end sends a source address to the destination end, the source address is used for the destination end to determine a destination address of memory data to be transmitted in a destination end virtual machine through a destination end first driver, and the destination address is configured to a destination end FPGA, wherein the destination address is a virtual machine memory virtual address of the memory data to be transmitted in the destination end virtual machine; the source end directly copies the memory data from the source address to the destination address through the source end FPGA and the destination end FPGA, and the purpose that the memory data is directly transmitted from the source end to the destination end through the hardware logic is achieved through the source end FPGA and the destination end FPGA, so that the technical effect that the memory data is directly transmitted from the source end to the destination end by using the hardware logic of the FPGA is achieved, multiple copies are not needed to be carried out at the source end, and multiple copies are carried out at the destination end, and the technical problems that in the related technology, the memory data are copied in a pure software mode, the efficiency is low, and the occupied resources are high are effectively solved.

As an alternative embodiment, the method further includes: the source end further sends the data length of the memory data and/or a source end identifier for identifying the source end to the destination end, wherein the data length is used for the destination end to apply for a memory space for the memory data, and the source end identifier is used for the destination end to verify the source end.

As an optional embodiment, when the source end transmits the memory data to the destination end, the source end may send the length of the memory data to the destination end at the same time, and after receiving the memory data and the data length of the memory data, the destination end applies for a memory space capable of storing the memory data in a virtual machine in a destination end user space of the destination end according to the data length, so as to prevent the memory data from being unable to be stored in a suitable space after being transmitted to the virtual machine, which may cause the memory data to be damaged or damaged.

As an optional embodiment, the source end identifier is used to identify an identity of the source end, and the destination end may verify the identity of the source end by using the source end identifier, and receive data transmission of the source end when the identity of the source end passes verification, so as to prevent the source end that does not correspond to the destination end or other data ends from sending data to the destination end, which results in that data of the source end that corresponds to the destination end cannot be migrated.

As an optional embodiment, the directly copying, by the source end through the source end FPGA and the destination end FPGA, the memory data from the source address to the destination address includes: and the source end compresses the memory data copied from the source address through the source end FPGA to obtain compressed data, and the destination end FPGA decompresses the compressed data obtained by copying and stores the decompressed compressed data into the destination address. The data is compressed at the source end and then transmitted, and the corresponding decompression is carried out at the destination end after the data is transmitted, so that the data volume in the transmission process is reduced to a certain extent, the transmission resources are saved to a certain extent, and the transmission efficiency is improved.

As an optional embodiment, the data transmission between the source end FPGA and the destination end FPGA may further perform encryption and decryption processing, and other various data processing manners.

As an alternative embodiment, the data path between the source end FPGA and the destination end FPGA includes at least one of the following: and reserving a ring network channel, wherein the reserved ring network channel is a source end FPGA and a destination end FPGA which realize a communication protocol in a hardware form and are directly connected into a network or an Ethernet channel through a physical link.

As an optional embodiment, the source end FPGA and the destination end FPGA transmit memory data through a data channel. The data channel can be a preset ring network channel or an Ethernet channel, and the data channel and the source end FPGA and the destination end FPGA both have communication protocols so as to ensure normal communication of data. The predetermined ring network channel can be a communication protocol realized by the source end FPGA and the destination end FPGA in a hardware form and is accessed to the network through a physical link.

As an optional embodiment, in a case that a data channel between a source end FPGA and a destination end FPGA is an ethernet channel, directly copying, by the source end, memory data from a source address to a destination address includes: the source end fills the memory data into the source end buffer area from the source address through a source end second drive driving source end FPGA, takes out the memory data from the source end buffer area, and sends the memory data to the destination end buffer area through the network card of the Ethernet; and the destination end drives the destination end FPGA to take out the memory data from the destination end buffer area through the destination end second drive, and stores the taken out memory data into a destination address.

As an alternative embodiment, under some special server architectures, for example, the server architecture cannot support RDMA data transmission in the conventional sense, the source FPGA and the destination FPGA may communicate via ethernet. Specifically, the source-end FPGA fills the buffer area with the memory data through the source-end second driver, and transmits the memory data to the destination end through the buffer area, the destination end has the same structure as the source-end, the destination-end network card receives the memory data, the destination-end network card fills the received data into the destination-end buffer area, and transmits the data to the destination-end FPGA through the destination-end second driver.

As an alternative embodiment, the second driver is similar to the first driver, and the second driver may drive the source FPGA in a kernel space, or may drive the source FPGA in a user space. The source-end network card and the source-end FPGA can be connected to the same hardware, and can also be separately arranged on two different hardware.

As an alternative embodiment, the source buffer and the destination buffer are fifo queues, and the size of each empty storage space in the fifo queue is determined according to the maximum transmission unit of the ethernet.

As an alternative embodiment, the source buffer may be a source FIFO queue, i.e., a source FIFO, and the size of each empty storage space in the FIFO queue depends on the size of the maximum transmission unit of the ethernet. The larger the maximum transmission unit of the ethernet is, the larger the blank storage space (i.e. storage unit) of the FIFO can be set; the smaller the maximum transmission unit of the ethernet, the smaller the empty memory space of the FIFO can be set.

As an optional embodiment, after the source directly copies the memory data from the source address to the destination address through the source FPGA and the destination FPGA, the method further includes: the source end empties the data configured in the source end FPGA, and sends a first notification message to the destination end, wherein the first notification message is used for notifying the destination end to empty the data configured in the destination end FPGA.

As an optional embodiment, after the source successfully copies the memory data to the destination, to prevent data leakage and reduce system load, the source deletes the data stored in the source FPGA and sends a first notification message for instructing the destination to delete the data configured in the destination FPGA, and the destination deletes the data configured in the destination FPGA after receiving the first notification message.

Example 2

According to another aspect of the embodiments of the present invention, there is also provided a memory data transmission method, and fig. 3 is a flowchart of another memory data transmission method according to embodiment 2 of the present invention, as shown in fig. 3, the method includes:

step S302, a destination end receives a source address sent by a source end, wherein the source address is a virtual machine memory virtual address of memory data to be transmitted in a source end virtual machine, and the source address is configured in a source end FPGA through a first driver of the source end;

step S304, the destination terminal converts the source address into a destination address through a first driver of the destination terminal and configures the destination address to the FPGA of the destination terminal, wherein the destination address is a virtual machine memory virtual address of memory data to be transmitted in a virtual machine of the destination terminal;

and S306, the destination terminal directly copies the memory data from the source address to the destination address through the source terminal FPGA and the destination terminal FPGA.

As an alternative embodiment, the source end sends the source address to the destination end before receiving the source address sent by the source end. The source address may be processed by the source end, and the source end virtual machine may be a virtual machine in the source end.

As an optional embodiment, the destination first driver may be the same as the source first driver, the source first driver is configured to configure the memory data to the source FPGA, the destination first driver is configured to convert a source address of the memory data of the destination FPGA into a destination address, and a user may access the memory data through the destination address.

Through the steps, a destination end is adopted to receive a source address sent by a source end, wherein the source address is a virtual machine memory virtual address of memory data to be transmitted in a source end virtual machine, and the source address is configured in a source end FPGA through a source end first drive; the destination terminal converts the source address into a destination address through a destination terminal first driver and configures the destination address to a destination terminal FPGA, wherein the destination address is a virtual machine memory virtual address of memory data to be transmitted in a destination terminal virtual machine; the target terminal directly copies the memory data from the source address to the target address through the source terminal FPGA and the target terminal FPGA, and the purpose that the memory data is directly transmitted from the source terminal to the target terminal through the hardware logic is achieved through the source terminal FPGA and the target terminal FPGA, so that the technical effect that the memory data is directly transmitted from the source terminal to the target terminal through the hardware logic of the FPGA is achieved, multiple copies are not needed to be carried out at the source terminal, and multiple copies are carried out at the target terminal, and the technical problems that in the related technology, the memory data are copied through a pure software mode, the efficiency is low, and the occupied resources are high are effectively solved.

As an alternative embodiment, the method further includes: the destination terminal also receives the data length of the memory data sent by the source terminal and/or a source terminal identification used for identifying the source terminal; and the destination terminal applies for the memory space for the memory data according to the data length and verifies the source terminal according to the source terminal identification.

As an optional embodiment, the directly copying, by the destination, the memory data from the source address to the destination address through the source FPGA and the destination FPGA includes: the destination end monitors the data length of the copied data in the copying process; and sending a second notification message to the source end for notifying the source end to stop data copying under the condition that the data length of the copied data is monitored to exceed the data length of the memory data to be transmitted, which is sent by the source end.

As an alternative embodiment, in the case that the data sent by the source end includes the length of the memory data, the transmitted memory data is monitored in real time. And under the condition that the length of the memory data reaches the length, considering that the memory data copying is finished, sending a second notification message for indicating the source end to stop data copying to the source end, and stopping data copying after the source end receives the second notification message.

As an optional embodiment, the directly copying, by the destination, the memory data from the source address to the destination address through the source FPGA and the destination FPGA includes: the destination end receives compressed data sent by the source end, wherein the compressed data is obtained by compressing memory data copied from a source address through the source end FPGA; and the destination terminal decompresses the compressed data through the destination terminal FPGA and stores the decompressed data into a destination address.

Example 3

According to another aspect of the embodiments of the present invention, there is also provided a memory data transmission method, and fig. 4 is a flowchart of another memory data transmission method according to embodiment 3 of the present invention, as shown in fig. 4, the method includes:

step S402, a source end configures a source address to a source end FPGA through a source end first drive, wherein the source address is a virtual machine memory virtual address of memory data to be transmitted in a source end virtual machine;

step S404, the source end sends the source address to the destination end;

step S406, the destination terminal converts the source address into a destination address through the destination terminal first driver, and configures the destination address to the destination terminal FPGA, wherein the destination address is a virtual machine memory virtual address of memory data in the destination terminal virtual machine;

step S408, the source end initiates data copying to the destination end, and the memory data is directly copied from the source address to the destination address through the source end FPGA and the destination end FPGA.

Through the steps, a source end is adopted to configure a source address to a source end FPGA through a source end first drive, wherein the source address is a virtual machine memory virtual address of memory data to be transmitted in a source end virtual machine; the source end sends the source address to the destination end; the destination terminal converts a source address into a destination address through a destination terminal first driver and configures the destination address to a destination terminal FPGA, wherein the destination address is a virtual machine memory virtual address of memory data in a destination terminal virtual machine; the source end initiates data copy to the destination end, the memory data is directly copied from a source address to a destination address through the source end FPGA and the destination end FPGA, the purpose that the memory data is directly transmitted from the source end to the destination end through hardware logic is achieved through the source end FPGA and the destination end FPGA, the technical effect that the memory data is directly transmitted from the source end to the destination end through the hardware logic of the FPGA is achieved, multiple copies are not needed to be carried out at the source end, multiple copies are carried out at the destination end, and the technical problems that in the related technology, the memory data are copied through a pure software mode, the efficiency is low, and the occupied resources are high are effectively solved.

As an alternative embodiment, the method further includes: the source end also sends the data length of the memory data and/or a source end identifier for identifying the source end to the destination end; and the destination terminal applies for the memory space for the memory data according to the data length and verifies the source terminal according to the source terminal identification.

As an optional embodiment, the initiating, by a source end, data copying to a destination end, and directly copying memory data from a source address to a destination address through a source end FPGA and a destination end FPGA includes: the source end compresses the memory data copied from the source address through the source end FPGA to obtain compressed data; and the destination end FPGA decompresses the compressed data and stores the decompressed data into a destination address.

As an alternative embodiment, the data path between the source end FPGA and the destination end FPGA includes at least one of the following: the method comprises the steps of presetting a ring network channel, wherein the preset ring network channel is a source end FPGA and a destination end FPGA which realize a communication protocol in a hardware form and are directly connected into a network through a physical link; an ethernet channel.

As an optional embodiment, in a case that a data channel between a source end FPGA and a destination end FPGA is an ethernet channel, directly copying, by the source end, memory data from a source address to a destination address includes: the source end fills the memory data into the source end buffer area from the source address through a source end second drive driving source end FPGA, takes out the memory data from the source end buffer area, and sends the memory data to the destination end buffer area through the network card of the Ethernet; and the destination end drives the destination end FPGA to take out the memory data from the destination end buffer area through a second driver of the destination end and stores the taken out memory data into a destination address.

As an optional embodiment, after initiating data copy from a source end to a destination end and directly copying memory data from a source address to a destination address through a source end FPGA and the destination end FPGA, the method further includes: the source end empties data configured in a source end FPGA and sends a first notification message to a destination end; and the destination terminal clears the data configured in the FPGA of the destination terminal according to the first notification message.

As an optional embodiment, the initiating, by a source end, data copying to a destination end, and directly copying memory data from a source address to a destination address through a source end FPGA and a destination end FPGA includes: the destination end monitors the data length of the copied data in the copying process; sending a second notification message to the source end under the condition that the data length of the copied data is monitored to exceed the data length of the memory data to be transmitted, which is sent by the source end; the source end stops data copying according to the second notification message.

Example 4

According to another aspect of the embodiments of the present invention, there is also provided a memory data transmission method, and fig. 5 is a flowchart of another memory data transmission method according to embodiment 4 of the present invention, as shown in fig. 5, the method includes:

step S502, a source end FPGA receives a source address configured by a first drive of a source end, wherein the source address is a virtual machine memory virtual address of memory data to be transmitted in a source end virtual machine;

step S504, when the destination address of the memory data to be transmitted in the destination virtual machine is configured to the destination FPGA, the source FPGA communicates with the destination FPGA to directly copy the memory data from the source address to the destination address, where the destination address is a virtual machine memory virtual address of the memory data to be transmitted in the destination virtual machine.

As an optional embodiment, the source FPGA communicates with the destination FPGA, and directly copying the memory data from the source address to the destination address includes: and the source end FPGA compresses the memory data copied from the source address to obtain compressed data, and the compressed data is decompressed by the destination end FPGA and stored into the destination address.

As an optional embodiment, in a case that a data channel between the source end FPGA and the destination end FPGA is an ethernet channel, the source end FPGA communicates with the destination end FPGA, and directly copying memory data from a source address to a destination address includes: the source end FPGA fills the memory data into a source end buffer area from a source address based on the drive of a source end second drive; the source end FPGA takes out the memory data from the source end buffer area, sends the memory data to the destination end buffer area through the network card of the Ethernet, and is used for the destination end FPGA to take out the memory data from the destination end buffer area based on the drive of the second drive of the destination end and store the taken out memory data into a destination address.

Example 5

According to another aspect of the embodiments of the present invention, there is also provided a memory data transmission method, and fig. 6 is a flowchart of another memory data transmission method according to embodiment 5 of the present invention, as shown in fig. 6, the method includes:

step S602, a destination end FPGA receives a destination address configured by a destination end first drive, wherein the destination address is a virtual machine memory virtual address of memory data to be transmitted in a destination end virtual machine, the destination address is obtained by source address conversion, the source address is a virtual machine memory virtual address of the memory data to be transmitted in a source end virtual machine, and the source address is configured in a source end FPGA through the source end first drive;

step S604, the destination FPGA communicates with the source FPGA, and the memory data is directly copied from the source address to the destination address.

As an optional embodiment, in a case that a data channel between the source FPGA and the destination FPGA is an ethernet channel, the destination FPGA communicates with the source FPGA, and directly copying memory data from a source address to a destination address includes: the destination terminal FPGA receives memory data which is taken out from the source terminal buffer area and sent by the network card of the Ethernet and stores the memory data into the destination terminal buffer area, wherein the memory data is filled into the source terminal buffer area from a source address through the drive of a source terminal second drive; and the destination terminal FPGA takes out the memory data from the destination terminal buffer area through the drive of the destination terminal second drive and stores the taken out memory data into a destination address.

Example 6

According to another aspect of the embodiments of the present invention, a virtual machine live migration memory data transmission scheme based on an FPGA is further provided, and the scheme is described in detail below.

Fig. 7 is a schematic diagram of a conventional thermomigration memory transmission method according to embodiment 6 of the present invention, as shown in fig. 7, in each memory iterative copy, memory data of a virtual machine is first copied from a user space of a source server to a kernel buffer, and is sent out through a network card after being processed by a network protocol stack; and the receiving end also needs to be processed by data copying and a protocol stack. These processes consume CPU computational power and increase data transfer time.

Fig. 8 is a schematic diagram of a point-to-point live migration memory transmission method based on an FPGA according to embodiment 6 of the present invention, where as shown in fig. 8, the FPGA implements a PCI protocol, becomes a PCI device on a server, and needs to integrate a driver of the device in a server kernel. The specific point-to-point memory transmission flow is as follows:

before each iterative copy, the source-end FPGA device driver sets an io bus address IOVA of memory data or a physical address HPA of a physical machine and a destination-end ID (if both ends need to be transmitted through ethernet, the ID may be a destination-end IP) to the FPGA. The IOMMU is a chip on the north bridge, and can convert a DMA (Direct Memory Access) address in the device into a host physical address, where the DMA address is an io bus address, iova. The DMA of the device can correctly access the system memory, and the io bus address may be identical to the HPA or may have a different mapping relationship. Host Virtual Address (HVA), which translates the device DMA into a corresponding physical address via IOMMU. The FPGA may be regarded as a peripheral device, so when the system performs migration configuration, a related driver is needed, but the driver may drive the FPGA in a kernel space, or drive the FPGA in a user space, in this scheme, as an optional implementation manner, as shown in fig. 8, the driver is set in the kernel space, and both the source-end FPGA and the destination-end FPGA are set in the kernel space.

The source sends a notification message to the destination, where the notification message includes a virtual machine memory physical address (GPA), a data length, and a source ID (for verification) to be transmitted. The destination end converts the physical memory address of the virtual machine into a host machine memory virtual address (HVA) corresponding to the destination end through FPGA drive, and simultaneously applies for necessary memory pages according to the data length. And the memory virtual address is configured to the FPGA together as a destination address of the data copy, a source end ID and a data length.

The source end initiates copying, the FPGA at the two ends carries out data communication, and data are directly copied from a source address to a destination address. In the copying process, the source end FPGA can select data compression, and the target end FPGA decompresses data. The destination end also needs to make a source check sum and a copied data length record, and once the copied data length is found to exceed the preset data length, the copying is stopped and the source end is informed.

After copying, the source end clears the data configuration (memory address, data size and destination end ID) in the FPGA and sends notification information to the destination end, and the destination end receives the notification and also clears the configuration (memory address, data size and source end ID) of the FPGA.

The channel between the two end FPGAs can be a self-defined data transmission channel or an Ethernet.

The self-defined channel can be a token ring network based on FPGA ID, and the FPGA realizes a communication protocol in a hardware form and is directly connected into a network through a physical link.

Under the server architecture, data transmission can be carried out between the FPGAs through the Ethernet. At this time, an FPGA driver (driver B) needs to be introduced into the management and control node, and a software FIFO queue is used for data buffering. Fig. 9 is a schematic diagram of a method for applying a point-to-point conventional live migration memory transfer based on an FPGA to a server architecture according to embodiment 6 of the present invention, as shown in fig. 9:

before data Transmission, driver B will set the size of each entry in the FIFO according to the network MTU (maximum Transmission Unit) size.

In data transmission, the drive B sequentially fills data into the tail part of the FIFO queue.

Meanwhile, the driver B takes out data from the head of the FIFO queue and sends the data through the network card (via the management and control node protocol stack or the network card itself supporting toe (tcp offload engine)).

The size of the FIFO queue can be preconfigured and drive B will signal the FPGA to suspend copying once the FIFO is full. When FIFO has space, drive B will inform FPGA to continue copying.

And the destination end driver B puts the data received by the network into the tail part of the FIFO, and simultaneously takes out the data from the head part of the FIFO and sends the data to the FPGA to complete copying.

In the embodiment, the method is specially designed for the live migration of the virtual machine and is based on the FPGA memory data transmission method; the FPGA realizes the hot migration memory compression and decompression; the method for the two-end FPGA to communicate through the Ethernet under the server architecture is provided.

It should be noted that, for simplicity of description, the above-mentioned method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the present invention is not limited by the order of acts, as some steps may occur in other orders or concurrently in accordance with the invention. Further, those skilled in the art should also appreciate that the embodiments described in the specification are preferred embodiments and that the acts and modules referred to are not necessarily required by the invention.

Through the above description of the embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but the former is a better implementation mode in many cases. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which is stored in a storage medium (e.g., ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a terminal device (e.g., a mobile phone, a computer, a server, or a network device) to execute the method according to the embodiments of the present invention.

Example 7

According to an embodiment of the present invention, there is further provided a source server for implementing the memory data transmission method described in embodiment 1, where fig. 10 is a schematic diagram of a source server according to embodiment 7 of the present invention, and as shown in fig. 10, the apparatus includes: a configuration module 1002, a sending module 1004, and a first copy module 1006, which are described in detail below.

A configuration module 1002, configured to configure a source address to a source-end FPGA through a source-end first driver, where the source address is a virtual machine memory physical address of memory data to be transmitted in a source-end virtual machine; a sending module 1004, connected to the configuring module 1002, configured to send a source address to a destination, where the destination determines a destination address of the memory data to be transmitted in the destination virtual machine through a destination first driver, and configures the destination address to a destination FPGA, where the destination address is a physical address of a virtual machine memory of the memory data to be transmitted in the destination virtual machine; the first copying module 1006 is connected to the sending module 1004, and is configured to directly copy the memory data from the source address to the destination address through the source FPGA and the destination FPGA.

It should be noted here that the configuration module 1002, the sending module 1004, and the first copying module 1006 correspond to steps S202 to S206 in embodiment 1, and the three modules are the same as the corresponding steps in the implementation example and application scenario, but are not limited to the disclosure in embodiment 1. It should be noted that the above modules may be operated in the computer terminal 10 provided in embodiment 1 as a part of the apparatus.

Example 8

According to an embodiment of the present invention, there is further provided a destination server for implementing the memory data transmission method described in embodiment 2, where fig. 11 is a schematic diagram of a destination server according to embodiment 8 of the present invention, and as shown in fig. 11, the apparatus includes: a first receiving module 1102, a converting module 1104 and a second copying module 1106, which are described in detail below.

A first receiving module 1102, configured to receive a source address sent by a source end, where the source address is a virtual machine memory physical address of memory data to be transmitted in a source end virtual machine, and the source address is configured in a source end FPGA through a source end first driver; a conversion module 1104, connected to the first receiving module 1102, and configured to convert a source address into a destination address through a destination first driver, and configure the destination address to a destination FPGA, where the destination address is a physical address of a virtual machine memory of memory data to be transmitted in a destination virtual machine; and a second copy module 1106, connected to the conversion module 1104, and configured to directly copy the memory data from the source address to the destination address through the source FPGA and the destination FPGA.

It should be noted here that the first receiving module 1102, the converting module 1104 and the second copying module 1106 correspond to steps S302 to S306 in embodiment 2, and the three modules are the same as the corresponding steps in the implementation example and application scenario, but are not limited to the disclosure in embodiment 2. It should be noted that the above modules may be operated in the computer terminal 10 provided in embodiment 1 as a part of the apparatus.

Example 9

According to an embodiment of the present invention, there is further provided a memory data transmission system for implementing the memory data transmission method described in embodiment 3, where fig. 12 is a schematic diagram of a data transmission system according to embodiment 9 of the present invention, and as shown in fig. 12, the apparatus includes: a source peer 1202 and a destination peer 1204, the devices of which are described in detail below.

The source end 1202 is configured with a source end FPGA, the destination end 1204 is configured with a destination end FPGA, and the source end 1202 is configured to configure a source address to the source end FPGA through a first driver of the source end and send the source address to the destination end, where the source address is a physical address of a virtual machine memory of memory data to be transmitted in a source end virtual machine; the destination 1204 is configured to convert the source address into a destination address through a destination first driver, and configure the destination address to the destination FPGA, where the destination address is a physical address of a virtual machine memory of memory data to be transmitted in a destination virtual machine; the source end 1202 is further configured to initiate data copying to the destination end, and directly copy the memory data from the source address to the destination address through the source end FPGA and the destination end FPGA.

It should be noted here that the source end 1202 and the destination end 1204 correspond to steps S402 to S408 in embodiment 3, and both ends are the same as the example and application scenario realized by the corresponding steps, but are not limited to the disclosure in embodiment 3. It should be noted that the above modules may be operated in the computer terminal 10 provided in embodiment 1 as a part of the apparatus.

Example 10

According to an embodiment of the present invention, there is further provided a destination server for implementing the memory data transmission method described in embodiment 2, where fig. 13 is a schematic diagram of a memory data transmission apparatus according to embodiment 10 of the present invention, and as shown in fig. 13, the apparatus includes: a second receiving module 1302 and a third copying module 1304, which will be described in detail below.

A second receiving module 1302, configured to receive, by the source-end FPGA, a source address configured by a first driver at the source end, where the source address is a virtual machine memory virtual address of memory data to be transmitted in the source-end virtual machine; a third copying module 1304, connected to the second receiving module 1302, configured to, when a destination address of the memory data to be transmitted in the destination virtual machine is configured to the destination FPGA, communicate between the source FPGA and the destination FPGA, and directly copy the memory data from the source address to the destination address, where the destination address is a virtual machine memory virtual address of the memory data to be transmitted in the destination virtual machine.

It should be noted here that the second receiving module 1302 and the third copying module 1304 correspond to steps S502 to S504 in embodiment 4, and the three modules are the same as the corresponding steps in the implementation example and application scenario, but are not limited to the disclosure in embodiment 4. It should be noted that the above modules may be operated in the computer terminal 10 provided in embodiment 1 as a part of the apparatus.

Example 11

According to an embodiment of the present invention, there is further provided a destination server for implementing the memory data transmission method described in embodiment 2, where fig. 14 is a schematic diagram of a memory data transmission apparatus according to embodiment 11 of the present invention, and as shown in fig. 14, the apparatus includes: a third receiving module 1402 and a fourth copying module 1404, which will be described in detail below.

A third receiving module 1402, configured to receive, by the destination FPGA, a destination address configured by a destination first driver, where the destination address is a virtual machine memory virtual address of memory data to be transmitted in a destination virtual machine, the destination address is obtained by converting a source address, the source address is a virtual machine memory virtual address of the memory data to be transmitted in a source virtual machine, and the source address is configured in the source FPGA through the source first driver; and a fourth copying module 1404, connected to the third receiving module 1402, configured to communicate between the destination FPGA and the source FPGA, and directly copy the memory data from the source address to the destination address.

It should be noted here that the third receiving module 1402 and the fourth copying module 1404 correspond to steps S602 to S604 in embodiment 5, and the three modules are the same as the corresponding steps in the implementation example and application scenario, but are not limited to the disclosure of embodiment 5. It should be noted that the above modules may be operated in the computer terminal 10 provided in embodiment 1 as a part of the apparatus.

Example 12

The embodiment of the invention can provide a computer terminal which can be any computer terminal device in a computer terminal group. Optionally, in this embodiment, the computer terminal may also be replaced with a terminal device such as a mobile terminal.

Optionally, in this embodiment, the computer terminal may be located in at least one network device of a plurality of network devices of a computer network.

In this embodiment, the computer terminal may execute the program code of the following steps in the memory data transmission method of the application program: the source end configures a source address to the source end FPGA through a first driver of the source end, wherein the source address is a virtual machine memory virtual address of memory data to be transmitted in a source end virtual machine; the source end sends a source address to the destination end, the source address is used for the destination end to determine a destination address of memory data to be transmitted in a destination end virtual machine through a destination end first driver, and the destination address is configured to a destination end FPGA, wherein the destination address is a virtual machine memory virtual address of the memory data to be transmitted in the destination end virtual machine; the source end directly copies the memory data from the source address to the destination address through the source end FPGA and the destination end FPGA.

Alternatively, fig. 15 is a block diagram of a computer terminal according to embodiment 12 of the present invention. As shown in fig. 15, the computer terminal 150 may include: one or more processors 152 (only one shown), memory 154, and a peripheral interface.

The memory may be used to store software programs and modules, such as program instructions/modules corresponding to the memory data transmission method and apparatus in the embodiments of the present invention, and the processor executes various functional applications and data processing by operating the software programs and modules stored in the memory, that is, the memory data transmission method is implemented. The memory may include high speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory may further include memory located remotely from the processor, which may be connected to the terminal 150 via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

The processor can call the information and application program stored in the memory through the transmission device to execute the following steps: the source end configures a source address to the source end FPGA through a first driver of the source end, wherein the source address is a virtual machine memory virtual address of memory data to be transmitted in a source end virtual machine; the source end sends a source address to the destination end, the source address is used for the destination end to determine a destination address of memory data to be transmitted in a destination end virtual machine through a destination end first driver, and the destination address is configured to a destination end FPGA, wherein the destination address is a virtual machine memory virtual address of the memory data to be transmitted in the destination end virtual machine; the source end directly copies the memory data from the source address to the destination address through the source end FPGA and the destination end FPGA.

Optionally, the processor may further execute the program code of the following steps: the method further comprises the following steps: the source end further sends the data length of the memory data and/or a source end identifier for identifying the source end to the destination end, wherein the data length is used for the destination end to apply for a memory space for the memory data, and the source end identifier is used for the destination end to verify the source end.

Optionally, the processor may further execute the program code of the following steps: the source end directly copies the memory data from the source address to the destination address through the source end FPGA and the destination end FPGA, and the method comprises the following steps: and the source end compresses the memory data copied from the source address through the source end FPGA to obtain compressed data, and the destination end FPGA decompresses the compressed data obtained by copying and stores the decompressed compressed data into the destination address.

Optionally, the processor may further execute the program code of the following steps: the data channel between the source end FPGA and the destination end FPGA comprises at least one of the following: the method comprises the steps of presetting a ring network channel, wherein the preset ring network channel is a source end FPGA and a destination end FPGA which realize a communication protocol in a hardware form and are directly connected into a network through a physical link; an ethernet channel.

Optionally, the processor may further execute the program code of the following steps: under the condition that a data channel between a source end FPGA and a destination end FPGA is an Ethernet channel, the step of directly copying memory data from a source address to a destination address by the source end comprises the following steps: the source end fills the memory data into the source end buffer area from the source address through a source end second drive driving source end FPGA, takes out the memory data from the source end buffer area, and sends the memory data to the destination end buffer area through the network card of the Ethernet; and the destination end drives the destination end FPGA to take out the memory data from the destination end buffer area through the destination end second drive, and stores the taken out memory data into a destination address.

Optionally, the processor may further execute the program code of the following steps: the source end buffer area and the destination end buffer area are first-in first-out queues, and the size of each blank storage space in the first-in first-out queues is determined according to the maximum transmission unit of the Ethernet.

Optionally, the processor may further execute the program code of the following steps: after the source end directly copies the memory data from the source address to the destination address through the source end FPGA and the destination end FPGA, the method further comprises the following steps: the source end empties the data configured in the source end FPGA, and sends a first notification message to the destination end, wherein the first notification message is used for notifying the destination end to empty the data configured in the destination end FPGA.

The processor can also call the information stored in the memory and the application program through the transmission device to execute the following steps: the destination end receives a source address sent by the source end, wherein the source address is a virtual machine memory virtual address of memory data to be transmitted in the source end virtual machine, and the source address is configured in the source end FPGA through a first driver of the source end; the destination terminal converts the source address into a destination address through a destination terminal first driver and configures the destination address to a destination terminal FPGA, wherein the destination address is a virtual machine memory virtual address of memory data to be transmitted in a destination terminal virtual machine; and the destination terminal directly copies the memory data from the source address to the destination address through the source terminal FPGA and the destination terminal FPGA.

Optionally, the processor may further execute the program code of the following steps: the method further comprises the following steps: the destination terminal also receives the data length of the memory data sent by the source terminal and/or a source terminal identification used for identifying the source terminal; and the destination terminal applies for the memory space for the memory data according to the data length and verifies the source terminal according to the source terminal identification.

Optionally, the processor may further execute the program code of the following steps: the target terminal directly copies the memory data from the source address to the target address through the source terminal FPGA and the target terminal FPGA, and the method comprises the following steps: the destination end monitors the data length of the copied data in the copying process; and sending a second notification message to the source end for notifying the source end to stop data copying under the condition that the data length of the copied data is monitored to exceed the data length of the memory data to be transmitted, which is sent by the source end.

Optionally, the processor may further execute the program code of the following steps: the target terminal directly copies the memory data from the source address to the target address through the source terminal FPGA and the target terminal FPGA, and the method comprises the following steps: the destination end receives compressed data sent by the source end, wherein the compressed data is obtained by compressing memory data copied from a source address through the source end FPGA; and the destination terminal decompresses the compressed data through the destination terminal FPGA and stores the decompressed data into a destination address.

The processor can also call the information stored in the memory and the application program through the transmission device to execute the following steps: the source end configures a source address to the source end FPGA through a first driver of the source end, wherein the source address is a virtual machine memory virtual address of memory data to be transmitted in a source end virtual machine; the source end sends the source address to the destination end; the destination terminal converts a source address into a destination address through a destination terminal first driver, and configures the destination address to a destination terminal FPGA, wherein the destination address is a virtual machine memory virtual address of memory data to be transmitted in a destination terminal virtual machine; the source end initiates data copy to the destination end, and the memory data is directly copied from a source address to a destination address through the source end FPGA and the destination end FPGA.

Optionally, the processor may further execute the program code of the following steps: the method further comprises the following steps: the source end also sends the data length of the memory data and/or a source end identifier for identifying the source end to the destination end; and the destination terminal applies for the memory space for the memory data according to the data length and verifies the source terminal according to the source terminal identification.

Optionally, the processor may further execute the program code of the following steps: the source end initiates data copy to the destination end, and the step of directly copying the memory data from the source address to the destination address through the source end FPGA and the destination end FPGA comprises the following steps: the source end compresses the memory data copied from the source address through the source end FPGA to obtain compressed data; and the destination end FPGA decompresses the compressed data and stores the decompressed data into a destination address.

Optionally, the processor may further execute the program code of the following steps: under the condition that a data channel between a source end FPGA and a destination end FPGA is an Ethernet channel, the step of directly copying memory data from a source address to a destination address by the source end comprises the following steps: the source end fills the memory data into the source end buffer area from the source address through a source end second drive driving source end FPGA, takes out the memory data from the source end buffer area, and sends the memory data to the destination end buffer area through the network card of the Ethernet; and the destination end drives the destination end FPGA to take out the memory data from the destination end buffer area through a second driver of the destination end and stores the taken out memory data into a destination address.

Optionally, the processor may further execute the program code of the following steps: initiating data copy from a source end to a destination end, and directly copying memory data from a source address to a destination address through a source end FPGA and the destination end FPGA, and the method further comprises the following steps: the source end empties data configured in a source end FPGA and sends a first notification message to a destination end; and the destination terminal clears the data configured in the FPGA of the destination terminal according to the first notification message.

Optionally, the processor may further execute the program code of the following steps: the source end initiates data copy to the destination end, and the step of directly copying the memory data from the source address to the destination address through the source end FPGA and the destination end FPGA comprises the following steps: the destination end monitors the data length of the copied data in the copying process; sending a second notification message to the source end under the condition that the data length of the copied data is monitored to exceed the data length of the memory data to be transmitted, which is sent by the source end; the source end stops data copying according to the second notification message.

The processor can also call the information stored in the memory and the application program through the transmission device to execute the following steps: the source end FPGA receives a source address configured by a first driver of the source end, wherein the source address is a virtual machine memory virtual address of memory data to be transmitted in a source end virtual machine; under the condition that the destination address of the memory data to be transmitted in the destination virtual machine is configured to the destination FPGA, the source FPGA communicates with the destination FPGA to directly copy the memory data from the source address to the destination address, wherein the destination address is the virtual machine memory virtual address of the memory data to be transmitted in the destination virtual machine.

Optionally, the processor may further execute the program code of the following steps: the source end FPGA communicates with the destination end FPGA, and directly copying the memory data from the source address to the destination address comprises the following steps: and the source end FPGA compresses the memory data copied from the source address to obtain compressed data, and the compressed data is decompressed by the destination end FPGA and stored into the destination address.

Optionally, the processor may further execute the program code of the following steps: under the condition that a data channel between a source end FPGA and a destination end FPGA is an Ethernet channel, the source end FPGA communicates with the destination end FPGA, and directly copying memory data from a source address to a destination address comprises the following steps: the source end FPGA fills the memory data into a source end buffer area from a source address based on the drive of a source end second drive; the source end FPGA takes out the memory data from the source end buffer area, sends the memory data to the destination end buffer area through the network card of the Ethernet, and is used for the destination end FPGA to take out the memory data from the destination end buffer area based on the drive of the second drive of the destination end and store the taken out memory data into a destination address.

The processor can also call the information stored in the memory and the application program through the transmission device to execute the following steps: the method comprises the steps that a destination end FPGA receives a destination address configured by a destination end first drive, wherein the destination address is a virtual machine memory virtual address of memory data to be transmitted in a destination end virtual machine, the destination address is obtained by converting a source address, the source address is a virtual machine memory virtual address of the memory data to be transmitted in a source end virtual machine, and the source address is configured in a source end FPGA through the source end first drive; and the destination end FPGA communicates with the source end FPGA and directly copies the memory data from the source address to the destination address.

Optionally, the processor may further execute the program code of the following steps: under the condition that a data channel between a source end FPGA and a destination end FPGA is an Ethernet channel, the destination end FPGA communicates with the source end FPGA, and directly copying memory data from a source address to a destination address comprises the following steps: the destination terminal FPGA receives memory data which is taken out from the source terminal buffer area and sent by the network card of the Ethernet and stores the memory data into the destination terminal buffer area, wherein the memory data is filled into the source terminal buffer area from a source address through the drive of a source terminal second drive; and the destination terminal FPGA takes out the memory data from the destination terminal buffer area through the drive of the destination terminal second drive and stores the taken out memory data into a destination address.

The embodiment of the invention provides a scheme of a memory data transmission method. Configuring a source address to a source-end FPGA by a source-end first driver, wherein the source address is a virtual machine memory virtual address of memory data to be transmitted in a source-end virtual machine; the source end sends a source address to the destination end, the source address is used for the destination end to determine a destination address of memory data to be transmitted in a destination end virtual machine through a destination end first driver, and the destination address is configured to a destination end FPGA, wherein the destination address is a virtual machine memory virtual address of the memory data to be transmitted in the destination end virtual machine; the source end directly copies the memory data from the source address to the destination address through the source end FPGA and the destination end FPGA, and the purpose that the memory data is directly transmitted from the source end to the destination end through the hardware logic is achieved through the source end FPGA and the destination end FPGA, so that the technical effect that the memory data is directly transmitted from the source end to the destination end by using the hardware logic of the FPGA is achieved, multiple copies are not needed to be carried out at the source end, and multiple copies are carried out at the destination end, and the technical problems that in the related technology, the memory data are copied in a pure software mode, the efficiency is low, and the occupied resources are high are effectively solved.

It can be understood by those skilled in the art that the structure shown in fig. 11 is only an illustration, and the computer terminal may also be a terminal device such as a smart phone (e.g., an Android phone, an iOS phone, etc.), a tablet computer, a palmtop computer, a Mobile Internet Device (MID), a PAD, and the like. Fig. 11 is a diagram illustrating a structure of the electronic device. For example, computer terminal 110 may also include more or fewer components (e.g., network interfaces, display devices, etc.) than shown in FIG. 11, or have a different configuration than shown in FIG. 11.

Those skilled in the art will appreciate that all or part of the steps in the methods of the above embodiments may be implemented by a program instructing hardware associated with the terminal device, where the program may be stored in a computer-readable storage medium, and the storage medium may include: flash disks, Read-Only memories (ROMs), Random Access Memories (RAMs), magnetic or optical disks, and the like.

Example 8

The embodiment of the invention also provides a storage medium. Optionally, in this embodiment, the storage medium may be configured to store a program code executed by the memory data transmission method provided in the first embodiment.

Optionally, in this embodiment, the storage medium may be located in any one of computer terminals in a computer terminal group in a computer network, or in any one of mobile terminals in a mobile terminal group.

Optionally, in this embodiment, the storage medium is configured to store program code for performing the following steps: the source end configures a source address to the source end FPGA through a first driver of the source end, wherein the source address is a virtual machine memory virtual address of memory data to be transmitted in a source end virtual machine; the source end sends a source address to the destination end, the source address is used for the destination end to determine a destination address of memory data to be transmitted in a destination end virtual machine through a destination end first driver, and the destination address is configured to a destination end FPGA, wherein the destination address is a virtual machine memory virtual address of the memory data to be transmitted in the destination end virtual machine; the source end directly copies the memory data from the source address to the destination address through the source end FPGA and the destination end FPGA.

Optionally, in this embodiment, the storage medium is configured to store program code for performing the following steps: the method further comprises the following steps: the source end further sends the data length of the memory data and/or a source end identifier for identifying the source end to the destination end, wherein the data length is used for the destination end to apply for a memory space for the memory data, and the source end identifier is used for the destination end to verify the source end.

Optionally, in this embodiment, the storage medium is configured to store program code for performing the following steps: the source end directly copies the memory data from the source address to the destination address through the source end FPGA and the destination end FPGA, and the method comprises the following steps: and the source end compresses the memory data copied from the source address through the source end FPGA to obtain compressed data, and the destination end FPGA decompresses the compressed data obtained by copying and stores the decompressed compressed data into the destination address.

Optionally, in this embodiment, the storage medium is configured to store program code for performing the following steps: the data channel between the source end FPGA and the destination end FPGA comprises at least one of the following: the method comprises the steps of presetting a ring network channel, wherein the preset ring network channel is a source end FPGA and a destination end FPGA which realize a communication protocol in a hardware form and are directly connected into a network through a physical link; an ethernet channel.

Optionally, in this embodiment, the storage medium is configured to store program code for performing the following steps: under the condition that a data channel between a source end FPGA and a destination end FPGA is an Ethernet channel, the step of directly copying memory data from a source address to a destination address by the source end comprises the following steps: the source end fills the memory data into the source end buffer area from the source address through a source end second drive driving source end FPGA, takes out the memory data from the source end buffer area, and sends the memory data to the destination end buffer area through the network card of the Ethernet; and the destination end drives the destination end FPGA to take out the memory data from the destination end buffer area through the destination end second drive, and stores the taken out memory data into a destination address.

Optionally, in this embodiment, the storage medium is configured to store program code for performing the following steps: the source end buffer area and the destination end buffer area are first-in first-out queues, and the size of each blank storage space in the first-in first-out queues is determined according to the maximum transmission unit of the Ethernet.

Optionally, in this embodiment, the storage medium is configured to store program code for performing the following steps: after the source end directly copies the memory data from the source address to the destination address through the source end FPGA and the destination end FPGA, the method further comprises the following steps: the source end empties the data configured in the source end FPGA, and sends a first notification message to the destination end, wherein the first notification message is used for notifying the destination end to empty the data configured in the destination end FPGA.

Optionally, in this embodiment, the storage medium is configured to store program code for performing the following steps: the destination end receives a source address sent by the source end, wherein the source address is a virtual machine memory virtual address of memory data to be transmitted in the source end virtual machine, and the source address is configured in the source end FPGA through a first driver of the source end; the destination terminal converts the source address into a destination address through a destination terminal first driver and configures the destination address to a destination terminal FPGA, wherein the destination address is a virtual machine memory virtual address of memory data to be transmitted in a destination terminal virtual machine; and the destination terminal directly copies the memory data from the source address to the destination address through the source terminal FPGA and the destination terminal FPGA.

Optionally, in this embodiment, the storage medium is configured to store program code for performing the following steps: the method further comprises the following steps: the destination terminal also receives the data length of the memory data sent by the source terminal and/or a source terminal identification used for identifying the source terminal; and the destination terminal applies for the memory space for the memory data according to the data length and verifies the source terminal according to the source terminal identification.

Optionally, in this embodiment, the storage medium is configured to store program code for performing the following steps: the target terminal directly copies the memory data from the source address to the target address through the source terminal FPGA and the target terminal FPGA, and the method comprises the following steps: the destination end monitors the data length of the copied data in the copying process; and sending a second notification message to the source end for notifying the source end to stop data copying under the condition that the data length of the copied data is monitored to exceed the data length of the memory data to be transmitted, which is sent by the source end.

Optionally, in this embodiment, the storage medium is configured to store program code for performing the following steps: the target terminal directly copies the memory data from the source address to the target address through the source terminal FPGA and the target terminal FPGA, and the method comprises the following steps: the destination end receives compressed data sent by the source end, wherein the compressed data is obtained by compressing memory data copied from a source address through the source end FPGA; and the destination terminal decompresses the compressed data through the destination terminal FPGA and stores the decompressed data into a destination address.

Optionally, in this embodiment, the storage medium is configured to store program code for performing the following steps: the source end configures a source address to the source end FPGA through a first driver of the source end, wherein the source address is a virtual machine memory virtual address of memory data to be transmitted in a source end virtual machine; the source end sends the source address to the destination end; the destination terminal converts a source address into a destination address through a destination terminal first driver, and configures the destination address to a destination terminal FPGA, wherein the destination address is a virtual machine memory virtual address of memory data with transmission in a destination terminal virtual machine; the source end initiates data copy to the destination end, and the memory data is directly copied from a source address to a destination address through the source end FPGA and the destination end FPGA.

Optionally, in this embodiment, the storage medium is configured to store program code for performing the following steps: the method further comprises the following steps: the source end also sends the data length of the memory data and/or a source end identifier for identifying the source end to the destination end; and the destination terminal applies for the memory space for the memory data according to the data length and verifies the source terminal according to the source terminal identification.

Optionally, in this embodiment, the storage medium is configured to store program code for performing the following steps: the source end initiates data copy to the destination end, and the step of directly copying the memory data from the source address to the destination address through the source end FPGA and the destination end FPGA comprises the following steps: the source end compresses the memory data copied from the source address through the source end FPGA to obtain compressed data; and the destination end FPGA decompresses the compressed data and stores the decompressed data into a destination address.

Optionally, in this embodiment, the storage medium is configured to store program code for performing the following steps: under the condition that a data channel between a source end FPGA and a destination end FPGA is an Ethernet channel, the step of directly copying memory data from a source address to a destination address by the source end comprises the following steps: the source end fills the memory data into the source end buffer area from the source address through a source end second drive driving source end FPGA, takes out the memory data from the source end buffer area, and sends the memory data to the destination end buffer area through the network card of the Ethernet; and the destination end drives the destination end FPGA to take out the memory data from the destination end buffer area through a second driver of the destination end and stores the taken out memory data into a destination address.

Optionally, in this embodiment, the storage medium is configured to store program code for performing the following steps: initiating data copy from a source end to a destination end, and directly copying memory data from a source address to a destination address through a source end FPGA and the destination end FPGA, and the method further comprises the following steps: the source end empties data configured in a source end FPGA and sends a first notification message to a destination end; and the destination terminal clears the data configured in the FPGA of the destination terminal according to the first notification message.

Optionally, in this embodiment, the storage medium is configured to store program code for performing the following steps: the source end initiates data copy to the destination end, and the step of directly copying the memory data from the source address to the destination address through the source end FPGA and the destination end FPGA comprises the following steps: the destination end monitors the data length of the copied data in the copying process; sending a second notification message to the source end under the condition that the data length of the copied data is monitored to exceed the data length of the memory data to be transmitted, which is sent by the source end; the source end stops data copying according to the second notification message.

Optionally, in this embodiment, the storage medium is configured to store program code for performing the following steps: the source end FPGA receives a source address configured by a first driver of the source end, wherein the source address is a virtual machine memory virtual address of memory data to be transmitted in a source end virtual machine; under the condition that the destination address of the memory data to be transmitted in the destination virtual machine is configured to the destination FPGA, the source FPGA communicates with the destination FPGA to directly copy the memory data from the source address to the destination address, wherein the destination address is the virtual machine memory virtual address of the memory data to be transmitted in the destination virtual machine.

Optionally, in this embodiment, the storage medium is configured to store program code for performing the following steps: the source end FPGA communicates with the destination end FPGA, and directly copying the memory data from the source address to the destination address comprises the following steps: and the source end FPGA compresses the memory data copied from the source address to obtain compressed data, and the compressed data is decompressed by the destination end FPGA and stored into the destination address.

Optionally, in this embodiment, the storage medium is configured to store program code for performing the following steps: under the condition that a data channel between a source end FPGA and a destination end FPGA is an Ethernet channel, the source end FPGA communicates with the destination end FPGA, and directly copying memory data from a source address to a destination address comprises the following steps: the source end FPGA fills the memory data into a source end buffer area from a source address based on the drive of a source end second drive; the source end FPGA takes out the memory data from the source end buffer area, sends the memory data to the destination end buffer area through the network card of the Ethernet, and is used for the destination end FPGA to take out the memory data from the destination end buffer area based on the drive of the second drive of the destination end and store the taken out memory data into a destination address.

Optionally, in this embodiment, the storage medium is configured to store program code for performing the following steps: the method comprises the steps that a destination end FPGA receives a destination address configured by a destination end first drive, wherein the destination address is a virtual machine memory virtual address of memory data to be transmitted in a destination end virtual machine, the destination address is obtained by converting a source address, the source address is a virtual machine memory virtual address of the memory data to be transmitted in a source end virtual machine, and the source address is configured in a source end FPGA through the source end first drive; and the destination end FPGA communicates with the source end FPGA and directly copies the memory data from the source address to the destination address.

Optionally, in this embodiment, the storage medium is configured to store program code for performing the following steps: under the condition that a data channel between a source end FPGA and a destination end FPGA is an Ethernet channel, the destination end FPGA communicates with the source end FPGA, and directly copying memory data from a source address to a destination address comprises the following steps: the destination terminal FPGA receives memory data which is taken out from the source terminal buffer area and sent by the network card of the Ethernet and stores the memory data into the destination terminal buffer area, wherein the memory data is filled into the source terminal buffer area from a source address through the drive of a source terminal second drive; and the destination terminal FPGA takes out the memory data from the destination terminal buffer area through the drive of the destination terminal second drive and stores the taken out memory data into a destination address.

The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.

In the above embodiments of the present invention, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

In the embodiments provided in the present application, it should be understood that the disclosed technology can be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one type of division of logical functions, and there may be other divisions when actually implemented, for example, a plurality of units or components may be combined or may be integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, units or modules, and may be in an electrical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.

Claims

1. A memory data transmission method is characterized by comprising the following steps:

the source end configures a source address to a source end FPGA through a source end first driver, wherein the source address is a virtual machine memory virtual address of memory data to be transmitted in a source end virtual machine;

the source end sends the source address to a destination end, and the source end is used for determining a destination address of the memory data to be transmitted in a destination end virtual machine through a destination end first driver and configuring the destination address to a destination end FPGA, wherein the destination address is a virtual machine memory virtual address of the memory data to be transmitted in the destination end virtual machine;

and the source end directly copies the memory data from the source address to the destination address through the source end FPGA and the destination end FPGA.

2. The method of claim 1, further comprising:

the source end further sends the data length of the memory data and/or a source end identifier for identifying the source end to the destination end, wherein the data length is used for the destination end to apply for a memory space for the memory data, and the source end identifier is used for the destination end to verify the source end.

3. The method of claim 1, wherein the source directly copying the memory data from the source address to the destination address through the source FPGA and the destination FPGA comprises:

and the source end compresses the memory data copied from the source address through the source end FPGA to obtain compressed data, wherein the destination end FPGA decompresses the compressed data obtained by copying and stores the decompressed data into the destination address.

4. The method of any of claims 1 to 3, wherein the data path between the source FPGA and the destination FPGA comprises at least one of:

a preset ring network channel, wherein the preset ring network channel is used for realizing a communication protocol between the source end FPGA and the destination end FPGA in a hardware form and is directly connected into a network through a physical link;

an ethernet channel.

5. The method of claim 4, wherein, in the case that a data channel between the source FPGA and the destination FPGA is an Ethernet channel, the source directly copying the memory data from the source address to the destination address comprises:

the source end drives the source end FPGA through a second driver of the source end to fill the memory data into a source end buffer area from the source address, takes out the memory data from the source end buffer area, and sends the memory data to a destination end buffer area through a network card of the Ethernet; and the destination drives the destination FPGA to take out the memory data from the destination buffer area through a destination second drive, and stores the taken out memory data into the destination address.

6. The method of claim 5, wherein the source buffer and the destination buffer are first-in-first-out queues, and a size of each empty storage space in the first-in-first-out queues is determined according to a maximum transmission unit of the Ethernet.

7. The method of claim 4, after the source side directly copies the memory data from the source address to the destination address through the source side FPGA and the destination side FPGA, further comprising:

the source end empties the data configured in the source end FPGA, and sends a first notification message to the destination end, so as to notify the destination end of emptying the data configured in the destination end FPGA.

8. A memory data transmission method is characterized by comprising the following steps:

a destination terminal receives a source address sent by a source terminal, wherein the source address is a virtual machine memory virtual address of memory data to be transmitted in a source terminal virtual machine, and the source address is configured in a source terminal FPGA through a source terminal first drive;

the destination terminal converts the source address into a destination address through a destination terminal first driver and configures the destination address to a destination terminal FPGA, wherein the destination address is a virtual machine memory virtual address of the memory data to be transmitted in a destination terminal virtual machine;

and the destination terminal directly copies the memory data from the source address to the destination address through the source terminal FPGA and the destination terminal FPGA.

9. The method of claim 8, further comprising:

the destination terminal also receives the data length of the memory data sent by the source terminal and/or a source terminal identifier for identifying the source terminal;

and the destination terminal applies for the memory space for the memory data according to the data length and verifies the source terminal according to the source terminal identification.

10. The method of claim 9, wherein the destination directly copying the memory data from the source address to the destination address through the source FPGA and the destination FPGA comprises:

the destination end monitors the data length of the copied data in the copying process; and sending a second notification message to the source end for notifying the source end to stop data copying under the condition that the data length of the copied data is monitored to exceed the data length of the memory data to be transmitted, which is sent by the source end.

11. The method of claim 8, wherein the destination directly copying the memory data from the source address to the destination address through the source FPGA and the destination FPGA comprises:

the destination end receives compressed data sent by the source end, wherein the compressed data is obtained by compressing the memory data copied from the source address through the source end FPGA;

and the destination terminal decompresses the compressed data through the destination terminal FPGA and stores the decompressed data into the destination address.

12. A memory data transmission method is characterized by comprising the following steps:

the source end sends the source address to a destination end;

the destination terminal converts the source address into a destination address through a destination terminal first driver, and configures the destination address to a destination terminal FPGA, wherein the destination address is a virtual machine memory virtual address of the memory data to be transmitted in a destination terminal virtual machine;

and the source end initiates data copying to the destination end, and directly copies the memory data from the source address to the destination address through the source end FPGA and the destination end FPGA.

13. The method of claim 12, further comprising:

the source end further sends the data length of the memory data and/or a source end identifier for identifying the source end to the destination end;

14. The method of claim 12, wherein the source initiates a data copy to the destination, and directly copying the memory data from the source address to the destination address through the source FPGA and the destination FPGA comprises:

the source end compresses the memory data copied from the source address through the source end FPGA to obtain compressed data;

and the destination end FPGA decompresses the compressed data and stores the decompressed data into the destination address.

15. The method of any of claims 12 to 14, wherein the data path between the source FPGA and the destination FPGA comprises at least one of:

an ethernet channel.

16. The method of claim 15, wherein, in the case that a data channel between the source FPGA and the destination FPGA is an ethernet channel, the source directly copying the memory data from the source address to the destination address comprises:

the source end drives the source end FPGA through a second driver of the source end to fill the memory data into a source end buffer area from the source address, takes out the memory data from the source end buffer area, and sends the memory data to a destination end buffer area through a network card of the Ethernet;

and the destination end drives the destination end FPGA to take out the memory data from the destination end buffer area through a destination end second drive, and stores the taken out memory data into the destination address.

17. The method of claim 16, wherein the source buffer and the destination buffer are fifo queues, and wherein the size of each empty memory space in the fifo queue is determined according to the maximum transmission unit of the ethernet.

18. The method of claim 15, wherein after the source peer initiates a data copy to the destination peer and directly copies the memory data from the source address to the destination address through the source peer FPGA and the destination peer FPGA, the method further comprises:

the source end empties the data configured in the source end FPGA and sends a first notification message to the destination end;

and the destination terminal clears the data configured in the destination terminal FPGA according to the first notification message.

19. The method of claim 15, wherein the source initiates a data copy to the destination, and directly copying the memory data from the source address to the destination address through the source FPGA and the destination FPGA comprises:

the destination end monitors the data length of the copied data in the copying process; sending a second notification message to the source end when the data length of the copied data is monitored to exceed the data length of the memory data to be transmitted, which is sent by the source end;

and the source end stops data copying according to the second notification message.

20. A memory data transmission method is characterized by comprising the following steps:

a source end FPGA receives a source address configured by a first driver of a source end, wherein the source address is a virtual machine memory virtual address of memory data to be transmitted in a source end virtual machine;

under the condition that the destination address of the memory data to be transmitted in the destination virtual machine is configured to the destination FPGA, the source FPGA communicates with the destination FPGA to directly copy the memory data from the source address to the destination address, wherein the destination address is the virtual machine memory virtual address of the memory data to be transmitted in the destination virtual machine.

21. The method of claim 20, wherein the source FPGA communicates with the destination FPGA and directly copying the memory data from the source address to the destination address comprises:

and the source end FPGA compresses the memory data copied from the source address to obtain compressed data, and the compressed data is decompressed by the destination end FPGA and stored into the destination address.

22. The method of claim 20 or 21, wherein in a case where a data channel between the source FPGA and the destination FPGA is an ethernet channel, the source FPGA and the destination FPGA communicate, and directly copying the memory data from the source address to the destination address comprises:

the source end FPGA fills the memory data into a source end buffer area from the source address based on a drive of a source end second drive;

the source end FPGA takes out the memory data from the source end buffer area, sends the memory data to a destination end buffer area through an Ethernet network card, and is used for the destination end FPGA to take out the memory data from the destination end buffer area based on the drive of a second drive of the destination end and store the taken out memory data into the destination address.

23. A memory data transmission method is characterized by comprising the following steps:

the method comprises the steps that a destination end FPGA receives a destination address configured by a destination end first driver, wherein the destination address is a virtual machine memory virtual address of memory data to be transmitted in a destination end virtual machine, the destination address is obtained by converting a source address, the source address is a virtual machine memory virtual address of the memory data to be transmitted in a source end virtual machine, and the source address is configured in a source end FPGA through a source end first driver;

and the destination FPGA communicates with the source FPGA and directly copies the memory data from the source address to the destination address.

24. The method of claim 23, wherein in a case that a data channel between the source FPGA and the destination FPGA is an ethernet channel, the destination FPGA communicates with the source FPGA to directly copy the memory data from the source address to the destination address, comprising:

the destination terminal FPGA receives memory data which is taken out from a source terminal buffer area and sent by a network card of the Ethernet and stores the memory data into the destination terminal buffer area, wherein the memory data is filled into the source terminal buffer area from the source address through a drive of a source terminal second drive;

and the destination end FPGA takes out the memory data from a destination end buffer area through a drive of a destination end second drive and stores the taken out memory data into the destination address.

25. A source-side server, comprising:

the configuration module is used for configuring a source address to the source end FPGA through a source end first driver, wherein the source address is a virtual machine memory virtual address of memory data to be transmitted in a source end virtual machine;

the sending module is used for sending the source address to a destination, and is used for the destination to determine a destination address of the memory data to be transmitted in a destination virtual machine through a destination first driver and configure the destination address to a destination FPGA, wherein the destination address is a virtual machine memory virtual address of the memory data to be transmitted in the destination virtual machine;

and the first copying module is used for directly copying the memory data from the source address to the destination address through the source end FPGA and the destination end FPGA.

26. A destination server, comprising:

the first receiving module is used for receiving a source address sent by a source end, wherein the source address is a virtual machine memory virtual address of memory data to be transmitted in a source end virtual machine, and the source address is configured in a source end FPGA through a source end first driver;

the conversion module is used for converting the source address into a destination address through a destination first driver and configuring the destination address to a destination FPGA (field programmable gate array), wherein the destination address is a virtual machine memory virtual address of the memory data to be transmitted in a destination virtual machine;

and the second copying module is used for directly copying the memory data from the source address to the destination address through the source end FPGA and the destination end FPGA.

27. A memory data transfer system, comprising: a source end and a destination end, wherein the source end is provided with a source end FPGA, the destination end is provided with a destination end FPGA,

the source end is used for configuring a source address to a source end FPGA through a first driver of the source end and sending the source address to the destination end, wherein the source address is a virtual machine memory virtual address of memory data to be transmitted in a source end virtual machine;

the destination is used for converting the source address into a destination address through a first driver of the destination and configuring the destination address to the destination FPGA, wherein the destination address is a virtual machine memory virtual address of the memory data to be transmitted in a virtual machine of the destination;

the source end is further configured to initiate data copying to the destination end, and directly copy the memory data from the source address to the destination address through the source end FPGA and the destination end FPGA.

28. A memory data transfer apparatus, comprising:

the second receiving module is used for the source end FPGA to receive a source address configured by a first driver of the source end, wherein the source address is a virtual machine memory virtual address of memory data to be transmitted in a source end virtual machine;

and the third copying module is configured to, under the condition that a destination address of the memory data to be transmitted in the destination virtual machine is configured to the destination FPGA, communicate with the destination FPGA, and directly copy the memory data from the source address to the destination address, where the destination address is a virtual machine memory virtual address of the memory data to be transmitted in the destination virtual machine.

29. A memory data transfer apparatus, comprising:

a third receiving module, configured to receive, by a destination FPGA, a destination address configured by a destination first driver, where the destination address is a virtual machine memory virtual address of memory data to be transmitted in a destination virtual machine, the destination address is obtained by converting a source address, the source address is a virtual machine memory virtual address of the memory data to be transmitted in a source virtual machine, and the source address is configured in a source FPGA through the source first driver;

and the fourth copying module is used for the destination FPGA to communicate with the source FPGA and directly copying the memory data from the source address to the destination address.

30. A storage medium, comprising a stored program, wherein when the program runs, a device in which the storage medium is located is controlled to execute the memory data transmission method according to any one of claims 1 to 24.