CN112394557B

CN112394557B - Display panel and display device

Info

Publication number: CN112394557B
Application number: CN202011430517.6A
Authority: CN
Inventors: 李东华; 魏晓丽
Original assignee: Xiamen Tianma Microelectronics Co Ltd
Current assignee: Xiamen Tianma Microelectronics Co Ltd
Priority date: 2020-12-07
Filing date: 2020-12-07
Publication date: 2022-07-01
Anticipated expiration: 2040-12-07
Also published as: CN112394557A

Abstract

The invention provides a display panel and a display device, wherein the display panel comprises a plurality of sub-pixel units, each sub-pixel unit comprises a grid electrode, a drain electrode and a pixel electrode, an adjusting capacitor is arranged between the drain electrode and/or the pixel electrode and the corresponding grid electrode, the sub-pixel units in the same row comprise a first sub-pixel unit and a second sub-pixel unit, a sub-pixel charging signal provided by the second sub-pixel unit has signal closing time, and the adjusting capacitor of the first sub-pixel unit is larger than the adjusting capacitor of the second sub-pixel unit. The invention can make the voltage difference between the pixel voltage and the common voltage obtained by the sub-pixel units in the display panel close to be consistent, thereby avoiding the phenomenon of obvious uneven flicker of the display panel.

Description

Display panel and display device

Technical Field

The present invention relates to the field of display technologies, and in particular, to a display panel and a display device.

Background

In order to avoid the polarization phenomenon of liquid crystal under the drive of the same polarity voltage, the liquid crystal display screen usually adopts alternating current drive during application, namely, the liquid crystal display screen needs two polarities of positive and negative to drive the liquid crystal between each frame, and when the voltage difference applied to the liquid crystal by the two polarities is inconsistent, the difference of the brightness of the transmitted light between the two frames can cause flicker. A common liquid crystal panel has a common electrode, a pixel electrode and a liquid crystal layer, when a voltage is applied to the common electrode and the pixel electrode, a voltage difference is generated between the common electrode and the pixel electrode to change a transmittance of the liquid crystal layer, and a light transmittance of the liquid crystal layer is related to a magnitude of the voltage difference between the common electrode and the pixel electrode. If the applied positive and negative pixel voltages are not the same, or the voltage difference between the common voltage and the positive pixel voltage is not the same as the voltage difference between the common voltage and the negative pixel voltage, the brightness of the display panel is different under the two polarities, so that the display panel can generate a flicker phenomenon.

Common different pixel units in the display panel cause inconsistency of common voltages required to be set among the different pixel units due to differences of charging time sequences, parasitic capacitances, opening areas and the like, but the common voltages cannot be set one by one in the display panel, namely, only one common voltage value is set in the display panel, so that inconsistency of positive and negative frame voltage differences occurs in partial pixel units, and uneven flicker occurs in the display panel.

Disclosure of Invention

In view of the above, embodiments of the present invention provide a display panel and a display device.

The display panel provided by the embodiment of the invention comprises an array substrate, wherein the array substrate comprises a glass substrate, a plurality of scanning lines and a plurality of data lines are arranged on the glass substrate, the plurality of scanning lines and the plurality of data lines are crossed to define a plurality of sub-pixel units, the plurality of sub-pixel units are arranged along a first direction to form sub-pixel rows, the plurality of sub-pixel rows are arranged along a second direction, the first direction is the extension direction of the scanning lines, and the first direction is crossed with the second direction;

the sub-pixel unit comprises a thin film transistor, the thin film transistor comprises a grid electrode, a source electrode and a drain electrode, the source electrode and the drain electrode are positioned on one side of the grid electrode, which is far away from the glass substrate, the source electrode and the drain electrode are positioned on the same layer, the grid electrode is electrically connected with the scanning line, and the source electrode is electrically connected with the data line;

the sub-pixel unit further comprises a pixel electrode which is electrically connected with the drain electrode;

the drain electrode and/or the pixel electrode and the corresponding scanning line have adjusting capacitance;

the scanning line is electrically connected with a shift register circuit, the data line is electrically connected with a multiplexing circuit, and after the shift register circuit provides a scanning signal for any one sub-pixel row, the multiplexing circuit provides a sub-pixel charging signal for each sub-pixel unit of the same sub-pixel row;

in the same sub-pixel line, a first sub-pixel unit and a second sub-pixel unit are included, the first sub-pixel unit is the sub-pixel unit which is provided with the sub-pixel charging signal in the nth line at last, the first sub-pixel unit is not turned off after being turned on by the sub-pixel charging signal provided by the first sub-pixel unit, but is kept in an on state, when the scanning signal is obtained in the (N + 1) th line, the first sub-pixel unit continues to provide the charging signal for the second sub-pixel unit which needs to be charged, and then is turned off, and N is a positive integer greater than 0; the second sub-pixel unit further comprises the sub-pixel unit provided with the sub-pixel charging signal and having a signal-on time and a signal-off time simultaneously;

the adjusting capacitance of the first sub-pixel unit is larger than that of the second sub-pixel unit.

The display device provided by the embodiment of the invention comprises the display panel.

The same sub-pixel row comprises a first sub-pixel unit and a second sub-pixel unit, wherein the charging signal provided to the second sub-pixel unit has signal off time, the charging signal provided to the first sub-pixel unit does not have signal off time, namely the charging signal provided to the first sub-pixel unit is not turned off before the next sub-pixel needs to provide the charging signal, and the charging signal provided to the second sub-pixel unit is turned off before the next sub-pixel provides the charging signal. Since the turn-off of the charging signal causes the coupling drop of the charging voltage provided to the sub-pixel unit, that is, the pixel voltage of the second sub-pixel unit, when the charging voltage is turned off, the pixel voltage of the first pixel is not changed on the sub-pixel unit provided with the charging signal without the turn-off time of the signal, that is, the first sub-pixel unit, because the provided charging voltage is maintained, and thus the charging voltage of the first sub-pixel unit and the charging voltage of the second sub-pixel unit in the same sub-pixel row are different, the display panel and the display device provided by the embodiment of the invention can cause the coupling drop of the pixel voltage of the sub-pixel unit due to the adjusting capacitor in the same sub-pixel row when the scanning signal is turned off, the first sub-pixel unit has larger adjustment capacitance, and the reduced coupling voltage of the first sub-pixel unit is also larger, so that the condition that the first sub-pixel unit does not have pixel voltage coupling reduction due to no charging signal closing time is overcome, and after consistent public voltage is provided in the display panel, the voltage difference between the pixel voltage of the sub-pixel unit and the public voltage is close to consistency, and the phenomenon that the display panel flickers unevenly is avoided.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings that are required in the description of the embodiments will be briefly introduced, the drawings described herein are provided to provide further understanding of the present invention and constitute a part of the present invention, and the exemplary embodiments and descriptions thereof of the present invention are provided for explaining the present invention and do not constitute a limitation of the present invention.

FIG. 1 is a top view of a display panel according to a prior art design;

FIG. 2 is a schematic diagram illustrating a conventional design for providing charging signals to color sub-pixel units;

fig. 3 is a top view of a display panel according to an embodiment of the invention;

FIG. 4 is a schematic diagram illustrating a charging signal provided to a color sub-pixel unit according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of the sub-pixel unit structure in the area of FIG. 3S;

FIG. 6 is a schematic cross-sectional view of FIG. 5 taken along section line A-A';

fig. 7 is a schematic diagram illustrating an nth row charged end pixel unit structure according to an embodiment of the present invention;

FIG. 8 is a graph of pixel voltages during positive frame display and negative frame display during pixel display;

fig. 9 is a schematic diagram of another nth row charged end pixel unit structure according to an embodiment of the present invention;

FIG. 10 is a schematic diagram illustrating a structure of an Nth row of charged end pixel cells according to an embodiment of the present invention;

fig. 11 is a schematic view of another nth row charged end pixel unit structure according to an embodiment of the present invention;

FIG. 12 is a schematic cross-sectional view of FIG. 11 taken along section line B-B';

FIG. 13 is a schematic diagram illustrating a structure of an Nth row of charged end pixel cells according to an embodiment of the present invention;

fig. 14 is a schematic view of another nth row charged end pixel unit structure according to an embodiment of the present invention;

FIG. 15 is a schematic diagram illustrating a structure of an Nth row of charged end pixel cells according to an embodiment of the present invention;

fig. 16 is a schematic view of another nth row charged end pixel unit structure according to an embodiment of the present invention.

Detailed Description

The embodiments of the present invention will be described more fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the invention are shown. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

As shown in fig. 1, fig. 1 is a top view of a display panel provided by a conventional design, where a conventional display panel 1 includes an array substrate 10, the array substrate 10 includes a plurality of scan lines 11 and a plurality of data lines 12, the plurality of scan lines 11 and the plurality of data lines 12 intersect to define a plurality of sub-pixel units 13, the plurality of sub-pixel units 13 are arranged along a first direction to form sub-pixel rows 14, the plurality of sub-pixel rows are arranged along a second direction, the first direction is a direction in which the scan lines 11 extend, and the first direction intersects the second direction;

the array substrate 10 further includes a shift register circuit 15 and a multiplexer circuit 16, the scan line 11 is electrically connected to the shift register circuit 15, the data line 12 is electrically connected to the multiplexer circuit 16, the shift register circuit 15 includes a plurality of cascaded scan driving units, the driving chips bound to the display panel provide a longitudinal Clock signal ckv (vertical Clock signal) to the shift register circuit 15, each stage of the scan driving units of the shift register circuit 15 provides a scan signal to the corresponding scan line 11 step by step, after receiving the scan signal on one row of the scan line 11, the driving chips bound to the display panel provide a transverse Clock signal ckh (horizontal Clock signal) to the multiplexer circuit 16, and the multiplexer circuit 16 provides a sub-pixel charging signal to the sub-pixel unit 13 through the data line 12, thereby controlling the on-off state of each sub-pixel unit.

As shown in fig. 2, fig. 2 is a schematic diagram illustrating a conventional design for providing charging signals to color sub-pixel units; assuming that the display panel 1 has N +1 rows of sub-pixel rows 14, N is a positive integer greater than 0, when the scan signals are provided on the scan lines 11 of N rows or N +1 rows, the charging signals provided to the sub-pixel cells (P1, P2, P3) of different colors in the N rows and N +1 rows of sub-pixel rows are identical, i.e. the charging signal provided to each sub-pixel cell has a signal on time T1 and a signal off time T2, where the signal on time T1 and the signal off time T2 refer to delay times, the T1 time refers to the time from the signal source providing a signal to the transmission circuit having a signal, the T2 time refers to the time from the signal source stopping providing a signal to the transmission circuit having no signal, and if the signal is not on or off, there will naturally be no signal on time or signal off time, so that each sub-pixel cell needs to be charged by itself, the charge signal is turned on and turned off before the next sub-pixel cell needs to be charged. When the horizontal clock signal CKH is turned off, the charging voltage for the sub-pixels provided on the data line is decreased due to the coupling between the circuits, and the charging voltage for each sub-pixel unit is consistent, so that the voltages decreased by the coupling for each sub-pixel unit are consistent, thereby ensuring that the charging voltage obtained by each sub-pixel in the display panel is consistent.

However, the present inventor proposes a display panel, as shown in fig. 3 and fig. 4, fig. 3 is a top view of a display panel according to an embodiment of the present invention, and fig. 4 is a schematic diagram of providing a charging signal to a color sub-pixel unit according to an embodiment of the present invention; the display panel 2 provided by the embodiment of the invention comprises an array substrate 20, wherein the array substrate 20 comprises a plurality of scanning lines 21 and a plurality of data lines 22, the plurality of scanning lines 21 and the plurality of data lines 22 intersect to define a plurality of sub-pixel units 23, the plurality of sub-pixel units 23 are arranged along a first direction to form a sub-pixel row 24, the plurality of sub-pixel rows are arranged along a second direction, the first direction is the extending direction of the scanning lines 21, and the first direction intersects with the second direction;

the array substrate 20 further includes a shift register circuit 25 and a multiplexer circuit 26, the scan lines 21 are electrically connected to the shift register circuit 25, the data lines 22 are electrically connected to the multiplexer circuit 26, the shift register circuit 25 includes a plurality of cascaded scan driving units, the driving chips bound to the display panel provide longitudinal clock signals CKV to the shift register circuit 25, each stage of the scan driving units of the shift register circuit 25 provides scan signals to the corresponding scan lines 21 step by step, after receiving the scan signals on a row of the scan lines 21, the driving chips bound to the display panel provide transverse clock signals CKH to the multiplexer circuit 26, and the multiplexer circuit 26 provides sub-pixel charging signals to the sub-pixel units 23 through the data lines 22, so as to control the on-off state of each sub-pixel unit.

With continued reference to fig. 4, assuming that the display panel 2 has N +1 rows of sub-pixel rows 24, where N is a positive integer greater than 0, when the scan signals are provided on the scan lines 11 of N rows or N +1 rows, the charging signals provided to the sub-pixel cells (P1, P2, P3) of different colors in the N rows and the N +1 rows of sub-pixel rows are not identical, in fig. 4, the sub-pixel cell to which the charging signal is provided in the first sub-pixel row of the N row is P1, the charging signal provided to the sub-pixel cell of the P1 color does not have the signal on time T1, the sub-pixel cell to which the charging signal is provided in the last sub-pixel row of the N row is P3, the charging signal provided to the sub-pixel cell of the P3 color does not have the signal off time T2, the sub-pixel cell to which the charging signal is provided in the first sub-pixel row of the N +1 row is P3, the charging signal provided to the sub-pixel cell of the P3 does not have the signal on time T1, the last sub-pixel unit of the N +1 th sub-pixel row provided with the charging signal is P1, and the P1 color sub-pixel unit is provided with the charging signal without the signal off time T2; that is, the timing of the charging signals provided to the color sub-pixel units in the nth row is P1, P2, P3, but the timing of the charging signals provided to the color sub-pixel units in the (N + 1) th row is P3, P2, P1, because the last charging sub-pixel unit P3 in the nth row is not turned off after being turned on by the charging signal provided, but remains turned on, and when the (N + 1) th row obtains the scanning signal, it continues to provide the charging signal to the first sub-pixel unit P3 to be charged, and then turns off again, that is, the last sub-pixel unit in the nth row provided with the charging signal is consistent with the first charging signal pixel unit in the (N + 1) th row, so that the switching time of the horizontal clock signal CKH between adjacent sub-pixel rows can be reduced, the scanning speed is increased, and the load of the display panel is relatively reduced.

With continued reference to fig. 4, after the horizontal clock signal CKH is turned off, due to the coupling effect between the circuits, the charging voltage actually provided to the sub-pixel unit will have a slight drop, and the voltage of the slight change is the coupling change voltage Δ V1, so that the charging voltage provided to the sub-pixel unit P3 in the nth row will not have a coupling drop, i.e. the coupling change voltage Δ V1 is not generated, since the voltage for charging the sub-pixel unit P3 is not turned off, whereas the charging voltages provided to the other sub-pixel units in the nth row will generate the coupling change voltage Δ V1, which causes the charging voltage provided to the last charged sub-pixel unit P3 in the nth row and the other sub-pixel units in the nth row to be inconsistent, and similarly, the charging voltage provided to the last charged sub-pixel unit P1 in the nth +1 row and the charging voltage provided to the other sub-pixel units in the nth +1 row will also be different from each other sub-pixel unit P1 in the nth row If the voltages in the sub-pixel lines are inconsistent, when the same common voltage is input into the display panel, the voltage difference between the common voltage and the charging voltage is different due to the fact that different charging voltages exist in the same sub-pixel line, and the charging voltage comprises the charging voltage under a positive frame and the charging voltage under a negative frame, so that when the positive frame and the negative frame of the liquid crystal are switched, the voltage difference of the sub-pixel units in the same sub-pixel line cannot be consistent under the positive frame and the negative frame, and further, the phenomenon of uneven flicker can be generated.

As shown in fig. 5 and fig. 6, fig. 5 is a schematic view of the structure of the sub-pixel unit in the area of fig. 3S, and fig. 6 is a schematic view of the cross section of fig. 5 along the cross section line a-a'; in fig. 6, the source electrode 232 and the drain electrode 233 are located on the side of the gate electrode 231, which is away from the glass substrate 201, the source electrode 232 and the drain electrode 233 are located on the same layer, the gate electrode 231 is electrically connected with the scanning line 21, and the source electrode 232 is electrically connected with the data line 22; the sub-pixel unit 23 further includes a pixel electrode 27, and the pixel electrode 27 is electrically connected to the drain 233; since the drain electrode 233 is electrically connected to the corresponding gate electrode 231 and the adjustment capacitor Cpg is present between the scanning lines 21, and the pixel electrode 27 is electrically connected to the drain electrode 233, the adjustment capacitor Cpg is also present between the pixel electrode 27 and the corresponding scanning line 21.

As shown in fig. 7, fig. 7 is a schematic view of an nth row end-of-charge pixel unit structure according to an embodiment of the present invention; in fig. 7, the N-th row of end-of-charge pixel cells includes P1, P2, and P3 color sub-pixel cells, as described above, the P3 color sub-pixel in the N-th row of end-of-charge pixel cells is the sub-pixel cell to which the charging signal is finally supplied, the charging signal supplied to the P3 color sub-pixel has no off-time, the P3 color sub-pixel cell is the first sub-pixel cell D1, the charging signal supplied to the N-th row of other sub-pixel cells has off-time, the N-th row of other sub-pixel cells is the second sub-pixel cell D2, and the adjustment capacitance of the first sub-pixel cell D1 is greater than the adjustment capacitance of the second sub-pixel cell D2.

It should be noted that, the present invention does not provide that the sub-pixel unit to which the charging signal is finally provided in the nth row is the P3 color sub-pixel unit, and may be the P1 or P2 color sub-pixel unit, that is, the present invention does not provide the charging timing of the color sub-pixel unit in the nth row, and the charging timing may be P1, P2, P3, or any permutation and combination of the three. In the following embodiments, the sub-pixel unit of the nth row to which the charging signal is finally provided is set as the sub-pixel unit of the P3 color.

As shown in fig. 3, 5 and 8, fig. 8 is a graph of pixel voltages during positive frame display and negative frame display during pixel display; in the pixel display process, the shift register circuit 25 provides the scan signal S1 to the scan line 21, the multiplexer circuit 26 provides the charge signal S2 to the data line 22, when the scan signal S1 is turned off, due to the coupling effect of the adjusting capacitor Cpg between the drain 233 and the gate 231, and between the pixel electrode 27 and the gate 231, the charge voltage at the charge signal S3 actually obtained by the sub-pixel unit is lower than the charge voltage at the charge signal S2, and there is a difference between the charge voltages at the signal S2 and the signal S3, which is the feed-through voltage Δ V2; the larger the adjusting capacitor Cpg is, the larger the feedthrough voltage Δ V2 is, that is, the smaller the charging voltage actually obtained by the sub-pixel unit is, and then assuming that the common voltage Vcom in the display panel is a stable value, the voltage difference V1 between the charging voltage actually obtained by the sub-pixel unit under the positive frame and the common voltage Vcom, and the voltage difference V2 between the charging voltage actually obtained by the sub-pixel unit under the negative frame and the common voltage Vcom are, the larger the difference between the voltage differences V1 and V2 is, and the obvious flicker phenomenon occurs in the display panel under the positive and negative frames.

The display panel provided by the embodiment of the invention is provided with the same sub-pixel row, the adjusting capacitor Cpg of the first sub-pixel unit D1 is larger than the adjusting capacitor Cpg of the second sub-pixel unit D2, and the feedthrough voltage Δ V2 corresponding to the first sub-pixel unit D1 is also larger than the second sub-pixel unit D2, so that the Δ V2 corresponding to the first sub-pixel unit D1 is close to the Δ V2 and Δ V1 corresponding to the second sub-pixel unit D2 because the first sub-pixel unit D1 does not have the coupling change voltage Δ V1 and the second sub-pixel unit D2 has the coupling change voltage, so that the charging voltages obtained by the sub-pixel units in the same sub-pixel row can be consistent, the charging voltages include a positive frame and a negative frame, and the common voltage Vcom of the display panel is set to the central values of the positive frame and the negative frame obtained by the sub-pixels under the same stable common voltage provided by the display panel, thereby ensuring that the flicker phenomenon of the positive frame and the negative frame does not occur obviously, and the phenomenon of uneven flicker can not occur.

Alternatively, as shown in fig. 7, in any sub-pixel unit, taking the P1 color sub-pixel unit as an example in fig. 7, a vertical projection of the drain 233 of the sub-pixel unit on the array substrate has a geometric center C, a side of the vertical projection of the scan line 21 electrically connected to the gate 231 of the same sub-pixel unit on the array substrate, which is close to the drain 233, has a first edge E, and a distance between the geometric center C and the first edge E is a first adjustment distance H; the first adjustment distance H1 of the first sub-pixel cell D1 is set to be smaller than the first adjustment distance H2 of the second sub-pixel cell D2.

Because the grid electrode, the drain electrode and the pixel electrode in the sub-pixel unit are positioned on different metal layers, the drain electrode is electrically connected with the pixel electrode, and the grid electrode is not electrically connected with the drain electrode and the grid electrode, when the vertical projection of the drain electrode or the pixel electrode of the same sub-pixel unit and the scanning line electrically connected with the corresponding grid electrode are overlapped, the overlapped part forms a flat capacitor, and when the vertical projection of the drain electrode or the pixel electrode of the same sub-pixel unit and the scanning line electrically connected with the corresponding grid electrode are not overlapped, the metal layer of the drain electrode and the metal layer of the scanning line or the metal layer of the pixel electrode and the metal layer of the scanning line form an edge capacitor.

According to a calculation formula C of the capacitance, wherein epsilon is a dielectric constant of a medium between polar plates, S is an area of the polar plates, and d is a distance between the polar plates, the larger the area of an overlapped part is, the larger the capacitance is, and for a fringe capacitance, the smaller the shortest distance between vertical projections of two opposite metal layers on the same plane is, the larger the fringe capacitance is; that is, the first adjustment distance H1 of the first sub-pixel unit D1 is set to be smaller than the first adjustment distance H2 of the second sub-pixel unit D2, that is, the adjustment capacitor Cpg of the first sub-pixel unit D1 is set to be larger than the adjustment capacitor Cpg of the second sub-pixel unit D2, so that the feed-through voltage Δ V2 corresponding to the first sub-pixel unit D1 is close to the feed-through voltage Δ V2 and the coupling variation voltage Δ V1 corresponding to the second sub-pixel unit D2, and therefore, the charging voltages obtained by the sub-pixel units in the same sub-pixel row can be consistent, and the phenomenon of uneven flicker of the display panel is avoided.

Optionally, as shown in fig. 9, fig. 9 is a schematic view of another nth row charging end pixel unit structure according to an embodiment of the present invention; in fig. 9, the vertical projection of the scan line 21 electrically connecting the drain 233 of the first sub-pixel unit D1 with the corresponding gate 231 on the array substrate is overlapped, and the vertical projection of the scan line 21 electrically connecting the drain 233 of the second sub-pixel unit D2 with the corresponding gate 231 on the array substrate is non-overlapped.

That is to say, the capacitance formed between the drain 233 of the first sub-pixel unit D1 and the scan line 21 is a plate capacitance, and the capacitance formed between the drain 233 of the second sub-pixel unit D2 and the scan line 21 is a fringe capacitance, so that the capacitance value of the plate capacitance is larger than that of the fringe capacitance compared with the fringe capacitance, that is, the adjusting capacitance Cpg of the first sub-pixel unit D1 is larger than the adjusting capacitance Cpg of the second sub-pixel unit D2, so that the feed-through voltage Δ V2 corresponding to the first sub-pixel unit D1 is close to the feed-through voltage Δ V2 and the coupling change voltage Δ V1 corresponding to the second sub-pixel unit D2, and therefore, in the same sub-pixel row, the charging voltages obtained by the sub-pixel units can be consistent, and the phenomenon of flicker unevenness of the display panel is avoided.

It should be noted that, optionally, the drain 233 of the first sub-pixel unit D1 and the drain 233 of the second sub-pixel unit D2 may overlap with the vertical projection of the scan line 21 electrically connected to the corresponding gate 231 on the array substrate, and the overlapping area corresponding to the first sub-pixel unit D1 is larger than the overlapping area corresponding to the second sub-pixel unit D2, so that the adjustment capacitance Cpg of the first sub-pixel unit D1 may also be larger than the adjustment capacitance Cpg of the second sub-pixel unit D2. The first adjustment distance H may be adjusted according to actual design requirements, and may also be adjusted according to a difference between charging voltages obtained by the first sub-pixel unit D1 and the second sub-pixel unit D2.

Optionally, as shown in fig. 10, fig. 10 is a schematic diagram of a structure of a pixel unit at the charge end of the nth row according to an embodiment of the present invention; in fig. 10, the first adjustment distance H1 of the first sub-pixel unit D1 and the first adjustment distance H2 of the second sub-pixel unit D2 are identical, but the size of the vertical projection of the drain 233 of the first sub-pixel unit D1 on the array substrate is larger than the size of the vertical projection of the drain 233 of the second sub-pixel unit D2 on the array substrate.

The shortest distance between the drain 233 of the first sub-pixel unit D1 and the vertical projection of the corresponding scan line 21 on the array substrate is h1, the shortest distance between the drain 233 of the second sub-pixel unit D2 and the vertical projection of the corresponding scan line 21 on the array substrate is h2, the size of the vertical projection of the drain 233 of the first sub-pixel unit D1 on the array substrate is larger than the size of the vertical projection of the drain 233 of the second sub-pixel unit D2 on the array substrate, h1 can be smaller than h2, that is, the edge of the drain 233 corresponding to the first sub-pixel unit D1 is closer to the scan line 21, so that the adjusting capacitor Cpg of the first sub-pixel unit D1 can be larger than the adjusting capacitor Cpg of the second sub-pixel unit D2, and the voltage V2 corresponding to the first sub-pixel unit D1 and the voltage V2 and the coupling voltage V1 corresponding to the second sub-pixel unit D2 are closer to the scan line 21, therefore, in the same sub-pixel line, the charging voltage obtained by the sub-pixel units can be consistent, and the phenomenon of uneven flicker of the display panel is avoided.

Alternatively, as shown in fig. 11 and 12, fig. 11 is a schematic diagram of a structure of a charge end pixel unit in an nth row according to an embodiment of the present invention, and fig. 12 is a schematic diagram of a cross section of fig. 11 along a cross-sectional line B-B'; the first sub-pixel unit D1 includes a metal layer 28, the drain of the first sub-pixel unit D1 is a first drain 2331, the first sub-pixel unit has a first sub-pixel unit width L1 along a first direction, a shortest distance L2 is between a vertical projection of the metal layer 28 on the array substrate and a vertical projection of the first drain 2331 on the array substrate, the shortest distance L2 is less than or equal to a width L1 of the first sub-pixel unit, and the metal layer 28 extends along the first direction.

In the range of the first sub-pixel unit D1, the metal layer 28 is disposed, so that the metal layer 28 and the metal layer where the gate 231 of the first sub-pixel unit is located form a capacitor C1, the metal layer where the metal layer 28 and the first drain 2331 are located or the metal layer where the pixel electrode 27 of the first sub-pixel unit is located form a capacitor C2, and the capacitors C1 and C2 are superimposed on the adjusting capacitor Cpg of the first sub-pixel unit D1, which is equivalent to increasing the adjusting capacitor Cpg of the first sub-pixel unit, so that the adjusting capacitor Cpg of the first sub-pixel unit D1 is larger than the adjusting capacitor Cpg of the second sub-pixel unit D2; the metal layer 28 extends along the first direction, so that the area of the metal layer covering the light-transmitting area of the first sub-pixel unit D1 can be reduced as much as possible, and the black matrix on the color filter substrate opposite to the array substrate can completely cover the metal layer 28, thereby not affecting the brightness of the first sub-pixel unit D1. It should be noted that, in fig. 12, the metal layer 28 is disposed between the metal layers of the gate 231 and the first drain 2331 of the first sub-pixel unit D1, but the invention is not limited to the position of the metal layer 28 between the film layers, and the metal layer 28 may be disposed between any film layers of the array substrate.

Optionally, as shown in fig. 13, fig. 13 is a schematic structural diagram of another nth row charging end pixel unit according to an embodiment of the present invention; the metal layer 28 and the first drain electrode 2331 in the area of the first sub-pixel cell D1 at least partially overlap in vertical projection on the array substrate, and the data line adjacent to the first drain electrode 2331 has two data lines, one is the data line 221 electrically connected to the source electrode of the first sub-pixel cell, and the other is the data line 222 electrically connected to the source electrode of the sub-pixel cell adjacent to the first sub-pixel cell, so that the metal layer 28 at least partially overlaps with the data line 221 and/or the data line 222 in vertical projection on the array substrate, which can greatly increase the capacitance C2 formed by the metal layer on which the metal layer 28 and the drain electrode 2331 of the first sub-pixel cell are located or the metal layer on which the pixel electrode 27 is located, and the capacitance C2 is superposed on the tuning capacitance Cpg of the first sub-pixel cell D1, thereby greatly increasing the tuning capacitance Cpg corresponding to the first sub-pixel cell D1, so that the tuning capacitance Cpg of the first sub-pixel cell D1 is greater than the tuning capacitance Cpg of the second sub-pixel cell D2, the feed-through voltage Δ V2 corresponding to the first sub-pixel unit D1, the feed-through voltage Δ V2 corresponding to the second sub-pixel unit D2 and the coupling change voltage Δ V1 are close to each other, so that the charging voltages obtained by the sub-pixel units in the same sub-pixel row can be consistent, and the phenomenon of uneven flicker of the display panel is avoided.

It should be noted that there may be an overlap between the metal layer 28 and the gate 231 of the first sub-pixel unit D1 in the vertical projection of the array substrate, so that the capacitance C1 formed by the metal layer where the metal layer 28 and the gate 231 of the first sub-pixel unit are located may be increased, and the capacitance C1 is superimposed on the adjusting capacitance Cpg of the first sub-pixel unit D1, thereby greatly increasing the adjusting capacitance Cpg corresponding to the first sub-pixel unit D1.

Optionally, as shown in fig. 14, fig. 14 is a schematic structural diagram of a pixel unit at the charge end of the nth row according to an embodiment of the present invention; the sub-pixel unit further includes a light-shielding layer 29, the light-shielding layer 29 is located between the gate 231 and the glass substrate 201, and the light-shielding layer 29 in the first sub-pixel unit D1 can be the metal layer, so that the design can avoid additional increase of the process for preparing the metal layer, and only the dimension of the light-shielding layer along the first direction needs to be increased properly, and no process condition needs to be changed, and the light-shielding layer 29 of the first sub-pixel unit D1 and the metal layer where the gate 231 of the first sub-pixel unit is located form a capacitor C1, and the capacitor C2 formed by the metal layer where the first drain 2331 is located and the metal layer where the pixel electrode 27 of the first sub-pixel unit D1, and the capacitors C1 and C2 are overlapped on the adjustment capacitor Cpg of the first sub-pixel unit D1, which is equivalent to increasing the adjustment capacitor Cpg of the first sub-pixel unit, so that the adjustment capacitor Cpg of the first sub-pixel unit D1 is larger than the adjustment capacitor Cpg of the second sub-pixel unit D2, the feed-through voltage Δ V2 corresponding to the first sub-pixel unit D1, the feed-through voltage Δ V2 corresponding to the second sub-pixel unit D2 and the coupling change voltage Δ V1 are close to each other, so that the charging voltages obtained by the sub-pixel units in the same sub-pixel row can be consistent, and the phenomenon of uneven flicker of the display panel is avoided.

Alternatively, as shown in fig. 15, fig. 15 is a schematic structural diagram of another nth row charging end pixel unit according to an embodiment of the present invention; the scan line 21 electrically connected to the gate 231 of the first sub-pixel cell D1 has a first branch 211, the first branch 211 extends along the second direction, and the first branch 211 partially overlaps with the pixel electrode 27 of the first sub-pixel cell D1 in the vertical projection of the array substrate.

The first branch 211 and the pixel electrode 27 of the first sub-pixel unit D1 are overlapped in the vertical projection of the array substrate, which is equivalent to increasing the area of the first sub-pixel unit D1, and the overlapping area between the metal layer of the scan line 21 and the metal layer of the pixel electrode 27 is increased, so that the adjusting capacitance Cpg between the two is increased, that is, the adjusting capacitance Cpg of the first sub-pixel unit is increased, so that the adjusting capacitance Cpg of the first sub-pixel unit D1 is larger than the adjusting capacitance Cpg of the second sub-pixel unit D2, and the first branch 211 is arranged on the scan line 21 in the area of the first sub-pixel unit D1, so that the process for preparing the metal layer is not required to be additionally increased, only the pattern of the scan line needs to be changed, the process condition does not need to be changed, and the cost is saved.

Alternatively, as shown in fig. 16, fig. 16 is a schematic diagram of a structure of a pixel unit at the charge end of the nth row according to an embodiment of the present invention; the pixel electrode of the first sub-pixel unit D1 has a second branch 271, the second branch 271 extends along the second direction, and the vertical projection of the second branch 271 and the scan line 21 electrically connected to the gate 231 of the first sub-pixel unit D1 on the array substrate partially overlaps.

The scan line 21 electrically connected to the gate 231 of the first sub-pixel unit D1 and the second branch 271 are disposed to overlap the vertical projection of the array substrate, which also increases the area of the first sub-pixel unit D1, and the overlapping area between the metal layer of the scan line 21 and the metal layer of the pixel electrode 27 increases the adjustment capacitance Cpg therebetween, that is, increases the adjustment capacitance Cpg of the first sub-pixel unit, so that the adjustment capacitance Cpg of the first sub-pixel unit D1 is larger than the adjustment capacitance Cpg of the second sub-pixel unit D2, and in the area of the first sub-pixel unit D1, the second branch 271 is disposed on the pixel electrode 21, and the process for preparing the metal layer is not required to be additionally added, and only the pattern of the pixel electrode needs to be changed, and the process condition does not need to be changed, thereby saving the cost.

The sub-pixel unit of the display panel provided by the embodiment of the invention at least comprises a first color sub-pixel, a second color sub-pixel and a third color sub-pixel, wherein the first color sub-pixel is a red sub-pixel R, the second color sub-pixel is a green sub-pixel G, the third color sub-pixel is a blue sub-pixel B, the charging time sequence of the odd-numbered sub-pixel can be RGB, and the charging time sequence of the even-numbered sub-pixel is BGR, the invention does not limit the charging time sequence of the odd-numbered sub-pixel to be RGB, and can be any arrangement combination of three kinds of sub-pixels of RGB, such as RBG, GBR and the like, as long as the charging time sequence of the even-numbered sub-pixel to the three color sub-pixels is arranged to satisfy that the color sub-pixel provided with the first time sequence is the color sub-pixel provided with the third time sequence on the odd-numbered line, and the color sub-pixel provided with the third time sequence on the even-numbered line is the color sub-pixel provided with the first time sequence, if the charging timing of the odd row sub-pixel is RBG, the charging timing of the even row sub-pixel is GBR.

The invention also does not limit the odd-numbered line and the even-numbered line of the display panel to respectively follow the same sub-pixel charging time sequence, and the display panel is assumed to comprise N +2 lines of sub-pixel lines, wherein N is a positive integer greater than 0, as long as the color sub-pixel satisfying the requirement that the N +1 line is provided with the first time sequence is the color sub-pixel provided with the third time sequence on the nth line, for example, the N lines of sub-pixel charging time sequence is RGB, the N +1 line of sub-pixel charging time sequence can be BGR or BRG, and if the N +1 line of sub-pixel charging time sequence is BGR, the N +2 line of sub-pixel charging time sequence can be RGB or RBG, and so on, and the description is omitted here.

The embodiment of the invention also provides a display device, the display device comprises a display terminal product such as a smart phone, a flat panel display device, a notebook computer display device and the like, the display device comprises the display panel, and the beneficial effects of the display device are also the beneficial effects described in the above embodiment, which are not repeated herein.

The foregoing description shows and describes several preferred embodiments of the present application, but as aforementioned, it is to be understood that the application is not limited to the forms disclosed herein, but is not to be construed as excluding other embodiments and is capable of use in various other combinations, modifications, and environments and is capable of changes within the scope of the inventive concept as expressed herein, commensurate with the above teachings, or the skill or knowledge of the relevant art. And that modifications and variations may be effected by those skilled in the art without departing from the spirit and scope of the application, which is to be protected by the claims appended hereto.

Claims

1. A display panel is characterized by comprising an array substrate;

the array substrate comprises a glass substrate, wherein a plurality of scanning lines and a plurality of data lines are arranged on the glass substrate, the plurality of scanning lines and the plurality of data lines are crossed to define a plurality of sub-pixel units, the plurality of sub-pixel units are arranged along a first direction to form sub-pixel rows, the plurality of sub-pixel rows are arranged along a second direction, the first direction is the extending direction of the scanning lines, and the first direction is crossed with the second direction;

2. The display panel according to claim 1, wherein a vertical projection of the drain of any one of the sub-pixel units on the array substrate has a geometric center, a side of a vertical projection of a scan line electrically connected to the gate of the same sub-pixel unit on the array substrate, which is close to the drain of the same sub-pixel unit, has a first edge, and a distance between the geometric center and the first edge is a first adjustment distance;

the first adjusting distance of the first sub-pixel unit is smaller than the first adjusting distance of the second sub-pixel unit.

3. The display panel according to claim 2, wherein the drain of the first sub-pixel unit overlaps with a vertical projection of the corresponding scan line on the array substrate, and the drain of the second sub-pixel unit does not overlap with a vertical projection of the corresponding scan line on the array substrate.

4. The display panel according to claim 1, wherein a vertical projection of the drain of any one of the sub-pixel units on the array substrate has a geometric center, a side of a vertical projection of the scan line electrically connected to the gate of the same sub-pixel unit on the array substrate, which is close to the drain of the same sub-pixel unit, has a first edge, a distance between the geometric center and the first edge is a first adjustment distance, and the first adjustment distances of the sub-pixels are equal in the same sub-pixel row;

the size of the vertical projection of the drain electrode of the first sub-pixel unit on the array substrate is larger than that of the vertical projection of the drain electrode of the second sub-pixel unit on the array substrate.

5. The display panel according to claim 1, wherein the first sub-pixel unit comprises a metal layer, the drain of the first sub-pixel unit is a first drain, the width of the first sub-pixel unit along the first direction is a first sub-pixel unit width, a shortest distance between a vertical projection of the metal layer on the array substrate and a vertical projection of the first drain on the array substrate is less than or equal to the first sub-pixel unit width, and the metal layer extends along the first direction.

6. The display panel according to claim 5, wherein a vertical projection of the metal layer on the array substrate overlaps a vertical projection of the first drain electrode on the array substrate, and a vertical projection of the metal layer on the array substrate overlaps a vertical projection of the data line adjacent to the first drain electrode on the array substrate.

7. The display panel according to claim 6, wherein the array substrate includes a light-shielding layer between the gate electrode and the glass substrate, and the metal layer is the light-shielding layer.

8. The display panel according to claim 1, wherein the scan line electrically connected to the gate electrode of the first sub-pixel unit comprises a first branch extending along the second direction, and the first branch overlaps with a vertical projection portion of the pixel electrode of the first sub-pixel unit on the array substrate.

9. The display panel according to claim 1, wherein the pixel electrode of the first sub-pixel unit comprises a second branch, the second branch extends along the second direction, and the second branch overlaps with a vertical projection portion of the scan line electrically connected to the gate electrode of the first sub-pixel unit on the array substrate.

10. The display panel according to claim 1, wherein the sub-pixel units comprise at least a first color sub-pixel, a second color sub-pixel and a third color sub-pixel, and the first sub-pixel units of adjacent sub-pixel rows have different colors.

11. A display device comprising the display panel according to any one of claims 1 to 10.