CN112385186A

CN112385186A - Apparatus and method for ordering data packets

Info

Publication number: CN112385186A
Application number: CN201880095263.1A
Authority: CN
Inventors: 拉米·扎查里亚
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2018-07-03
Filing date: 2018-07-03
Publication date: 2021-02-19
Anticipated expiration: 2038-07-03
Also published as: WO2020007447A1; CN112385186B

Abstract

The present invention provides an apparatus and method for ordering packets, and in particular for reordering packets that arrive out of order. To this end, the apparatus includes a buffer to store received data packets and processing logic to control the buffer to store each received data packet at a different buffer location corresponding to a unique sequence number associated with the data packet. Further, the processing logic is to control the read pointer to point to a buffer location, then output a packet from the buffer location from the buffer, control the last write pointer to point to a buffer location of a received packet associated with a highest sequence number, and control the first gap pointer to point to a buffer location of a first received unordered packet. The processing logic is further to maintain a pre-counter that stores a number of empty buffer locations between the read pointer and the first gap pointer, and to maintain a post-counter that stores a number of received packets stored at a buffer location after the first gap pointer.

Description

Apparatus and method for ordering data packets

Technical Field

The present invention relates generally to communication systems and switching fabrics. In particular, the present invention relates to an apparatus and method for ordering received data packets, in particular reordering received out-of-order data packets. Thus, the apparatus and method can handle sporadic packet loss in a communication system.

Background

A communication system is composed of a plurality of switches (referred to as networks or fabrics) connected to each other so as to allow a plurality of nodes to communicate with each other. A node is any device capable of communicating using the network (i.e., computer, workstation, data storage device/array, or network interface). Generally, nodes are capable of transmitting and receiving data packets simultaneously. In the transmission of a given data packet, the node transmitting the data packet is hereinafter referred to as the transmitting or source node, and the node receiving the data packet is hereinafter referred to as the receiving or destination node.

The switch has a plurality of bidirectional ports. The ports of the switches are connected to other switches or to communication nodes. The entire network includes a plurality of switches and a plurality of nodes connected to each other through ports of the switches, as exemplarily illustrated in fig. 13.

Any connection set up between two nodes through the network is identified by unique information that is stored in each data packet (called a header) transmitted from the source to the destination (this information is commonly referred to as a 5-tuple when using TCP and ethernet protocols). Packets from the same source to the same destination are collectively referred to as a "flow". There may be multiple streams from the same source to the same destination. However, each stream is uniquely identified.

Arriving traffic from the input ports is directed to the output ports based on routing decisions made within the switch for each packet. Typically, the switch selects the same output port for a flow (i.e., all packets from a particular source are routed to a particular destination). This approach avoids the situation where packets arrive at the destination out of order. If packets are sent to a given flow through different output ports, the packets of the flow may arrive at the destination out of order (out of order) due to different path lengths within the network.

However, it is not efficient to send a given flow completely through a unique path in the network, as this can easily create congested areas in the network while leaving other areas underutilized. Accordingly, various techniques attempt to optimize the transmission of data packets through a network in order to minimize congestion on a particular path and reduce latency (i.e., transit time from a source to a destination). All techniques are intended to deliver packets of a given flow through different output ports of the switch.

However, these techniques may result in packets arriving at the destination out of order. Therefore, a reordering mechanism is required at the destination. Furthermore, the network may sometimes drop packets for various reasons, such as data corruption during packet delivery, decision making within switches due to congestion (insufficient storage area), etc. Thus, in order to take advantage of the described techniques, each destination needs to be able to reorder the arriving flows of packets for a given flow and deliver the packets in sequence to the actual end user, while also handling dropped packets in the network. Packet loss means that at least some packets will not reach their destination.

One conventional mechanism for reordering data packets requires each source to attach a Sequence Number (SN) to each communicated data packet. The SN of each packet is unique and is incremented each time a packet is sent. For example, when sending n packets, the SN of the 1 st packet is i, the SN of the 2 nd packet is i +1, the SN of the 3 rd packet is i +2, and so on, and the SN of the nth packet is i + n-1. The sequence of SNs must be unique between each source and destination. For example, if a particular source has two destinations, a and B respectively, then the source needs to maintain two different sequences, one for source a and the other for source B.

In this conventional mechanism for reordering data packets, the destination uses the SN received from a particular source in order to reorder the received data packets into their original sequence, i.e., into the sequence in which they left off from this source. When doing so, the destination must take into account that some packets may have been dropped by the network and will not be reached in the near future (note that high level protocols between the source and destination may identify the dropped packets and the destination may request retransmission of the lost packets).

A conventional reordering mechanism at the destination using the arrival SN of a data packet from a particular source is implemented by means of a buffer for storing the arrived data packet (or storing a pointer to the arriving data packet while storing the data packet in a general purpose memory). The buffer typically maintains the following two values:

read pointer (RdPtr), which is a pointer to read a packet already in sequence from a buffer.

Expected sequence number (ExpSN), where SN corresponds to the entry pointed to by RdPtr.

An example of this mechanism is shown in fig. 14. Each arriving packet is written to the buffer according to its SN relative to ExpSN, i.e., written to a buffer location equal to SN-ExpSN. This means that the data packet is written into a buffer location in the buffer corresponding to its sequence in the data packet stream, which is determined by the source based on the SN. When a packet is present in the location pointed to by RdPtr, the packet is treated as an ordered (sequential) packet and can be read from the buffer. When a packet is read out of the buffer, RdPtr is incremented by 1 and ExpSN is also incremented by 1.

Since the delay is different for each packet in the network, the maximum variance is defined as the maximum gap between multiple arriving out-of-order packets. If the maximum variance is defined as the number of packets when a packet with ExpSN is expected, then a packet with an SN higher than ExpSN + the maximum variance will not reach the destination. The maximum variance between multiple arriving packets determines the buffer size, since the maximum number of accumulated packets in the buffer must accommodate all packets arriving within the maximum variance.

The algorithm of the reordering mechanism described above is illustrated by the following pseudo-code (this pseudo-code does not take into account the initialization process so that the SN at the source matches the ExpSN at the destination):

at initialization (reset):

RdPtr＝0

ExpSN ═ 0// assuming all sources begin with SN ═ 0

When a packet arrives (with SN):

v/data packet arrives after RdPtr shift, or

// data packet arrives and exceeds the buffer size

If ((SN < ExpSN) or (SN > ExpSN + buffer size)

Immediately transfer the data packet out of the buffer

Otherwise

WriteAddress＝RdPtr+(SN-ExpSN)

Writing a packet at location WriteAddress in the buffer

In each clock cycle:

if (location at RdPtr with valid packet)

Transferring data packets out of a buffer

RdPtr++

When the network is unlikely to accidentally drop packets, thus ensuring that each transmitted packet reaches its destination, the latency of the packet to reach the RdPtr location is insignificant, since the packet will eventually arrive and be transferred out of the buffer. However, when the network may occasionally drop packets, the latency of the packets to the RdPtr location must be limited so as not to wait indefinitely long. Thus, the latency is typically limited to a value related to the maximum variance time. If a packet does not arrive during this waiting time, it is considered a packet loss and RdPtr is incremented to the next position.

If the latency is too long, buffer inflation can occur because no packets are being transmitted out of the buffer during that time. If the latency is too short, out of order packets will be passed out of the buffer because the packets at the RdPtr location can eventually arrive (not dropped) and pass out of the buffer.

Disclosure of Invention

When using the conventional reordering mechanism described above, and when the network occasionally drops one or more packets, it is desirable to identify gaps in the sequence of arrival of the packets at the destination and wait long enough for the packets to arrive, but not too long, because too long a wait results in buffer inflation.

The following methods are in principle feasible solutions:

1. a timer with the maximum allowed time is applied for each arriving packet (e.g., the maximum allowed latency may be the maximum variance of the network if it can be measured). When the timer expires, the corresponding packet and all previous packets are forwarded out of the buffer without waiting for a packet among them that has not yet arrived.

Disadvantageously, this method requires a timer for each packet, which is expensive in hardware. Furthermore, the number of packets that can be accumulated (and also the number of timers) depends on the maximum variance provided by the network.

2. One rudimentary approach is to apply a timer to packets that are to be placed in the RdPtr location (which means that packets arrive out of order when the buffer is not empty). By this method, each null RdPtr waits for a maximum timeout value. Disadvantageously, each packet must wait for a maximum timeout even if two packet pointers are skipped for arriving out-of-order packets. Thus, this approach is too conservative.

In view of the above-described problems and disadvantageous solutions, the present invention aims to improve the conventional reordering mechanism. It is an object of the invention to provide an apparatus and a method for ordering received data packets with increased efficiency. Thus, too much extra hardware resources are not needed to implement the solution, but the solution is not too conservative. In particular, the present invention aims to provide a mechanism that is able to accurately detect gaps between arriving data packets and track the fill level of the gaps. Furthermore, the present invention contemplates using one or more timers in a more efficient manner. I.e. it should be ensured that the waiting time is not too short nor too long.

The object of the invention is achieved by the solution presented in the appended independent claims. Advantageous embodiments of the invention are further defined in the dependent claims.

The assumption behind the present invention is that once a certain number of out-of-order packets arrive, all previous packets should arrive at the destination within the maximum variance time, except for the packets dropped in the network. One implementation idea of the invention is to use two counters. When a gap is detected in a sequence of arriving packets (i.e., arriving out-of-order packets), one counter counts the number of packets that arrive before a packet and create a gap (i.e., the SN of an arriving packet is less than the SN of a packet), and the other counter counts the number of packets that arrive after a packet and create a gap (i.e., the SN of an arriving packet is higher than the SN of this packet).

A first aspect of the invention provides an apparatus for ordering received data packets, the apparatus comprising: a buffer for storing the received data packets; and processing logic to: controlling the buffer to store each received data packet at a different buffer location corresponding to a unique SN associated with the data packet, controlling a read pointer to point to a buffer location from which data packets are then output from the buffer, controlling a last write pointer to point to a buffer location of the received data packet associated with a highest SN, controlling a first gap pointer to point to a buffer location of a first received unordered data packet, maintaining a front counter that stores a number of empty buffer locations between the read pointer and the first gap pointer, and maintaining a back counter that stores a number of received data packets stored at a buffer location after the first gap pointer.

Storing the data packets in the buffer comprises, inter alia, writing the entire data packet (data packet information) into the buffer, or writing a pointer to the data packet into the buffer, while writing the entire data packet (data packet information) into a general purpose memory, etc.

Controlling the last write pointer and the first gap pointer enables identifying gaps in the sequence of arriving data packets. However, not much additional hardware is required to implement these pointers. The maintenance of the back counter and the front counter, which are the two counters mentioned above, enables tracking of the fill level of gaps in the sequence of data packets. In summary, the apparatus of the first aspect implements a more efficient ordering or reordering mechanism than conventionally used apparatuses.

In an implementation form of the first aspect, the processing logic is further to: if the data packet is stored at the buffer location of the read pointer, the received data packet is output from the buffer.

In another implementation form of the first aspect, the processing logic is further to discard the received data packet with a SN corresponding to the buffer location before the read pointer or to output the received data packet bypassing the buffer.

The device is therefore well suited for networks where packets sometimes have to be dropped for some reason.

In another implementation form of the first aspect, the processing logic is further to: decrementing the previous counter if the received data packet is stored at an empty buffer location between the read pointer and the first gap pointer; and if the previous counter is decremented to 0, the first gap pointer is moved to the last write pointer or if the last write pointer is invalid, the previous counter is invalidated.

The pre-counter thus allows to track the filling of the gap between the read pointer and the first gap pointer, i.e. the filling of the first gap in the sequence of data packets. Once the gap is filled, the first gap pointer is moved to the last write pointer and the range between the previous position of the first gap pointer and the new position of the first gap pointer is considered as the next gap, which may have been filled with some packets (according to the post-counter).

In another implementation form of the first aspect, the processing logic is further to: if the pre-counter is decremented to 0 and if the last write pointer is valid, the pre-counter is set according to the post-counter and the post-counter is reset, otherwise the pre-counter remains 0.

Thus, the late counter serves as a pre-treatment for the next gap, and if the first gap is closed, the value of the late counter will be transferred to the early counter.

In another implementation form of the first aspect, the processing logic is further to decrement the post-counter if the received data packet is stored at an empty buffer location between the first gap pointer and the last write pointer.

Thus, the post counter tracks the filling of the next gap.

In another implementation form of the first aspect, the processing logic is further configured to start or restart the timer when controlling the first gap pointer to move to another buffer location or to change from invalid to valid.

The timer allows to reduce the latency in case a data packet is lost and never arrives, i.e. in case the gap may never be completely filled.

In another implementation form of the first aspect, the processing logic is further configured to limit the timer to a maximum time variance of receiving the data packet when starting the timer, wherein the maximum time variance is defined as a difference between a fastest arrival time of the data packet and a slowest arrival time of the data packet.

This provides the best compromise between latency and packet transmission efficiency.

In another implementation form of the first aspect, the processing logic is further configured to limit the timer to a maximum time variance of the received packet corrected based on the post-counter when the timer is restarted.

Since some packets have arrived and are tracked by the back counter, the timer duration can be reduced to optimize latency.

In another implementation form of the first aspect, the processing logic is further configured to set the buffer to a time-out state if the timer expires.

In the time-out state, the device is provided with some specific functionality with respect to handling various pointers and counters.

In another implementation form of the first aspect, the processing logic is further to: in a timeout state, a next non-empty buffer location is searched by moving the read pointer and skipping an empty buffer location, a data packet stored at the found non-empty buffer location is output, and the read pointer is further moved to a buffer location subsequent to the buffer location of the output data packet.

Therefore, the next packet can be output quickly, and thus latency is reduced.

In another implementation form of the first aspect, the processing logic is further to: in the timeout state, packets having SNs corresponding to skipped buffer locations are considered discarded and/or received packets having SNs corresponding to buffer locations preceding the read pointer are considered discarded.

Thus, the device is able to handle packet loss without inefficient latency.

In another implementation form of the first aspect, the processing logic is further to: in the time-out state, the arrival packets that are considered to have been dropped or the arrival packets are dropped are output bypassing the buffer.

Consequently, data packets arriving late are not lost, and the efficiency of the ordering mechanism implemented by means of the buffer is not affected.

In another implementation form of the first aspect, the processing logic is further to: in a timeout state, arriving packets with SNs corresponding to buffer locations after the current buffer location of the read pointer are stored into the buffer while the read pointer is moved to search for the next non-empty buffer location.

Therefore, even in the time-out state, if outputting the packet according to the read pointer is not hindered, the packet can be saved.

In another implementation form of the first aspect, the processing logic is further to: exit from the timeout state when the read pointer points to the same buffer location as the first gap pointer or when the buffer is empty.

In another implementation form of the first aspect, the processing logic is further to: when the read pointer points to the same buffer location as the first gap pointer and the buffer is not empty and the last write pointer is valid and the late counter is greater than 0, re-entering the timeout state and restarting the timer upon re-entering the timeout state.

In another implementation form of the first aspect, the processing logic is further to maintain an expected SN corresponding to a buffer location of the read pointer.

In another implementation form of the first aspect, the apparatus further comprises a parser to extract a SN associated with the received data packet and provide the extracted SN to the processing logic.

A second aspect of the invention provides a method for ordering received data packets, the method comprising: control a buffer to store each received data packet at a different buffer location corresponding to a unique sequence number, SN, associated with the data packet, control a read pointer to point to a buffer location from which data packets are then output from the buffer, control a last write pointer to point to a buffer location of the received data packet associated with a highest SN, control a first gap pointer to point to a buffer location of a first received unordered data packet, maintain a front counter that stores a number of empty buffer locations between the read pointer and the first gap pointer, and maintain a back counter that stores a number of received data packets stored at a buffer location after the first gap pointer.

In one implementation form of the second aspect, the method further comprises: if the data packet is stored at the buffer location of the read pointer, the received data packet is output from the buffer.

In another implementation form of the second aspect, the method further comprises: discarding the received packet having the SN corresponding to the buffer location preceding the read pointer or outputting the received packet bypassing the buffer.

In another implementation form of the second aspect, the method further comprises: decrementing the previous counter if the received data packet is stored at an empty buffer location between the read pointer and the first gap pointer; and if the previous counter is decreased to 0, moving the first gap pointer to the last write pointer; or if the last write pointer is invalid, the previous counter is invalidated.

In another implementation form of the second aspect, the method further comprises: if the leading counter is decremented to 0, and if the last write pointer is valid, the leading counter is set according to the trailing counter and then the trailing counter is reset, otherwise the leading counter remains 0.

In another implementation form of the second aspect, the method further comprises: if the received data packet is stored at an empty buffer location between the first gap pointer and the last write pointer, the post counter is decremented.

In another implementation form of the second aspect, the method further comprises: the timer is started or restarted when the first gap pointer is controlled to move to another buffer location or change from invalid to valid.

In another implementation form of the second aspect, the method further comprises: the timer is limited when started to a maximum time variance for receiving the data packet, wherein the maximum time variance is defined as the difference between the fastest arrival time of the data packet and the slowest arrival time of the data packet.

In another implementation form of the second aspect, the method further comprises: when restarting the timer, the timer is limited to the maximum time variance of the received packet corrected based on the post-counter.

In another implementation form of the second aspect, the method further comprises: the buffer is set to a time-out state in case the timer expires.

In another implementation form of the second aspect, the method further comprises: in a timeout state, a next non-empty buffer location is searched by moving the read pointer and skipping an empty buffer location, a data packet stored at the found non-empty buffer location is output, and the read pointer is further moved to a buffer location subsequent to the buffer location of the output data packet.

In another implementation form of the second aspect, the method further comprises: in the timeout state, packets having SNs corresponding to skipped buffer locations are considered discarded and/or received packets having SNs corresponding to buffer locations preceding the read pointer are considered discarded.

In another implementation form of the second aspect, the method further comprises: in the time-out state, the arrival packets that are considered discarded are output bypassing the buffer or discarded.

In another implementation form of the second aspect, the method further comprises: in a timeout state, arriving packets with SNs corresponding to buffer locations after the current buffer location of the read pointer are stored into the buffer while the read pointer is moved to search for the next non-empty buffer location.

In another implementation form of the second aspect, the method further comprises: exit from the timeout state when the read pointer points to the same buffer location as the first gap pointer or when the buffer is empty.

In another implementation form of the second aspect, the method further comprises: when the read pointer points to the same buffer location as the first gap pointer and the buffer is not empty and the last write pointer is valid and the late counter is greater than 0, re-entering the timeout state and restarting the timer upon re-entering the timeout state.

In another implementation form of the second aspect, the method further comprises: an expected SN corresponding to the buffer location of the read pointer is maintained.

In another implementation form of the second aspect, the method further comprises: the SN associated with the received data packet is extracted and the extracted SN is provided to processing logic.

The method of the second aspect and its implementation form achieve all the advantages and effects described above for the device of the first aspect and its corresponding implementation form.

It has to be noted that all devices, elements, units and means described in the present application may be implemented in software or hardware elements or any kind of combination thereof. All steps performed by the various entities described in the present application and the functions described to be performed by the various entities are intended to indicate that the respective entities are adapted or used to perform the respective steps and functions. Although in the following description of specific embodiments specific functions or steps performed by external entities are not reflected in the description of specific elements of said entities performing said specific steps or functions, it should be clear to a skilled person that these methods and functions may be implemented in corresponding hardware or software elements or any combination thereof.

Drawings

The foregoing aspects and many of the attendant aspects of this invention will become more readily appreciated as the same become better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:

fig. 1 shows an apparatus according to an embodiment of the invention.

Fig. 2 shows an apparatus according to an embodiment of the invention.

FIG. 3 illustrates an example reordering with locked SNs and timers.

Fig. 4 shows that the counter/pointer is set for the enqueue cases 1-4 in the normal state.

Fig. 5 shows setting the counter/pointer for the enqueue case 5-6 in the normal state.

Fig. 6 shows that the counter/pointer is set for the enqueue case 7-8 in the normal state.

Fig. 7 shows the setting of the counter/pointer for the enqueue cases 9-12 in the normal state.

Fig. 8 shows the setting of the counter/pointer for the dequeue case 1-5 in the normal state.

Fig. 9 shows setting the counter/pointer for enqueue cases 1-4 in a timeout state.

Fig. 10 shows setting the counters/pointers for the dequeue cases 1-4 in the timeout state.

Fig. 11 shows setting the counter/pointer for the dequeue case 5-7 in the timeout state.

FIG. 12 illustrates a method according to an embodiment of the invention.

Fig. 13 shows an example of a communication system composed of switches and nodes.

FIG. 14 illustrates an example of a reordering technique.

Detailed Description

Fig. 1 shows an apparatus 100 for ordering received data packets 101, in particular for reordering (re-ordering) data packets 101 that arrive out of order. The apparatus 100 comprises: a buffer 102 for storing arriving (i.e., received) packets 101; and processing logic 103 for controlling the buffer 102, and controlling the pointers and maintaining the counters, as described below.

In particular, processing logic 103 is to control buffer 102 to store each received data packet 101 at a different buffer location 104 corresponding to a unique SN associated with data packet 101. Each arriving packet 101 has a unique SN, i.e., a different SN. In addition, each buffer location 104 is associated with a determined SN. Thus, processing logic 103 may control buffer 102 to sequentially store arriving packets according to their respective SNs.

Furthermore, processing logic 103 is configured to control read pointer 105 to point to buffer location 104, and then output packet 101 from buffer 102 from buffer location 104. That is, the read pointer 105 is a pointer for reading those data packets 101 already in sequence from the buffer 102.

Further, processing logic 103 is to control last write pointer 106 to point to buffer location 104 of received data packet 101 associated with the highest SN. The last write pointer 106 stores in particular the SN (or buffer location 104) of the received data packet 101 having the highest SN so far, irrespective of whether the data packet has been written into the buffer 102. The last write pointer 106 may carry a valid indication of whether its contents are valid.

Further, the processing logic 103 is to control the first gap pointer 107 to point to the buffer location 104 of the first received out-of-order packet 101. The first gap pointer 107 stores the SN of the first out-of-order packet 101 arriving at the buffer 102 (or buffer location 104) until all previous packets arrive. Next, if there is a gap between the previous value of the first gap pointer 107 and the current last write pointer value, the first gap pointer 107 may store the pointer of the last write pointer 106, i.e. move the first gap pointer 107 to the last write pointer. In addition, the first gap pointer 107 may carry a valid indication of whether its contents are valid.

Further, processing logic 103 is to maintain a pre-counter 108 that stores the number of empty buffer locations 104 between read pointer 105 and first gap pointer 107. Whenever the number changes, for example when a new data packet 101 is received, the processing logic 103 is arranged to update the stored number in accordance with the new data packet 101 received. Thus, the pre-counter 108 stores the number of missing packets before the first gap pointer 107, i.e. the number of all packets from the read pointer 105 to the first gap pointer 107. When a packet arrives with a SN before the first gap pointer 107, the previous counter 108 is decremented since there are now 1 missing packets 101.

Further, processing logic 103 is to maintain a back counter 109 that stores the number of received packets 101 stored at buffer location 104 after first gap pointer 107. Whenever the number changes, for example when a new data packet 101 is received, the processing logic 103 is arranged to update the stored number in dependence of the most recently received data packet 101. Thus, the post counter 109 stores the number of arriving packets 101 (i.e., all packets 101 from the first gap pointer 107 to the write pointer 106) from the first gap pointer 107 to the last write pointer 106.

Fig. 2 shows an apparatus 100 according to an embodiment of the invention, which is based on the apparatus 100 shown in fig. 1. Like elements in fig. 1 and 2 are labeled with like reference numerals and function identically. Fig. 2 particularly shows a high-level block diagram for implementing the device 100. Similar to fig. 1, fig. 2 shows a packet buffer 102, processing logic 103, and received and output packets 101.

However, in contrast to fig. 1, fig. 2 also shows a parser 200 of the device 100, said parser 200 being arranged to extract a SN associated with the received data packet 101 and to provide the extracted SN to the processing logic 103. Thus, arriving packet 101 first passes through parser 200, causing the SN associated with packet 101 to be extracted. The extracted SN is then forwarded to processing logic 103, which, as described above, is used to manage

pointers

105, 106 and 107 and counters 108 and 109, respectively, based on the arriving SNs. Processing logic 103 may determine whether an incoming packet 101 is to be written to packet buffer 102 or output bypassing the buffer directly. This can be done by controlling the write ('Wr') and 'bypass' indications. And processing logic 103 is to manage the reading from the packet buffer 102 based on the read pointer 105 (state) and potentially additionally based on the flow control from the next block of the output ordered stream of received packets 101.

Hereinafter, the operation of the apparatus 100 as shown in fig. 1 or fig. 2 will be described in more detail. The main steps that the device 100 is capable of performing are:

the SN of the first out-of-order arrival packet 101 is locked. This means that the arrival of a data packet 101 is too early and therefore one or more data packets 101 that have not yet arrived are present before this data packet.

When the SN is locked, the first gap pointer 107 is set to point to the buffer location 104 corresponding to the locked SN, i.e., it can change from invalid to valid. The timer starts counting for the duration of the maximum variance. In particular, the processing logic 103 is configured to start or restart the timer when controlling the first gap pointer 107 to change from invalid to valid, or when controlling the first gap pointer 107 to move to another buffer location 104.

Declare a timeout for the buffer 102 if not all packets 101 before the locked SN have arrived within the maximum variance time, i.e. when the timer expires before all packets 101 are received. In other words, the buffer 102 enters a timeout state.

If all data packets 101 before the locked SN arrive within the maximum variance time, i.e. before the timer expires, the lock of the SN is released and the first gap pointer 107 is controlled to point to the SN of the then earliest arriving data packet. To monitor the earliest arriving packet 101, the last write pointer 106 is always used to store the maximum arriving SN. Thus, that is, the first gap pointer 107 moves to the last write pointer 106.

During the time of the first lock of the SN (by verifying and setting the first gap pointer 107) to the time of release of the lock (and the first gap pointer 107 moving or failing), there may be multiple arriving data packets 101, some with SNs less than the locked SN and some with SNs higher than the locked SN. When the locked SN is released, the timer restarts from that SN to the maximum variance of all packets 101 until the then earliest arriving SN. This essentially covers any gaps in the sequence of arriving packets 101 with a single counter. Thus, to track the gap between arriving out-of-order packets 101 and determine if and when to apply the timer, the last write pointer 106, first gap pointer 107, front counter 108, and back counter 109 described above are controlled and maintained.

Fig. 3 shows an example of the above. Fig. 3 shows in particular the following:

1. the data packets 1-4 arrive in sequence, i.e. so far there is no gap. Thus, the first gap pointer 107 is (so far) invalid. The last write pointer 106 points to the packet 101 with SN 4 because it is now the highest SN of the arrived packet 101.

2. Packet 7 arrives, forming a gap of two buffer locations 104 (two missing packets 101 in the sequence). Thus, the pre-counter 108 is set to 2 (and indicates the number of remaining packets for filling the gap) and the first gap pointer 107 is set to 7. From now on, the post counter 109 counts the number of arriving packets 101 after the first gap pointer 107. The last write pointer 106 is set to 7 because this is the highest SN currently received.

3.

Packets

5 and 6 arrive to fill the gap. However, during this time,

packets

13, 14, 18 arrive, creating two new gaps. The last write pointer 106 is set to 18 because this is the highest SN that is now reached. At this point, the first gap pointer 107 is set to 18, the front counter 108 (up to 0) is set to the value of the back counter 109, i.e. according to the back counter 109 (indicating 6 missing packets), and the back counter 109 is set to 0.

4. The gap is filled by the missing data packet 101 and since there are no more gaps and the first gap pointer 107 is disabled, the last write pointer 106 remains 18 since no further data packets 101 arrive.

During the counting time and waiting for the arrival of the data packet 101 before the first gap pointer 107, the data packet 101 may also arrive after the first gap pointer 106. Therefore, when shifting the first gap pointer 107 to the last write pointer 106, it is preferable to no longer set the timer to the maximum variance, since the data packet 101 has arrived after the first gap pointer 107. The maximum variance should be calculated from the arrival time of the data packet. To compensate for this time, the following operations may be performed:

the arrival time of the last write pointer 106 is always locked.

1. When the first gap pointer 107 is shifted to the last write pointer 106.

a. The back counter 109 is set according to the front counter 108 and the back counter 108 is reset.

i. The number of missing packets 101 that fill the first gap pointer 107 is known.

b. Set timer-timeout time- (current time-last write pointer 106 arrival time).

i. If the result of the calculation is negative, it is set to zero or a minimum value.

2. The back counter 109 and the front counter 108 continue to be counted.

a. If the previous counter 109 reaches the required number of packets 101.

i. Stop timer

Go to step 1

b. If the timer expires before the pre-counter 108 is reached, a timeout is declared.

In general, the timer is limited to the maximum time variance of the received packet 101 corrected based on the post-counter 109.

More details about the setting counters 108 and 109 and the

pointers

105, 106 and 107 are described below. Thus, the process of writing arriving packets 101 to the buffer 102 is referred to as "enqueuing". The process of reading and passing the sequential data packets 101 from the buffer 102 is referred to as "dequeuing". With these definitions, most of the changes to

counters

108, 109 and

pointers

105 and 107 occur during the arrival of the enqueue phase of packet 101.

Typical values for the pointers 105 and 107 (and the valid indication of the pointer) and counters 108, 109 after system initialization (reset) are as follows:

1. first slot pointer 107 ═ NA (null)

2. The first gap pointer is valid as 0

3. Last write pointer 106 NA (invalid)

4. Last write pointer valid 0

5. Pre-counter 108 equals 0

6. The rear counter 109 is 0

Figures 4 to 11 show graphically all cases to be considered when setting the pointers 105 and counters 108, 109 for enqueue or dequeue and when the buffer 102 is not in a time-out state or when the buffer is in a time-out state.

FIG. 4 shows enqueue cases 1-4 when the buffer 102 is not in a timeout state. The starting point is an empty buffer 102 or a buffer 102 that is not empty but does not have any gaps. Case 1 shows that the data packets 101 arrive in sequence and the last write pointer 106 is set to the buffer location 104 where the data packet 101 is stored. This buffer location 104 corresponds to the read pointer 105 so that the data packet 101 will be output next. Case 2 shows that the out-of-order packet 101 arrives and the last write pointer 106 and the first gap pointer 107 are set to the buffer location 104 where the packet 101 is stored. The front counter 108 is set to the difference from the read pointer 105, i.e., to 4. Case 3 shows that the last write pointer 106 has been set, at which point the data packets 101 arrive in sequence and have SN corresponding to the buffer location 104 after the last write pointer 107 moved accordingly. There is no gap. Case 4 shows that the last write pointer 106 has been set and that the data packet 101 arrives out of order and has a buffer position 104SN corresponding to after the last write pointer 107 moved accordingly. As the gap is formed, a first gap pointer 107, a front counter 108, and a rear counter are provided.

Fig. 5 shows enqueue cases 5-6 for arriving packet 101 having SNs corresponding to buffer location 104 before first gap pointer 107 (case 5) and after first gap pointer 107 (case 6) when buffer 102 is not in a timeout state, where first gap pointer 107 is now equal to last write pointer 106. In case 5, the front counter 108 is decremented by 1 and the rear counter 109 (held) is 0. In case 6, the last write pointer 106 moves according to the SN of the arrival data 101, and the post counter increments by 1.

Fig. 6 shows enqueue cases 7-8 for arriving packets 101 having SNs corresponding to buffer locations 104 before the first gap pointer 107 (case 7) and after the first gap pointer 107 (case 8) when the buffer 102 is not in a timeout state, when the first gap pointer 107 is not equal to the last write pointer 106. In case 7, the front counter 108 is decremented by 1, and in case 8, the rear counter is incremented by 1.

Fig. 7 shows enqueue cases 9-11 for arriving packets 101 that fill a gap (the previous counter reaches 0) at the buffer location 104 before the first gap pointer 107 when the buffer 102 is not in a time-out state. In case 9, the first gap pointer 107 is at the last write pointer 106. After enqueuing, there are no more gaps, causing the first gap pointer 107 to be invalidated. In case 10, there is still another gap such that the first gap pointer 107 moves to the last write pointer 106. In case 11, the first gap pointer 107 is different from the last write pointer 106. After enqueuing, there are no more gaps, causing the first gap pointer 107 to be invalidated. Fig. 7 further shows the case 12 for an arriving packet 101 filling a gap at a buffer position 104 after the first gap pointer 107. In this case, when the post counter is incremented by 1, the first gap pointer 107 is not moved.

Fig. 8 shows dequeue cases 1-5 when the buffer 102 is not in the time-out state, i.e., shows dequeue cases in the normal state of the buffer 102. The values of the back counter 109 and the front counter 108 are not changed by the dequeue stage. Case 1 shows data packet 101 stored at buffer location 104 of read pointer 105. Thus, the data packet 101 is output and the read pointer 105 is moved to the next buffer location 104. Case 2 shows the same case, but in case 1 the first gap pointer 107 and the last write pointer 106 point to different buffer locations 104, whereas in case 2 they point to the same buffer location 104. Case 3 shows the reading of the first packet 101 of a plurality of sequential packets 101 (without gaps). Case 4 shows a read of the data packet 101 at the last write pointer 106, i.e. a read of the last stored data packet 101. In case 5, the first gap pointer 107 also points to the buffer location 104 of the read pointer 105 before dequeuing.

When the buffer 102 is in the time-out state, the value of the first gap pointer 107 is locked and does not change until the time-out state ends. The enqueue phase can only terminate the time-out state when all data packets 101 having a SN corresponding to the buffer location 104 before the first gap pointer 107 arrive. The dequeue phase can only terminate the timeout state when the read pointer 105 is equal to or greater than the first gap pointer 107. It is noted that during dequeuing, the read pointer 105 may be skipped when searching for the next valid data packet 101 in the buffer 102.

FIG. 9 shows enqueue cases 1-4 when buffer 102 is in a timeout state. In case 1, a data packet 101 is received with an SN associated with the buffer location 104 after the read pointer 105 and the data packet 101 is stored into the buffer 101. The pre-counter 108 reaches 0 and the first gap pointer 107 is disabled. The buffer 102 exits the timeout state. In case 2, the buffer 102 also exits the time-out state for the original value of the first gap pointer 107, since the first gap is filled by the arriving packet 101, but re-enters the time-out state for the new value of the first gap pointer 107 moved to the last write pointer 106. Case 3 is similar to case 1, but the first gap pointer 107 is not at the last write pointer 106 before dequeuing. In case 4, a data packet 101 arrives with a SN after the read pointer 105 and also after the first gap pointer 107. Therefore, the post counter 109 is incremented, but remains in a timeout state.

FIG. 10 shows the dequeue cases 1-4 when the buffer 102 is in a timeout state. It should be noted that normal state dequeuing applies to the time-out state dequeuing case if read pointer 105 is not skipped. In case 1, the read pointer 105 is skipped over at the empty buffer location 104 until the data packet 101 to be output is found. Subsequently, the read pointer 105 is moved to the next buffer location 104 after the output data packet 101. Case 2 is similar to case 1, but the first gap pointer 107 shifts to the last write pointer 106 after outputting the data packet 101, because there is a gap in the sequence (indicated by the value of the post counter 109), and a new timeout begins. In case 3, since there is no gap between the first gap pointer 107 and the last write pointer 106, the first gap pointer 107 is disabled, and the timeout state is terminated after the data packet 101 is output. In case 4, the read pointer 105 jumps to the packet 101 at the buffer location 104 of the last write pointer 106, the packet 101 is output and the timeout state terminates.

FIG. 11 shows the dequeue cases 5-7 when the buffer 102 is in a timeout state. In case 5, the buffer location 104 is skipped before the next packet 101 can be output. The first gap pointer 107 and the last write pointer 106 are set to different buffer locations 104. In case 6, the read pointer 105 is located at location 104 of packet 101, which can be output without skipping buffer location 104. In case 7, the last sequential packet 101 is output. Then, the first gap pointer 107 is moved to the last write pointer 106, the front counter 108 is set according to the rear counter 109, and the rear counter 109 is reset to 0.

FIG. 12 illustrates a method 1200 according to an embodiment of the invention. The method 1200 may be performed by the apparatus 100 shown, for example, in fig. 1 or fig. 2. Method 1200 includes step 1201: the buffers are controlled to store each received data packet 101 at a different buffer location 104 corresponding to a unique SN associated with the data packet 101. Further, the method comprises step 1202: controls the read pointer 105 to point to the buffer location 104 and then outputs the data packet 101 from the buffer 102 from the buffer location 104. The method 1200 further includes step 1203: controls the last write pointer 106 to point to the buffer location 105 of the received packet 101 associated with the highest SN; and a step 1204: the first gap pointer 107 is controlled to point to the buffer location 104 of the first received out-of-order packet 101. The method 1200 further includes a step 1205: maintaining a pre-counter 108 of the number of empty buffer locations 104 stored between the read pointer 105 and the first gap pointer 107, and step 1206: a post counter 109 is maintained that stores the number of received data packets 101 stored at the buffer location 104 after the first gap pointer 107.

The invention has been described in connection with various embodiments and implementations as examples. Other variations will be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims. In the claims and in the description, the term "comprising" does not exclude other elements or steps, and "a" or "an" does not exclude a plurality. A single element or other unit may fulfill the functions of several entities or items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

1. An apparatus (100) for ordering received data packets (101), characterized in that the apparatus (100) comprises

A buffer (102), said buffer (102) being adapted to store said received data packet (101), an

Processing logic (103) for

-controlling the buffer (102) to store each received data packet (101) in a different buffer location (104) corresponding to a unique sequence number, SN, associated with the data packet (101),

-controlling a read pointer (105) to point to a buffer location (104), followed by outputting a data packet (101) from said buffer location (104) from said buffer (102),

-controlling a last write pointer (106) to point to a buffer location (104) of the received data packet (101) associated with the highest SN,

-controlling a first gap pointer (107) to point to a buffer location (104) of a first received out-of-order packet (101),

-maintaining a pre-counter (108), the pre-counter (108) storing the number of empty buffer positions (104) between the read pointer (105) and the first gap pointer (107), and

-maintaining a back counter (109), the back counter (109) storing the number of received data packets (101) stored at a buffer location (104) after the first gap pointer (107).

2. The apparatus (100) of claim 1, wherein the apparatus is a rotary drum

The processing logic (103) is further to

-outputting the received data packet (101) from the buffer (102) if the data packet (101) is stored at the buffer location (104) of the read pointer (105).

3. The apparatus (100) of claim 1 or 2,

the processing logic (103) is further to

-discarding a received data packet (101) having a SN corresponding to a buffer location (104) preceding the read pointer (105) or outputting the received data packet (101) bypassing the buffer (102).

4. The apparatus (100) according to any one of claims 1 to 3,

the processing logic (103) is further to

-decrementing the pre-counter (108) if the received data packet (101) is stored at an empty buffer position (104) between the read pointer (105) and the first gap pointer (107),

-moving the first gap pointer (107) to the last write pointer (106) if the pre-counter (108) decreases to 0, or deactivating the pre-counter (108) if the last write pointer (106) is invalid.

5. The apparatus (100) of claim 4,

the processing logic (103) is further to

-if the front counter (108) is decremented to 0 and if the last write pointer (106) is valid, setting the front counter (108) according to the back counter (109) and subsequently resetting the back counter (109), otherwise the front counter (108) remains 0.

6. The apparatus (100) according to any one of claims 1 to 5,

the processing logic (103) is further to

-decrementing the post counter (109) if the received data packet (101) is stored at an empty buffer location (104) between the first gap pointer (107) and the last write pointer (106).

7. The apparatus (100) according to any one of claims 1 to 6,

the processing logic (103) is further to

-starting or restarting a timer when controlling the first gap pointer (107) to move to another buffer location (104) or to change from invalid to valid.

8. The apparatus (100) of claim 7,

the processing logic (103) is further configured to, upon starting the timer,

-limiting the timer to a maximum time variance of the received data packet (101), wherein the maximum time variance is defined as the difference between the fastest arrival time of the data packet (101) and the slowest arrival time of the data packet (101).

9. The apparatus (100) of claim 7,

the processing logic (103) is further configured to, upon restarting the timer,

-limiting the timer to a maximum time variance of the received data packet (101) corrected based on the post-counter (109).

10. The apparatus (100) according to any one of claims 7 to 9,

the processing logic (103) is further to

-in case the timer expires, then setting the buffer (102) to a time-out state.

11. The apparatus (100) of claim 10,

the processing logic (103) is further configured to, in the timeout state,

-searching for a next non-empty buffer location (104) by moving the read pointer (105) and skipping an empty buffer location (104),

-outputting the data packet (101) stored at the found non-empty buffer location (104), and

-moving the read pointer (105) further to the buffer position (104) after the buffer position (104) of the output data packet (101).

12. The apparatus (100) of claim 11,

the processing logic (103) is further configured to, in the timeout state,

-considering data packets (101) having SNs corresponding to skipped buffer locations (104) as discarded, and/or

-considering a received data packet (101) having a SN corresponding to a buffer location (104) preceding the read pointer (105) as discarded.

13. The apparatus (100) of claim 12,

the processing logic (103) is further configured to, in the timeout state,

-outputting the arriving packet (101) considered as dropped or dropping the arriving packet (101) bypassing the buffer.

14. The apparatus (100) according to any one of claims 11 to 13,

the processing logic (103) is further configured to, in the timeout state,

-storing an arriving data packet (101) having a SN corresponding to a buffer location (104) after the current buffer location (104) of the read pointer (105) into the buffer (102) while moving the read pointer (105) to search for the next non-empty buffer location (104).

15. The apparatus (100) according to any one of claims 10 to 14,

the processing logic (102) is further to

-exit from the time-out state when the read pointer (105) points to the same buffer location (104) as the first gap pointer (107) or when the buffer (102) is empty.

16. The apparatus (100) of claim 15,

the processing logic (103) is further to

-re-entering the time-out state when the read pointer (105) points to the same buffer location (104) as the first gap pointer (107) and the buffer (102) is not empty and the last write pointer (106) is valid and the post counter (109) is above 0,

-restarting said timer when re-entering said time-out state.

17. The apparatus (100) according to any one of claims 1 to 16,

the processing logic (102) is further to maintain

-an expected SN corresponding to the buffer location (104) of the read pointer (105).

18. The apparatus (100) of any of claims 1 to 17, further comprising

A parser (200) for extracting a SN associated with a received data packet (101) and providing the extracted SN to the processing logic (103).

19. A method (1200) for ordering received data packets (101), the method (1200) comprising

-controlling (1201) a buffer (102) to store each received data packet (101) in a different buffer location (104) corresponding to a unique sequence number, SN, associated with the data packet (101),

-controlling (1202) a read pointer (105) to point to a buffer location (104) and then outputting a data packet (101) from the buffer location (104) from the buffer (102),

-controlling (1203) a last write pointer (106) to point to a buffer location (105) of the received data packet (101) associated with the highest SN,

-controlling (1204) a first gap pointer (107) to point to a buffer location (104) of a first received out-of-order packet (101),

-maintaining (1205) a pre-counter (108), the pre-counter (108) storing a number of empty buffer positions (104) between the read pointer (105) and the first gap pointer (107), and

-maintaining (1206) a back counter (109) storing the number of received data packets (101) stored at a buffer location (104) after the first gap pointer (107).