CN112383462A - Network device and bus configuration method - Google Patents
Network device and bus configuration method Download PDFInfo
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- CN112383462A CN112383462A CN202011270637.4A CN202011270637A CN112383462A CN 112383462 A CN112383462 A CN 112383462A CN 202011270637 A CN202011270637 A CN 202011270637A CN 112383462 A CN112383462 A CN 112383462A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40169—Flexible bus arrangements
- H04L12/40176—Flexible bus arrangements involving redundancy
- H04L12/40189—Flexible bus arrangements involving redundancy by using a plurality of bus systems
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
- H04L41/06—Management of faults, events, alarms or notifications
- H04L41/0654—Management of faults, events, alarms or notifications using network fault recovery
- H04L41/0663—Performing the actions predefined by failover planning, e.g. switching to standby network elements
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Abstract
The embodiment of the application provides a network device and a bus configuration method, wherein the network device comprises at least one control core and a plurality of data cores, the control core comprises a first controller and a second controller, the data cores comprise a third controller and a fourth controller, the first controller and the third controller are connected through a first serial bus, and the second controller and the fourth controller are connected through a second serial bus; the first controller is used for sending a first read-write signal to the third controller through the first serial bus; the third controller is used for processing the first read-write signal; a second controller for transmitting a second read/write signal to the fourth controller through the second serial bus when the failure of the first serial bus is detected; and a fourth controller for processing the second read-write signal. By applying the technical scheme provided by the embodiment of the application, the number of the connecting lines of the bus is reduced, and the reliability of the bus system is improved.
Description
Technical Field
The present application relates to the field of network communication technologies, and in particular, to a network device and a bus configuration method.
Background
A bus is an important component of a network device for connecting a control core and a data core in the network device. And connecting the control core and the data core by adopting a point-to-point configuration mode. This causes a problem that a plurality of buses exist in the network device, the number of wires is large, and wiring is difficult.
In order to solve the above problems, the related art adopts a serial bus to connect the control core and the data core. Although the method can reduce the number of connecting wires and reduce occupied wiring resources, when the control core and the data core are connected by the method, if a certain control core or data core fails, the bus is likely to be hung up, and the reliability of a bus system formed by the control core and the data core is poor.
Disclosure of Invention
An object of the embodiments of the present application is to provide a network device and a bus matching method, so as to reduce the number of bus lines and improve the reliability of a bus system. The specific technical scheme is as follows:
in a first aspect, an embodiment of the present application provides a network device, where the network device includes at least one control core and multiple data cores, where the control core includes a first controller and a second controller, and the data cores include a third controller and a fourth controller, where the first controller and the third controller are connected by a first serial bus, and the second controller and the fourth controller are connected by a second serial bus;
the first controller is configured to send a first read/write signal to the third controller through the first serial bus; the third controller is used for processing the first read-write signal;
the second controller is used for sending a second read-write signal to the fourth controller through the second serial bus when the first serial bus fault is detected; the fourth controller is configured to process the second read-write signal.
In a second aspect, an embodiment of the present application provides a bus configuration method, which is applied to a network device, where the network device includes at least one control core and multiple data cores, the control core includes a first controller and a second controller, the data cores include a third controller and a fourth controller, the first controller and the third controller are connected through a first serial bus, and the second controller and the fourth controller are connected through a second serial bus; the method comprises the following steps:
the first controller sends a first read-write signal to the third controller through the first serial bus;
the third controller processes the first read-write signal;
the second controller sends a second read-write signal to the fourth controller through the second serial bus when detecting the first serial bus fault;
the fourth controller processes the second read-write signal.
In a third aspect, embodiments of the present application provide a machine-readable storage medium storing a machine-executable program executable by a processor, the processor being caused by the machine-executable program to: implementing any of the method steps described above.
In the technical scheme provided by the embodiment of the application, the control core and the data core are connected through the serial bus, so that the number of connecting wires of the bus is reduced. In addition, the two controllers are respectively arranged on the control core and the data core, the control core and the data core are connected through the two serial buses through the controllers, and the control core and the data core can communicate through the other serial bus under the condition that one serial bus fails, so that the reliability of a bus system is improved.
Of course, it is not necessary for any product or method of the present application to achieve all of the above-described advantages at the same time.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic diagram of a framework of a network device provided in the related art;
fig. 2 is a schematic diagram of another framework of a network device provided in the related art;
fig. 3 is a schematic diagram of a framework of a network device according to an embodiment of the present application;
fig. 4 is a schematic flowchart of a bus configuration method according to an embodiment of the present application;
fig. 5a is a schematic diagram of another framework of a network device according to an embodiment of the present application;
FIG. 5b is a schematic diagram illustrating normal operation of the bus of the network device shown in FIG. 5 a;
fig. 5c is an operational schematic diagram of a bus fault of the network device shown in fig. 5 a.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the embodiment of the present application, the control core may serve as a MASTER device (MASTER), and the data core may serve as a SLAVE device (SLAVE).
In the related art, a framework of a network device is shown in fig. 1, and includes a control core 11 and a plurality of data cores 12. The control core 11 and the data cores 12 are connected in a point-to-point configuration manner, that is, the control core 11 and each data core 12 are connected separately, which causes the problem that a plurality of buses exist in the network device, the number of the connected wires is large, and the wiring is difficult. In particular, the network device may include a plurality of control cores 11, which may result in a multiplied number of buses present in the network device, further increasing the degree of wiring difficulty.
In order to solve the above problem, another network device is provided in the related art, and as shown in fig. 2, the network device includes a control core 21 and a plurality of data cores 22. The control core and the data core are connected through a serial bus. In this network device, although the number of wires is reduced and the occupied wiring resources are reduced, the reliability of the bus system constituted by the control core and the data core is poor. If one of the control core 21 or the data core 22 fails, it is likely to cause the bus to hang up.
In order to reduce the number of connection lines of a bus in a network device and improve the reliability of a bus system, an embodiment of the present application provides a network device, as shown in fig. 3, the network device includes at least one control core 31 and a plurality of data cores 32, the control core 31 includes a first controller 311 and a second controller 312, the data cores 32 include a third controller 321 and a fourth controller 322, the first controller 311 and the third controller 321 are connected by a first serial bus, and the second controller 312 and the fourth controller 322 are connected by a second serial bus. The network device may include a plurality of control cores 31, and in the embodiment of the present application, only one control core 31 is taken as an example for illustration, which is not limiting. The first controller, the second controller, the third controller and the fourth controller may be implemented by a Complex Programmable Logic Device (CPLD), or may be implemented by a Field-Programmable Gate Array (FPGA).
In this case, the first controller 311 is configured to send a first read/write signal to the third controller 321 through the first serial bus; a third controller 321, configured to process the first read/write signal;
a second controller 312 for transmitting a second read/write signal to the fourth controller 322 through the second serial bus when the first serial bus failure is detected; and a fourth controller 322 for processing the second read-write signal.
In the technical scheme provided by the embodiment of the application, the control core and the data core are connected through the serial bus, so that the number of connecting wires of the bus is reduced. In addition, the two controllers are respectively arranged on the control core and the data core, the control core and the data core are connected through the two serial buses through the controllers, and the control core and the data core can communicate through the other serial bus under the condition that one serial bus fails, so that the reliability of a bus system is improved.
In the embodiment of the present application, the network device includes two serial buses, namely, a first serial bus and a second serial bus. The first serial bus and the second serial bus are divided into a main serial bus and a standby serial bus. If the first serial bus is a main serial bus, the second serial bus is a standby serial bus; and if the second serial bus is the main serial bus, the first serial bus is a standby serial bus.
For each control core 31, the first controller 311 of the control core 31 communicates with the third controller 321 of each data core 32, respectively, through the first serial bus. That is, the first controller 311 of the control core 31 transmits read and write signals, such as first read and write signals, to the third controller 321 of each data core 32 through the first serial bus, respectively. The read/write signal may be used to instruct the third controller 321 to read/write data, including reading data stored in the data core, storing data in the data core, writing configuration information in the data core, and the like. The third controller 321, which receives the first read/write signal, processes the first read/write signal.
For each control core 31, the first controller 311 of the control core 31 is connected with the second controller 312. For each data core 32, the third controller 321 of that data core 32 is connected to the fourth controller 322. In addition, for each control core 31, the two controllers of the control core 31 mutually detect whether or not the serial bus to which the other is connected fails.
Specifically, for each control core 31, when the control core 31 communicates with the data core 32 through the first serial bus, as described above, the first controller 311 sends the first read/write signal to the third controller 321 through the first serial bus, and the second controller 312 of the control core 31 detects whether the first serial bus fails in real time. When a failure of the first serial bus is detected, the second controller 312 of the control core 31 communicates with the fourth controller 322 of each data core 32 via the second serial bus, respectively. That is, the second controller 312 of the control core 31 transmits read and write signals, such as a second read and write signal, to the fourth controller 322 of each data core 32 through the first serial bus, respectively. The fourth controller 322, which receives the first read/write signal, processes the second read/write signal.
In an embodiment of the present application, the second controller 312 may be further configured to send a repair signal to the fourth controller through the second serial bus when detecting the failure of the first serial bus, and repair the first controller 311 based on the repair signal; the fourth controller 322 may also be configured to repair the third controller based on the repair signal.
Specifically, the second controller 312 may send a repair signal to the fourth controller 322 through the second serial bus in addition to sending the second read/write signal to the fourth controller 322 through the second serial bus when detecting the first serial bus failure, and repair the first controller 311 based on the repair signal. The modification signal may be used to indicate a reset controller. The modification signal may also carry configuration information for instructing reconfiguration of the controller.
For each data core 32, after the fourth controller 322 of the data core 32 receives the repair signal, the third controller 321 of the data core 32 is repaired based on the repair signal.
In the embodiment of the present application, the first serial bus failure may be caused by the failure of only the third controller 321 of one data core 32, or only the first controller 311 of the control core 31, or the failure of both the third controllers 321 of a plurality of data cores 32 and the first controller 31 of the control core 31.
In one example, in order to accurately determine the failed third controller 321 and accurately repair the failed third controller 321, the second controller 312 sends a probing signal to the fourth controller 322 of each data core 32 through the second serial bus; the fourth controller 322 of each data core 32, upon receiving the probing signal, detects whether the third controller 321 of that data core 32 has failed. If the third controller 321 of one data core 32 in the network device fails, for example, the third controller 321 of the first data core fails, the fourth controller 322 of the first data core 32 sends a first probe response signal to the second controller 312 of the control core 31, and the first probe response signal indicates the controller failure. If the third controller 321 of one data core 32 in the network device is normal, for example, the third controller 321 of the second data core is normal, the fourth controller 322 of the second data core 32 sends a second probe response signal to the second controller 312 of the control core 31, where the second probe response signal indicates that the controller is normal.
The second controller 312 receives the first probe response signal and the second probe response signal and transmits a repair signal to the fourth controller 322 (i.e., the third controller 321 of the first data core) that transmitted the first probe response signal.
In the embodiment of the present application, if the network device includes one control core 31, the second controller 312 of the control core 31 sends a probe signal to the fourth controller 322 of each data core 32 through the second serial bus, respectively, so as to detect the failed third controller 321.
If the network device includes a plurality of control cores 31, one control core 31 may be pre-designated from the plurality of control cores 31, and the second controller 312 of the designated control core 31 transmits a probe signal to the fourth controller 322 of each data core 32 through the second serial bus, respectively, to detect the failed third controller 321.
In addition, for each control core 31, the second controller 312 of the control core 31 detects whether the first controller 311 of the control core 31 fails. In the case where the first controller 311 of the control core 31 is detected, the second controller 312 of the control core 31 repairs the first controller 311 of the control core 31 based on the repair signal.
In another example, to implement a fast-forwarding repair failed serial bus, the second controller 312 directly sends repair signals to the fourth controller 322 of each data core 32 via the second serial bus, respectively, upon detecting the first serial bus failure. The fourth controller 322 of each data core 32 is capable of receiving the repair signal and repairing the third controller 321 based on the repair signal
In this embodiment, if the network device includes one control core 31, the second controller 312 of the control core 31 directly sends a repair signal to the fourth controller 322 of each data core 32 through the second serial bus when detecting that the first serial bus fails.
If the network device includes a plurality of control cores 31, one control core 31 may be pre-designated from the plurality of control cores 31, and the second controller 312 of the designated control core 31 directly transmits a repair signal to the fourth controller 322 of each data core 32 through the second serial bus, respectively, upon detecting the first serial bus failure.
In addition, for each control core 31, the second controller 312 of the control core 31 detects whether the first controller 311 of the control core 31 fails. In the case where the first controller 311 of the control core 31 is detected, the second controller 312 of the control core 31 repairs the first controller 311 of the control core 31 based on the repair signal.
In the embodiment of the application, the two controllers are respectively arranged on the control core and the data core, the control core and the data core are connected through the two serial buses through the controllers, and the control core and the data core can communicate through the other serial bus under the condition that one serial bus fails, so that the reliability of a bus system is improved. In addition, in the event of a failure of one serial bus, the failed serial bus is repaired by the other serial bus. Therefore, if the other serial bus fails, the control core and the data core can communicate through the repaired serial bus, and the reliability of the bus system is further improved.
In addition, in the embodiment of the application, the signals transmitted between the control core and the data core are switched between the first serial bus and the second serial bus, so that normal communication between the control core and the data core is ensured. In the whole process, human intervention is not needed, and the reliability of the bus system is further improved.
In an embodiment of the present application, the first controller 311 may be further configured to determine that the first serial bus fails when the read-write success signal fed back by the third controller is not received after the first read-write signal is continuously sent for a preset number of times.
The size of the preset quantity can be set according to actual requirements. For example, the preset number may be 2, 3, 4, or 5, etc.
After sending the first read/write signal to the third controller 321 of one data core 32, if the read/write success signal fed back by the third controller 321 of the data core 32 is not received, the first controller 311 sends the first read/write signal to the third controller 321 of the data core 32 again. If the read-write success signal fed back by the third controller 321 of the data core 32 is not received in the first read-write signal sent for a preset number of times continuously, the first controller 311 determines that the first serial bus has a fault.
In the embodiment of the present application, the first controller 311 may also determine in other manners. For example, a detection module is configured on each data core. For each data core, the detection module of the data core 32 detects whether the controller (including the third controller 321 and the fourth controller 322) of the data core 32 fails, and in case that the controller (including the first controller 311 and the second controller 312) of the data core 32 is detected, sends a signal indicating that the controller of the data core 32 fails to the controller of the control core 31, so that the controller of the control core 31 repairs the controller of the data core 32, and switches the serial bus that transmits the read and write signals.
In an embodiment of the present application, the first controller 311 may be further configured to, when the first controller 311 communicates with the third controller 321 through the first serial bus, if it is detected that an operating state of a first data core of the plurality of data cores is abnormal, use the first serial bus as a debug bus;
the first controller 311 may be further configured to use the first serial bus as the functional bus when the first controller 311 detects that the operating states of the plurality of data cores are all normal when the first controller 311 communicates with the third controller 321 through the first serial bus.
In this embodiment, the first controller 311 detects whether the operating state of the data core is abnormal in real time. If the working state of a first data core in the plurality of data cores is detected to be abnormal, for example, the program running in the processor of the first data core is abnormal, the interface is abnormal, and the like, the first serial bus is used as a debugging bus. At this time, the first controller 311 may debug the plurality of data cores using the first serial bus.
The first controller 311 takes the first serial bus as the functional bus when detecting that the operating states of the plurality of data cores 32 are all normal, that is, the operating state of the first data core is recovered to be normal. At this time, the first serial bus is used as a functional bus to perform management, status monitoring, and the like.
In the embodiment of the present application, the same physical wiring resources are used, the control core 31 determines the working state of the whole machine (including the plurality of data cores 32), and when the state of the whole machine is abnormal, the serial bus is multiplexed from the functional bus to the debugging bus without additionally arranging other debugging buses, so that the utilization rate of the bus is improved, and the wiring resources are saved.
Based on the foregoing network device embodiment, the present application further provides a bus configuration method. Referring to fig. 4, fig. 4 is a schematic flowchart of a bus configuration method provided in an embodiment of the present application, where the method is applied to a network device, the network device includes at least one control core and a plurality of data cores, the control core includes a first controller and a second controller, the data cores include a third controller and a fourth controller, the first controller and the third controller are connected through a first serial bus, and the second controller and the fourth controller are connected through a second serial bus; the method comprises the following steps:
step S41, the first controller sends a first read/write signal to the third controller through the first serial bus;
step S42, the third controller processes the first read/write signal;
step S43, the second controller sends a second read/write signal to the fourth controller through the second serial bus when detecting the failure of the first serial bus;
in step S44, the fourth controller processes the second read-write signal.
In the technical scheme provided by the embodiment of the application, the control core and the data core are connected through the serial bus, so that the number of connecting wires of the bus is reduced. In addition, the two controllers are respectively arranged on the control core and the data core, the control core and the data core are connected through the two serial buses through the controllers, and the control core and the data core can communicate through the other serial bus under the condition that one serial bus fails, so that the reliability of a bus system is improved.
In an embodiment of the present application, the method further includes: when the second controller detects the fault of the first serial bus, the second controller sends a repair signal to the fourth controller through the second serial bus, and the first controller is repaired based on the repair signal; the fourth controller repairs the third controller based on the repair signal.
In the embodiment of the application, the two controllers are respectively arranged on the control core and the data core, the control core and the data core are connected through the two serial buses through the controllers, and the control core and the data core can communicate through the other serial bus under the condition that one serial bus fails, so that the reliability of a bus system is improved. In addition, in the event of a failure of one serial bus, the failed serial bus is repaired by the other serial bus. Therefore, if the other serial bus fails, the control core and the data core can communicate through the repaired serial bus, and the reliability of the bus system is further improved.
In addition, in the embodiment of the application, the signals transmitted between the control core and the data core are switched between the first serial bus and the second serial bus, so that normal communication between the control core and the data core is ensured. In the whole process, human intervention is not needed, and the reliability of the bus system is further improved.
In an embodiment of the present application, in the method, the following steps may be adopted to determine whether the first serial bus fails:
and if the first controller continuously sends the first read-write signals for a preset number of times and does not receive the read-write success signals fed back by the third controller, determining that the first serial bus fails.
In an embodiment of the application, when the first controller communicates with the third controller through the first serial bus, if the working state of a first data core of the plurality of data cores is detected to be abnormal, the first controller takes the first serial bus as a debugging bus;
when the first controller communicates with the third controller through the first serial bus, and if the working states of the data cores are detected to be normal, the first controller takes the first serial bus as a functional bus.
In the embodiment of the application, the same physical wiring resources are used, the control core judges the working state of the whole machine (comprising a plurality of data cores), when the state of the whole machine is abnormal, the serial bus is multiplexed from the functional bus to the debugging bus, and other debugging buses do not need to be additionally arranged, so that the utilization rate of the bus is improved, and the wiring resources are saved.
The bus configuration method provided by the embodiment of the present application is described in detail below with reference to the network devices shown in fig. 5 a-c. The network device shown in fig. 5a includes a Master and 3 Slave, which are Slave-1, Slave-2 and Slave-3, respectively. Wherein Master denotes a control core and Slave denotes a data core.
The Master is provided with a controller 0 (namely, a first controller) and a controller 1 (namely, a second controller), and the Slave-1, the Slave-2 and the Slave-3 are also provided with a controller 0 (namely, a third controller) and a controller 1 (namely, a fourth controller), respectively.
Master's controller 0 and Slave-1, Slave-2 and Slave-3's controller 0 are connected via BUS1 (serial BUS), and Master's controller 1 and Slave-1, Slave-2 and Slave-3's controller 1 are connected via BUS2 (serial BUS). The BUS1 is a main serial BUS, and the BUS2 is a standby serial BUS.
The BUS1 is used as a functional BUS, and the Master controller 0 detects whether the working states of the Slave-1, the Slave-2 and the Slave-3 are normal through the BUS 1. If the working states of the Slave-1, the Slave-2 and the Slave-3 are all normal, the Master controller 0 sends read-write signals to the Slave-1, the Slave-2 and the Slave-3 through the BUS 1.
If not, if the working state of the Slave-1 is abnormal, the BUS1 is set as a debugging BUS. Master's controller 0 debugs the Slave-1, Slave-2 and Slave-3 through BUS 1. When the working states of the Slave-1, the Slave-2 and the Slave-3 are all debugged to be normal, the BUS1 is set as a functional BUS. And the controller 0 of the Master sends read-write signals to the Slave-1, the Slave-2 and the Slave-3 through the BUS 1.
The controller 0 of the Master sends read-write signals to the Slave-1, the Slave-2 and the Slave-3 through the BUS1, and the controller 0 of the Slave-1, the Slave-2 and the Slave-3 receives the read-write signals, as shown in figure 5 b. The black arrows in fig. 5b indicate the direction of signal transmission between the Master and the Slave.
When the BUS1 fails, the BUS1 at the Slave-1 as shown in fig. 5c fails, the Master enables the controller 1, and the Master's controller 1 sends read-write signals to the Slave-1, the Slave-2 and the Slave-3 through the BUS 2. The controller 1 of the Slave-1, the Slave-2 and the Slave-3 receives read-write signals. In fig. 5c, black arrows indicate the direction of signal transmission between the Master and the Slave, and an "X" symbol indicates a faulty node.
In addition, when the BUS1 fails, the Master's controller 1 sends modification signals to the Slave-1, the Slave-2 and the Slave-3 through the BUS 2. The controller 1 of the Slave-1, the Slave-2 and the Slave-3 receives the repair signal and repairs the controller 0 of the Slave-1, the Slave-2 and the Slave-3 based on the repair signal.
Then, when the BUS2 fails, the Master enables the controller 0, and the Master controller 0 sends read-write signals to the Slave-1, the Slave-2 and the Slave-3 through the BUS 1. The controller 0 of the Slave-1, the Slave-2 and the Slave-3 receives the read-write signals.
In addition, when the BUS2 fails, the Master's controller 0 sends modification signals to the Slave-1, the Slave-2 and the Slave-3 through the BUS 1. The controllers of the Slave-1, the Slave-2 and the Slave-3 receive the repair signal and repair the controller 1 of the Slave-1, the Slave-2 and the Slave-3 based on the repair signal.
According to the technical scheme provided by the embodiment of the application, the self-healing of the main serial bus and the standby serial bus is realized, and the reliability of a bus system is improved.
Based on the foregoing network device embodiments, the present application further provides a machine-readable storage medium storing a machine-executable program, which can be executed by a processor. The processor is caused by a machine executable program to implement any of the steps shown in figures 3-5 above.
The machine-readable storage medium may include a RAM (Random Access Memory) and a NVM (Non-Volatile Memory), such as at least one disk Memory. Additionally, the machine-readable storage medium may be at least one memory device located remotely from the aforementioned processor.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
All the embodiments in the present specification are described in a related manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the embodiments of the bus configuration method and the machine-readable storage medium, since they are substantially similar to the embodiments of the network device, the description is relatively simple, and for the relevant points, reference may be made to the partial description of the embodiments of the network device method.
The above description is only for the preferred embodiment of the present application, and is not intended to limit the scope of the present application. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application are included in the protection scope of the present application.
Claims (10)
1. A network device, comprising at least one control core comprising a first controller and a second controller and a plurality of data cores comprising a third controller and a fourth controller, the first controller and the third controller being connected by a first serial bus and the second controller and the fourth controller being connected by a second serial bus;
the first controller is configured to send a first read/write signal to the third controller through the first serial bus; the third controller is used for processing the first read-write signal;
the second controller is used for sending a second read-write signal to the fourth controller through the second serial bus when the first serial bus fault is detected; the fourth controller is configured to process the second read-write signal.
2. The network device of claim 1,
the second controller is further configured to send a repair signal to the fourth controller through the second serial bus when the first serial bus fault is detected, and repair the first controller based on the repair signal;
the fourth controller is further configured to repair the third controller based on the repair signal.
3. The network device of claim 1, wherein the first controller is further configured to determine that the first serial bus has failed when a predetermined number of consecutive times of sending the first read/write signal do not receive the read/write success signal fed back by the third controller.
4. The network device according to claim 1, wherein the first controller is further configured to, in a case where the first controller communicates with the third controller through the first serial bus, if an operating state of a first data core among the plurality of data cores is detected as abnormal, take the first serial bus as a debug bus;
the first controller is further configured to, when the first controller communicates with the third controller through the first serial bus, use the first serial bus as a functional bus if it is detected that the operating states of the multiple data cores are all normal.
5. The network device of any of claims 1-4, wherein the first controller, the second controller, the third controller, and the fourth controller are complex programmable logic devices or field-editable gate arrays.
6. A bus configuration method is applied to a network device, the network device comprises at least one control core and a plurality of data cores, the control core comprises a first controller and a second controller, the data cores comprise a third controller and a fourth controller, the first controller and the third controller are connected through a first serial bus, and the second controller and the fourth controller are connected through a second serial bus; the method comprises the following steps:
the first controller sends a first read-write signal to the third controller through the first serial bus;
the third controller processes the first read-write signal;
the second controller sends a second read-write signal to the fourth controller through the second serial bus when detecting the first serial bus fault;
the fourth controller processes the second read-write signal.
7. The method of claim 6, further comprising:
when the second controller detects the fault of the first serial bus, sending a repair signal to the fourth controller through the second serial bus, and repairing the first controller based on the repair signal;
the fourth controller repairs the third controller based on the repair signal.
8. The method of claim 6, further comprising:
and if the first controller continuously sends the first read-write signal for a preset number of times and does not receive the read-write success signal fed back by the third controller, determining that the first serial bus has a fault.
9. The method of claim 6, further comprising:
the first controller, under the condition that the first controller communicates with the third controller through the first serial bus, if the working state of a first data core in the plurality of data cores is detected to be abnormal, using the first serial bus as a debugging bus;
and the first controller takes the first serial bus as a functional bus when detecting that the working states of the data cores are all normal under the condition that the first controller communicates with the third controller through the first serial bus.
10. A machine-readable storage medium storing a machine-executable program executable by a processor, the processor being caused by the machine-executable program to: -carrying out the method steps of any one of claims 6 to 9.
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