CN112382624A

CN112382624A - Chip and mainboard

Info

Publication number: CN112382624A
Application number: CN202011369115.XA
Authority: CN
Inventors: 林少芳; 杨晓君; 杜树安; 杨光林; 孟凡晓
Original assignee: Haiguang Information Technology Co Ltd
Current assignee: Haiguang Information Technology Co Ltd
Priority date: 2020-11-30
Filing date: 2020-11-30
Publication date: 2021-02-19

Abstract

The invention provides a chip and a mainboard, wherein the chip comprises a packaging substrate with a first surface and a second surface which are opposite, and at least one memory bare chip arranged on the first surface of the packaging substrate. The first side of the package substrate is provided with a central processor die electrically connected with each of the at least one memory die for writing data to or reading data from each memory die. The second surface of the packaging substrate is provided with pins used for being electrically connected with the printed circuit board, and the central processor bare chip is also electrically connected with the pins of the second surface. The central processing unit bare chip and the at least one memory bare chip are packaged on the packaging substrate, and each memory bare chip is electrically connected with the central processing unit bare chip, so that the central processing unit bare chip and the memory bare chips on the packaging substrate can work, the integration level of a chip and a mainboard is improved, the area of a printed circuit board of the mainboard can be reduced, the system design is simplified, and the system reliability is improved.

Description

Chip and mainboard

Technical Field

The invention relates to the technical field of computers, in particular to a chip and a mainboard.

Background

With the development of computers, device integration is gradually becoming a trend. The connection mode between the central processing unit and the memory module of the mainboard in the prior art is as follows: the printed circuit board is provided with a central processing unit and a plurality of memory connectors, and each memory connector is inserted with one memory bank, namely, all memories of the mainboard are provided by the memory banks on the printed circuit board. Because the size of the memory bank is larger, and the memory connector occupies more area of the printed circuit board when being arranged on the printed circuit board, the memory connector occupies the arrangement space of other devices, and the integration level of the mainboard is lower.

Disclosure of Invention

The invention provides a chip and a mainboard, which are used for improving the integration level of the chip and the mainboard and reducing the area of a printed circuit board of the mainboard.

In a first aspect, the present invention provides a chip including a package substrate having first and second opposing faces, and at least one memory die disposed on the first face of the package substrate. A central processor die is also disposed on the first side of the package substrate and electrically connected to each of the at least one memory die for writing data to or reading data from each of the memory dies. Pins for electrically connecting with the printed circuit board are further arranged on the second surface of the packaging substrate, and the central processor die is further electrically connected with the pins on the second surface.

In the above scheme, the central processing unit bare chip and the at least one memory bare chip are packaged on the packaging substrate, and each memory bare chip is electrically connected with the central processing unit bare chip, so that the central processing unit bare chip and the memory bare chips on the packaging substrate can work, the integration level of the chip and the mainboard is improved, and the area of the printed circuit board of the mainboard can be reduced. When the capacity of the required memory is not large, the memory connector and the memory bank do not need to be arranged on the mainboard, and the memory can be stored only by the memory bare chip arranged in the packaging substrate. In the prior art, a central processing unit chip and a memory bank are respectively disposed on a printed circuit board of a motherboard, and the central processing unit chip and the memory bank are electrically connected through traces and vias in the printed circuit board. Compared with the prior art, the scheme of this application, the central processing unit bare chip and the memory bare chip of the scheme of this application are connected through walking the line and the via hole electricity in the packaging substrate, because the area of packaging substrate compares the printed circuit board's of mainboard area less, the line width and the length of walking the line and the via hole in the packaging substrate can be littleer, the integrated level is higher to make the data transmission speed between central processing unit bare chip and the memory bare chip obtain improving, and simplify system design, improve the reliability of system.

In one embodiment, the memory die is a DDR memory die to increase the memory capacity and data transmission speed of the chip.

In one embodiment, the cpu die and the at least one memory die are flip-chip bonded to the package substrate to simplify the structure and electrical connections.

In one embodiment, a memory controller is integrated into the cpu die and electrically connected to the address and data signal bumps in each memory die to increase the integration and speed of data transfer between the cpu die and the memory die.

In a specific embodiment, the package substrate includes a first metal layer, a second metal layer, a third metal layer, and a tenth metal layer stacked and insulated from each other. The central processing unit bare chip and the at least one memory bare chip are arranged on the first metal layer of the packaging substrate; the memory controller is electrically connected with the address and data signal bumps in each memory bare chip through the via holes for connecting the first metal layer and the second metal layer and the wiring in the second metal layer; the pins are arranged on the tenth metal layer, and the memory controller is electrically connected with the pins through the through holes between the first metal layer and the second metal layer, the wires in the second metal layer and the through holes between the second metal layer and the tenth metal layer. To simplify the structure of the package substrate. The packaging of the CPU bare chip and the memory bare chip is completed at low cost by using a small number of metal layers.

In a specific embodiment, a plurality of first decoupling capacitors are disposed on the first side of the package substrate, each of the first decoupling capacitors being electrically connected to the cpu die and/or the memory die. To remove noise in the chip.

In a specific embodiment, a plurality of second decoupling capacitors are further disposed on the second side of the package substrate, each second decoupling capacitor is electrically connected to the cpu die and/or the memory die, and the height of the second decoupling capacitor is not higher than the height of the pin. So as to better remove the noise in the chip and simultaneously improve the chip integration level.

In a second aspect, the present invention further provides a motherboard, where the motherboard includes a printed circuit board and any one of the above chips disposed on the printed circuit board, and the pins are electrically connected to the printed circuit board.

In a specific embodiment, the printed circuit board is further provided with at least one memory connector and at least one memory bank plugged on the at least one memory connector, and each memory connector is further electrically connected with the cpu die. The printed circuit board is also provided with a BIOS chip which is electrically connected with the central processing unit bare chip and each memory connector so as to drive at least one memory bare chip and at least one memory bank to work. When a large-capacity memory application scene is needed, the memory connector is designed on the printed circuit board, and the memory bare chip in the packaging substrate and the memory bank on the printed circuit board work together through the BIOS chip configuration, so that the problem of wiring of driving two or more wires on the packaging substrate and the main board is solved, and the problem of compatibility between the memory bare chip on the packaging substrate and the memory bank on the main board is solved.

Drawings

Fig. 1 is a schematic cross-sectional structural diagram of a chip according to an embodiment of the present invention;

FIG. 2 is a schematic top view of a chip shown in FIG. 1;

FIG. 3 is a bottom view of a chip shown in FIG. 1;

fig. 4 is a schematic cross-sectional structural diagram of a package structure according to an embodiment of the invention;

fig. 5 is a schematic cross-sectional structural diagram of a main board according to an embodiment of the present invention.

Reference numerals:

10-package substrate 11-first side 12-second side 13-pins

14-bump 15-trace 16-via 20-cpu die

21-memory controller 30-memory die 41-first decoupling capacitance

42-second decoupling capacitor 50-printed circuit board 51-memory connector

52-memory bank 53-BIOS chip

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

For convenience of understanding the chip provided in the embodiment of the present invention, an application scenario of the chip provided in the embodiment of the present invention is first described below, where the chip is applied to a computer device such as a server. The chip will be described in detail with reference to the accompanying drawings.

Referring to fig. 1, 2 and 3, a chip provided by the embodiment of the invention includes a package substrate 10 having a first side 11 and a second side 12 opposite to each other, and at least one memory die 30 disposed on the first side 11 of the package substrate 10. A central processor die 20 is also disposed on the first side 11 of the package substrate 10, the central processor die 20 being electrically connected to each of the at least one memory die 30 for writing data to each of the memory dies 30 or reading data from each of the memory dies 30. Pins 13 for electrical connection with the printed circuit board 50 are also provided on the second side 12 of the package substrate 10, and the cpu die 20 is also electrically connected with the pins 13 on the second side 12.

In the above scheme, the cpu die 20 and the at least one memory die 30 are packaged on one package substrate 10, and each memory die 30 is electrically connected to the cpu die 20, so that the cpu die 20 and the memory die 30 on the package substrate 10 can work, the integration level of the chip and the motherboard is improved, and the area of the pcb 50 of the motherboard can be reduced. When the capacity of the required memory is not large, the memory connector and the memory bank do not need to be arranged on the main board, and the memory can be stored only by the memory bare chip 30 arranged in the package substrate 10. In the prior art, a central processing unit chip and a memory bank are respectively disposed on a printed circuit board 50 of a motherboard, and the central processing unit chip and the memory bank are electrically connected through traces 15 and vias 16 in the printed circuit board 50. Compared with the prior art, the scheme of this application, the central processing unit bare chip 20 and the memory bare chip 30 of the scheme of this application are electrically connected through the line 15 and the via hole 16 in the packaging substrate 10, because the area of the printed circuit board 50 of mainboard is less compared to the area of packaging substrate 10, the line width and the length of the line 15 and the via hole 16 in the packaging substrate 10 can be smaller, the integration level is higher, thereby the data transmission speed between the central processing unit bare chip 20 and the memory bare chip 30 is improved, and the system design is simplified, and the reliability of the system is improved. The arrangement of the above components will be described in detail with reference to the accompanying drawings.

Referring to fig. 1, a package substrate 10 has a first surface 11 and a second surface 12 opposite to each other, where the first surface 11 shown in fig. 1 is an upper surface of the package substrate 10, and the second surface 12 is a lower surface of the package substrate 10. The second surface 12 of the package substrate 10 is provided with a lead 13, the lead 13 is exposed outside the package layer after the package, and the lead 13 is used for connecting to the printed circuit board 50 of the motherboard. When the leads 13 are provided, the leads 13 may be ball-shaped leads 13 in a BGA package as shown in fig. 1, or may be pin-shaped leads 13 in an LGA package.

Referring to fig. 1 and 2, a cpu die 20 is disposed on the first surface 11 of the package substrate 10, and the cpu die 20 is electrically connected to the pins 13 on the second surface 12 of the package substrate 10. When provided, the cpu die 20 may be flip-chip bonded to the first side 11 of the package substrate 10. Specifically, the bumps 14 are disposed on the lower surface of the cpu die 20 (referring to the structure shown in fig. 1), and the pads for electrically connecting with the cpu die 20 are disposed on the first surface 11 of the package substrate 10, so that the cpu die 20 is directly flip-mounted on the corresponding pads on the first surface 11 of the package substrate 10, and thus, a bonding wire connection manner is not required, and the structure and the electrical connection manner are simplified. As shown in fig. 1, the bumps 14 on the cpu die 20 are electrically connected to the pins 13 on the second side 12 of the package substrate 10 through traces 15 and vias 16 in the package substrate 10.

With continued reference to fig. 1 and 2, at least one memory die 30 is disposed on the first side 11 of the package substrate 10, and each memory die 30 is electrically connected to the cpu die 20. Specifically, when the number of the memory dies 30 is determined, the number of the memory dies 30 may be any value of not less than 1, such as 1, 2, 3, 4, 6, 8, and the like. When the memory die 30 is multiple, referring to fig. 2, multiple memory dies 30 can be arranged side by side on both sides of the cpu die 20 to facilitate electrical connection between the cpu die 20 and each memory die 30. In determining the type of each memory die 30, the memory die 30 may be a DDR memory die 30 to increase the memory capacity and data transmission speed of the chip. Specifically, the memory dies 30 may be the DDR3 memory dies 30, DDR4 memory dies 30, and DDR5 memory dies 30 that are mature in the prior art. Of course, the memory die 30 may also be a DDR6 memory die 30, a DDR7 memory die 30, etc. currently under development. That is, it is within the scope of the present invention to realize that the cpu die 20 and the memory die 30 are of the same type, so that the cpu die 20 can write data into the memory die 30 or read data from the memory die 30.

When each memory die 30 is attached to the first side 11 of the package substrate 10, each memory die 30 may be flip-chip attached to the package substrate 10 to simplify the structure and electrical connections. Specifically, bumps 14 are disposed on a lower surface (with reference to the structure shown in fig. 1) of each memory die 30, pads for electrically connecting with the corresponding memory die 30 are disposed on the first surface 11 of the package substrate 10, and the memory die 30 can be directly flip-chip mounted on the corresponding pads on the first surface 11 of the package substrate 10, so that a bonding wire connection manner is not required, the structure is simplified, and the connection is facilitated.

In electrically connecting the cpu die 20 and each memory die 30, as shown in fig. 1, the cpu die 20 and each memory die 30 are electrically connected through the traces 15 and the vias 16 in the package substrate 10. For example, referring to fig. 1, a memory controller 21 may be integrated in the cpu die 20, the bumps 14 of each memory die 30 have address signal bumps 14 and data signal bumps 14, and the memory controller 21 is electrically connected to the address and data signal bumps 14 of each memory die 30, so as to improve the integration by integrating the memory controller 21 in the cpu die 20. Compared with the prior art in which the memory controller 21 is disposed on the motherboard or integrated in the cpu chip, the scheme of the present application can improve the data transmission speed between the cpu die 20 and the memory die 30.

When the trace 15 is specifically implemented in the package substrate 10, referring to fig. 4, the package substrate 10 includes a first metal layer, a second metal layer, a third metal layer, and a tenth metal layer, which are stacked and insulated from each other. Wherein the first metal layer is a power plane layer. The second metal layer is a wiring layer. The third metal layer is a ground layer. The fourth metal layer is a wiring layer. The fifth metal layer and the sixth metal layer are Core layers and are respectively provided with a power supply and a ground. The seventh metal layer is a wiring layer, the eighth metal layer is a ground layer, the ninth metal layer is a power supply layer, and the tenth metal layer is a ground layer. The cpu die 20 and the at least one memory die 30 may be disposed on a first metal layer of the package substrate 10, i.e., a bonding pad electrically connected to the cpu die 20 and a bonding pad electrically connected to the at least one memory die 30 are disposed on the first metal layer. Referring to fig. 1, the memory controller 21 and the address and data signal bumps 14 in each memory die 30 may be electrically connected through the vias 16 connecting the first metal layer and the second metal layer, and the traces 15 in the second metal layer. That is, the bump 14 on the memory controller 21 is electrically connected to the corresponding pad on the first metal layer, then the signal line of the memory controller 21 is connected to the second metal layer through the via 16 between the first metal layer and the second metal layer, then the signal line of the memory controller 21 is guided to the position right below each memory die 30 through the trace 15 in the second metal layer, and then the signal line is electrically connected to the pads electrically connected to the data signal bump 14 and the address signal bump 14 on the memory die 30 through the via 16 between the first metal layer and the second metal layer, so as to realize the electrical connection between the memory controller 21 and each memory die 30. The pin 13 is disposed on the tenth metal layer, and the memory controller 21 is electrically connected to the pin 13 through the via 16 between the first metal layer and the second metal layer, the trace 15 in the second metal layer, and the via 16 between the second metal layer and the tenth metal layer. That is, the bump 14 on the memory controller 21 is electrically connected to the corresponding pad on the first metal layer, then the signal line of the memory controller 21 is connected to the second metal layer through the via 16 between the first metal layer and the second metal layer, then the signal line of the memory controller 21 is guided to the position right above the corresponding pin 13 through the trace 15 in the second metal layer, and then the signal line is electrically connected through the via 16 between the second metal layer and the tenth metal layer. To simplify the structure of the package substrate 10. And the packaging of the cpu die 20 and the memory die 30 together is accomplished at low cost using a smaller number of metal layers.

Referring to fig. 1 and 2, a plurality of first decoupling capacitors 41 may be further disposed on the first surface 11 of the package substrate 10, and each first decoupling capacitor 41 is electrically connected to the cpu die 20 and/or the memory die 30. To remove noise in the chip. The number of the first decoupling capacitors 41 may be any value such as 2, 3, 4, 5, etc. Referring to fig. 2, a plurality of first decoupling capacitors 41 may be arranged on both sides of the plurality of memory dies 30 and the cpu die 20 for electrical connection. Each first decoupling capacitor 41 is arranged on a first metal layer. Each first decoupling capacitor 41 may be electrically connected only to the cpu die 20 and not to the memory die 30; it is also possible to electrically connect only the memory die 30 and not the cpu die 20; and may be electrically connected to both the cpu and the memory die 30. In particular, each first decoupling capacitor 41 is electrically connected to the cpu die 20 and/or the memory die 30 through the traces 15 and the vias 16 in the package substrate 10.

Referring to fig. 1 and 3, a plurality of second decoupling capacitors 42 may be further disposed on the second side 12 of the package substrate 10, each second decoupling capacitor 42 is electrically connected to the cpu die 20 and/or the memory die 30, and the height of the second decoupling capacitor 42 is not higher than the height of the leads 13. So as to better remove the noise in the chip and improve the integration level of the chip. Specifically, the number of the second decoupling capacitors 42 may be any value, such as 2, 3, 4, 5, and the like. Referring to fig. 3, a plurality of second decoupling capacitors 42 may be arranged on both sides of the lead 13 for convenience of arrangement and electrical connection. Each second decoupling capacitor 42 may be electrically connected only to the cpu die 20 and not to the memory die 30; it is also possible to electrically connect only the memory die 30 and not the cpu die 20; and may be electrically connected to both the cpu and the memory die 30. In particular, each second decoupling capacitor 42 may be disposed on the tenth metal layer, and each second decoupling capacitor 42 is electrically connected to the cpu die 20 and/or the memory die 30 through the traces 15 and the vias 16 in the package substrate 10. In addition, in order to prevent the second decoupling capacitor 42 from interfering with the connection between the lead 13 on the package substrate 10 and the printed circuit board 50 of the motherboard, the height of the second decoupling capacitor 42 is not higher than the height of the lead 13 when necessary, specifically, the height of the second decoupling capacitor 42 may be equal to the height of the lead 13 or lower than the height of the lead 13. For example, when the height of the lead 13 is 0.5mm, the height of the second decoupling capacitor 42 may be made not more than 0.5 mm.

By packaging the cpu die 20 and the at least one memory die 30 on one package substrate 10, and electrically connecting each memory die 30 to the cpu die 20, the cpu die 20 and the memory die 30 on the package substrate 10 can operate, thereby improving the integration of the chip and the motherboard, and reducing the area of the pcb 50 of the motherboard. When the capacity of the required memory is not large, the memory connector and the memory bank do not need to be arranged on the main board, and the memory can be stored only by the memory bare chip 30 arranged in the package substrate 10. In the prior art, a central processing unit chip and a memory bank are respectively disposed on a printed circuit board 50 of a motherboard, and the central processing unit chip and the memory bank are electrically connected through traces 15 and vias 16 in the printed circuit board 50. Compared with the prior art, the scheme of this application, the central processing unit bare chip 20 and the memory bare chip 30 of the scheme of this application are electrically connected through the line 15 and the via hole 16 in the packaging substrate 10, because the area of the printed circuit board 50 of mainboard is less compared to the area of packaging substrate 10, the line width and the length of the line 15 and the via hole 16 in the packaging substrate 10 can be smaller, the integration level is higher, thereby the data transmission speed between the central processing unit bare chip 20 and the memory bare chip 30 is improved, and the system design is simplified, and the reliability of the system is improved.

In addition, referring to fig. 5, the main board includes a printed circuit board 50 and any one of the above chips disposed on the printed circuit board 50, and the pins 13 are electrically connected to the printed circuit board 50. By packaging the cpu die 20 and the at least one memory die 30 on one package substrate 10, and electrically connecting each memory die 30 to the cpu die 20, the cpu die 20 and the memory die 30 on the package substrate 10 can operate, thereby improving the integration of the chip and the motherboard, and reducing the area of the pcb 50 of the motherboard. When the capacity of the required memory is not large, the memory connector 51 and the memory bank 52 need not be provided on the main board, and the memory can be stored only by the memory die 30 provided in the package substrate 10. In the prior art, a central processing unit chip and a memory bank 52 are respectively disposed on a printed circuit board 50 of a motherboard, and the central processing unit chip and the memory bank 52 are electrically connected through traces 15 and vias 16 in the printed circuit board 50. Compared with the prior art, the scheme of this application, the central processing unit bare chip 20 and the memory bare chip 30 of the scheme of this application are electrically connected through the line 15 and the via hole 16 in the packaging substrate 10, because the area of the printed circuit board 50 of mainboard is less compared to the area of packaging substrate 10, the line width and the length of the line 15 and the via hole 16 in the packaging substrate 10 can be smaller, the integration level is higher, thereby the data transmission speed between the central processing unit bare chip 20 and the memory bare chip 30 is improved, and the system design is simplified, and the reliability of the system is improved.

With continued reference to fig. 5, at least one memory connector 51 and at least one memory bank 52 plugged into the at least one memory connector 51 may also be disposed on the printed circuit board 50, and each memory connector 51 is further electrically connected to the cpu die 20 to expand the memory capacity of the motherboard. The memory bank 52 may be a DIMM memory bank 52. Each memory connector 51 has a memory bank 52 plugged therein. The memory connector 51 may be soldered to the printed circuit board 50. When the number of the memory banks 52 and the memory connectors 51 is specifically determined, the number of the memory banks 52 and the memory connectors 51 may be any value such as 1, 2, 3, or 4. The number of the memory banks 52 is mainly related to the required memory capacity, and when the required memory capacity is large, a plurality of memory banks 52 may be provided. When the required memory capacity is not large, a few memory banks 52 may be provided. Even in the case where the memory die 30 in the chip can satisfy the memory capacity, the memory bank 52 and the memory connector 51 may not be provided. Each memory connector 51 can be electrically connected to the pins 13 electrically connected to the cpu die 20 on the chip through the traces 15 and the vias 16 in the printed circuit board 50, and then electrically connected to the cpu die 20 through the corresponding pins 13.

With continued reference to fig. 5, a BIOS chip 53 is also disposed on the printed circuit board 50, and the BIOS chip 53 is electrically connected to both the cpu die 20 and each of the memory connectors 51 to drive the at least one memory die 30 and the at least one memory bank 52 to operate. When a large-capacity memory application scene is needed, the memory connector 51 is designed on the printed circuit board 50, and the BIOS chip 53 is configured, so that the memory bare chip 30 in the package substrate 10 and the memory bank 52 on the printed circuit board 50 work together, and meanwhile, the signal reflection of the memory bare chip 30 on the package substrate 10 is reduced, the problem of wiring that one drives two or more on the package substrate 10 and the mainboard is solved, and the problem of compatibility between the memory bare chip 30 on the package substrate 10 and the memory bank 52 on the mainboard is solved. Specifically, when the BIOS chip 53 is electrically connected to the cpu die 20, the BIOS chip 53 is electrically connected to the pins 13 of the chip through the traces 15 and the vias 16 in the printed circuit board 50, and the connected pins 13 are electrically connected to the cpu die 20 and the memory die 30, so that the BIOS chip 53 can drive the memory die 30 in the chip. When the BIOS chip 53 is connected to the memory connector 51, the BIOS chip 53 may be electrically connected through the trace 15 and the via 16 in the printed circuit board 50.

The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A chip, comprising:

a package substrate having a first surface and a second surface opposite to each other;

at least one memory die disposed on a first side of the package substrate;

a central processor die disposed on a first side of the package substrate; the central processor die is electrically connected with each of the at least one memory die to write data into each memory die or read data from each memory die;

pins for electrically connecting with a printed circuit board are arranged on the second surface of the packaging substrate, and the central processing unit bare chip is also electrically connected with the pins on the second surface.

2. The chip of claim 1, in which the memory die is a DDR memory die.

3. The chip of claim 1, wherein the cpu die and at least one memory die are flip-chip bonded to the package substrate.

4. The chip of claim 1, wherein the central processor die has integrated therein a memory controller electrically connected to the address and data signal bumps in each memory die.

5. The chip of claim 4, wherein the memory controller is electrically connected to the address and data signal bumps in each memory die by traces and vias within the package substrate.

6. The chip of claim 5, wherein the package substrate comprises a first metal layer, a second metal layer, a third metal layer, and a tenth metal layer stacked and insulated from each other;

wherein the central processor die and the at least one memory die are disposed on the first metal layer of the package substrate;

the memory controller is electrically connected with the address and data signal bumps in each memory bare chip through the via holes for connecting the first metal layer and the second metal layer and the wiring in the second metal layer;

the pins are arranged on the tenth metal layer, and the memory controller is electrically connected with the pins through the through holes between the first metal layer and the second metal layer, the wires in the second metal layer and the through holes between the second metal layer and the tenth metal layer.

7. The chip of claim 1, wherein a first plurality of decoupling capacitors are disposed on the first side of the package substrate, each first decoupling capacitor electrically connected to the central processor die and/or the memory die.

8. The chip of claim 7, wherein a second plurality of decoupling capacitors are further disposed on the second side of the package substrate, each second decoupling capacitor being electrically connected to the cpu die and/or the memory die;

and the height of the second decoupling capacitor is not higher than that of the pin.

9. A motherboard, comprising:

a printed circuit board;

the chip of any one of claims 1 to 8 disposed on the printed circuit board, the pins being electrically connected to the printed circuit board.

10. The motherboard of claim 9, wherein the printed circuit board further comprises at least one memory connector and at least one memory bar plugged onto the at least one memory connector, and each memory connector is electrically connected to the cpu die;

the printed circuit board is also provided with a BIOS chip; the BIOS chip is electrically connected with the central processing unit bare chip and each memory connector so as to drive the at least one memory bare chip and the at least one memory bank to work.