CN112381231B

CN112381231B - Quantum topological graph optimization method, device, terminal and storage medium

Info

Publication number: CN112381231B
Application number: CN202011196669.4A
Authority: CN
Inventors: 孔伟成
Original assignee: Benyuan Quantum Computing Technology Hefei Co ltd
Current assignee: Benyuan Quantum Computing Technology Hefei Co ltd
Priority date: 2020-10-31
Filing date: 2020-10-31
Publication date: 2023-10-13
Anticipated expiration: 2040-10-31
Also published as: CN112381231A

Abstract

The application discloses a quantum topology map optimization method, a device, a terminal and a storage medium, which comprise the steps of obtaining a first quantum topology map of a target quantum algorithm, and judging whether a cross connection line and/or a node to be optimized exist in the first quantum topology map; determining intermediate nodes in the first quantum topological graph, reserving connecting lines between the intermediate nodes and other map nodes, acquiring connecting line weights of the connecting lines between the other map nodes, and deleting the connecting lines according to the connecting line weights to obtain a second quantum topological graph which does not contain cross connecting lines; and determining an optimized subgraph consisting of N sub-nodes which are communicated through a connection and correspond to the node to be optimized according to a preset mode, and distributing the connection between the non-optimized node and each sub-node to obtain an optimized quantum topological graph. The application simplifies the depth of the quantum algorithm, improves the fidelity of the quantum algorithm, and enables the complex quantum algorithm to run on the quantum chip.

Description

Quantum topological graph optimization method, device, terminal and storage medium

Technical Field

The application belongs to the field of quantum computing, and particularly relates to a quantum topological graph optimization method, a quantum topological graph optimization device, a terminal and a storage medium.

Background

With the popularization of quantum computing technology, quantum chips for performing quantum computing have become an important object of research. Compared with a traditional integrated chip, the quantum chip has strong parallel computing capability, and the parallel computing capability is exponentially improved along with the number of bits (quantum bit number) of the quantum chip.

The quantum algorithm is a method for carrying out quantum computation which is simulated in a quantum circuit and needs to run on a quantum chip; when quantum algorithms with complex operations are compiled on a quantum chip, the situations of crossing coupling among a plurality of quantum bits (namely two-quantum bit logic gates) and excessive coupling quantity of a plurality of quantum bits and adjacent quantum bits can occur. However, the quantum chips at the present stage all belong to two-dimensional structures, and the coupling between the quantum bits is realized through specific coupling structures (capacitance, inductance, resonant cavity and the like), so that the two coupling structures cannot be crossed; and one qubit is coupled with too many adjacent qubits, so that the regulation and control of the qubit can be greatly reduced, and the accuracy of the executed quantum computation can be greatly reduced. Therefore, some complex quantum algorithms are not efficiently implemented on existing quantum chips of two-dimensional structure.

Disclosure of Invention

The application aims to provide a quantum algorithm optimization method, a device, a terminal and a storage medium, which are used for solving the defects in the prior art, can optimize a complex quantum algorithm, eliminate cross connection lines in a quantum topological graph corresponding to the quantum algorithm, reduce the operation of a switching gate applied in the quantum algorithm as much as possible, simplify the depth of the quantum algorithm, improve the fidelity of the quantum algorithm and enable the complex quantum algorithm to run on a quantum chip with a two-dimensional structure.

The technical scheme adopted by the application is as follows:

according to a first aspect of the present application, there is provided a quantum topology optimization method, the method comprising:

acquiring a first quantum topological graph of a target quantum algorithm, wherein the first quantum topological graph comprises a plurality of spectrum nodes and connecting lines between two spectrum nodes, the spectrum nodes are used for representing logic bits in the target quantum algorithm, and the connecting lines are used for representing quantum bit logic gates between the two logic bits;

judging whether a cross connection line and/or a node to be optimized exist in the first quantum topological graph, wherein the node to be optimized is a graph node with connectivity greater than a connectivity threshold of a quantum chip to be applied in the first quantum topological graph;

If the first quantum topological graph has a cross connection, determining intermediate nodes in the first quantum topological graph, reserving connection lines between the intermediate nodes and other graph nodes, acquiring connection line weights of the connection lines between the other graph nodes, and deleting the connection lines according to the connection line weights of the connection lines between the other graph nodes so as to acquire a second quantum topological graph which does not contain the cross connection lines; if not, updating the first quantum topological graph into a third quantum topological graph;

when the node to be optimized exists in the second quantum topological graph or the third quantum topological graph, determining an optimized sub graph consisting of N sub nodes which are communicated through a connecting line and correspond to the node to be optimized according to a preset mode, wherein the connectivity of all the sub nodes in the optimized sub graph is not greater than the connectivity threshold;

and distributing connecting lines between non-optimized nodes and the child nodes to generate an optimized quantum topological graph, wherein the non-optimized nodes are map nodes except the node to be optimized in the second quantum topological graph or the third quantum topological graph.

Further, the step of determining an intermediate node in the first quantum topology if the first quantum topology has a cross-connect, includes:

Acquiring connectivity, weight and/or dispersity of all map nodes in the first quantum topological graph; the connectivity is the number of the wires connected with each map node, the weight is the sum of the coarseness of all the wires connected with each map node, and the dispersity is the variance of the coarseness of all the wires connected with each map node;

selecting a map node with the maximum connectivity as the intermediate node;

when the connectivity of a plurality of map nodes is the same, selecting the map node with the largest weight as the intermediate node;

and when the connectivity and the weight of the map nodes are the same, selecting the map node with the largest dispersity as the intermediate node.

Further, the connection line in the first quantum topological graph has a roughness, the roughness represents the number of times of applying a qubit logic gate between any two of the logic bits in the quantum algorithm, the step of obtaining the connection line weight of the connection line between each other graph node and deleting the connection line according to the connection line weight of the connection line between each other graph node to obtain a second quantum topological graph without cross connection line further comprises:

Acquiring the link thickness of links between other map nodes in the first quantum topological graph, taking the link thickness as the link weight of the links between other map nodes, and determining the priority of the links between other map nodes according to the link weight of the links between other map nodes;

and determining a to-be-deleted connecting line in the cross connecting lines of the first quantum topological graph according to the priority of the connecting lines among the nodes of the other maps, and deleting the to-be-deleted connecting line to obtain a second quantum topological graph which does not contain the cross connecting line.

Further, the step of determining the connection to be deleted in the intersecting connection of the first quantum topological graph according to the priority of the connection between the nodes of each other graph specifically includes:

when connecting lines between other map nodes with the same priority exist in the cross connecting lines of the first quantum topological graph, determining related nodes corresponding to the connecting lines between the other map nodes with the same priority;

and acquiring the connectivity corresponding to the related nodes, and taking the node connecting line corresponding to the related nodes with high connectivity as the connecting line to be deleted.

Further, the step of determining an optimization sub-graph formed by N sub-nodes which are connected through a connection and correspond to the node to be optimized according to a preset mode includes:

Sequentially increasing one child node until the connectivity of N child nodes in the generated optimized sub-graph is not greater than the connectivity threshold, and connecting the optimized sub-graph with the non-optimized node through a connecting line, wherein N is a positive integer greater than 1.

Further, the step of determining an optimization sub-graph formed by N sub-nodes connected by a connection corresponding to the node to be optimized according to a preset manner further includes:

traversing all connection relations among the N sub-nodes;

and screening out an optimized sub-graph consisting of N sub-nodes which are communicated through connecting lines, wherein no cross connecting line exists in the optimized sub-graph, and the connectivity of all the sub-nodes in the optimized sub-graph is not greater than the connectivity threshold.

Further, the step of obtaining the first quantum topological graph of the target quantum algorithm includes:

acquiring the times of quantum bit logic gates applied to any two logic bits in the target quantum algorithm;

based on the number of the qubit logic gates applied on any two logic bits, a adjacency matrix is obtained and converted into the first quantum topology graph.

A second aspect of the present application provides a quantum topology optimization apparatus, characterized in that the apparatus comprises:

The acquisition module is used for acquiring a first quantum topological graph of a target quantum algorithm, wherein the first quantum topological graph comprises a plurality of spectrum nodes and connecting lines between the two spectrum nodes, the spectrum nodes are used for representing logic bits in the target quantum algorithm, and the connecting lines are used for representing a quantum bit logic gate between the two logic bits;

the judging module is used for judging whether a cross connection line and/or a node to be optimized exist in the first quantum topological graph, wherein the node to be optimized is a graph node with connectivity greater than a connectivity threshold value of a quantum chip to be applied in the first quantum topological graph;

the intersection processing module is used for determining intermediate nodes in the first quantum topological graph, reserving the connection lines between the intermediate nodes and other graph nodes, acquiring the connection line weight of the connection lines between the other graph nodes, and deleting the connection lines according to the connection line weight of the connection lines between the other graph nodes so as to acquire a second quantum topological graph without the intersection connection lines if the first quantum topological graph has the intersection connection lines; if not, updating the first quantum topological graph into a third quantum topological graph;

The determining module is used for determining an optimized sub-graph consisting of N sub-nodes which are communicated through a connecting line and correspond to the node to be optimized according to a preset mode when the node to be optimized exists in the second quantum topological graph or the third quantum topological graph, wherein the connectivity of all the sub-nodes in the optimized sub-graph is not greater than the connectivity threshold;

the generation module is used for distributing connection lines between non-optimized nodes and the child nodes to generate an optimized quantum topological graph, wherein the non-optimized nodes are map nodes except the nodes to be optimized in the second quantum topological graph or the third quantum topological graph.

A third aspect of the application provides a computer terminal comprising a machine-readable storage medium having stored therein a computer program and a processor arranged to run the computer program to perform the quantum topology optimization method of any of the first aspects.

A fourth aspect of the present application provides a computer-readable storage medium having a computer program stored therein, which when executed by a computer, implements the quantum topology optimization method of any one of the first aspects.

Compared with the prior art, the method has the advantages that the first quantum topological graph of the target quantum algorithm is obtained, the first quantum topological graph comprises a plurality of spectrum nodes and connecting lines between the two spectrum nodes, wherein the spectrum nodes are used for representing logic bits in the target quantum algorithm, and the connecting lines are used for representing quantum bit logic gates between the two logic bits; judging whether a cross connection line and/or a node to be optimized exist in the first quantum topological graph, wherein the node to be optimized is a graph node with connectivity greater than a connectivity threshold of a quantum chip to be applied in the first quantum topological graph; if the first quantum topological graph has a cross connection, determining intermediate nodes in the first quantum topological graph, reserving connection lines between the intermediate nodes and other graph nodes, acquiring connection line weights of the connection lines between the other graph nodes, and deleting the connection lines according to the connection line weights of the connection lines between the other graph nodes so as to acquire a second quantum topological graph which does not contain the cross connection lines; if not, updating the first quantum topological graph into a third quantum topological graph; when the node to be optimized exists in the second quantum topological graph or the third quantum topological graph, determining an optimized sub graph consisting of N sub nodes which are communicated through a connecting line and correspond to the node to be optimized according to a preset mode, wherein the connectivity of all the sub nodes in the optimized sub graph is not greater than the connectivity threshold; and distributing connecting lines between non-optimized nodes and the child nodes to generate an optimized quantum topological graph, wherein the non-optimized nodes are map nodes except the nodes to be optimized in the second quantum topological graph or the third quantum topological graph, and optimizing the target quantum algorithm according to the optimized quantum topological graph. The cross connection line in the optimized quantum topological graph corresponds to a coupling structure (capacitance, inductance, resonant cavity and the like) crossed among a plurality of quantum bits on the quantum chip, the quantum chip with a two-dimensional structure cannot be realized, and the optimized quantum topological graph without the cross connection line can be realized on the quantum chip with the two-dimensional structure by optimizing and eliminating the cross connection line; in addition, the frequency of applying the switching gate can be reduced in the implementation process, so that the execution effect of the quantum algorithm is improved; and optimizing nodes to be optimized exceeding the connectivity threshold of the quantum chip to be applied, so that when logic bits in the optimized quantum topological graph are mapped to quantum bits of the quantum chip, the influence of adjacent quantum bits on the quantum bits to be adjusted through a coupling structure is reduced, the fidelity of the quantum algorithm is improved, and the complex quantum algorithm can operate on the quantum chip

Drawings

Fig. 1 is a schematic diagram of a quantum topology diagram corresponding to a conventional quantum algorithm according to an embodiment of the present application;

fig. 2 is a schematic diagram of a quantum topology diagram corresponding to a complex quantum algorithm according to an embodiment of the present application;

fig. 3a and 3b show a schematic diagram of a quantum circuit diagram corresponding to a quantum algorithm and a schematic diagram of a two-dimensional lattice structure of a corresponding quantum chip, respectively;

FIG. 4 is a schematic flow chart of a quantum topology optimization method according to an embodiment of the present application;

fig. 5 shows a schematic diagram of a adjacency matrix corresponding to a quantum algorithm according to an embodiment of the present application;

FIG. 6 is a schematic diagram of an optimized second quantum topology without cross-wires according to an embodiment of the present application;

FIG. 7 is a schematic diagram of obtaining an optimized quantum topology diagram by replying to a deleted link according to an embodiment of the present application;

FIG. 8 is a schematic diagram of an optimization sub-graph consisting of two sub-nodes according to an embodiment of the present application;

FIG. 9 is a schematic diagram of a second quantum topology diagram including nodes to be optimized with high connectivity according to an embodiment of the present application;

FIG. 10 is a schematic diagram of an optimized sub-graph consisting of a plurality of child nodes according to an embodiment of the present application;

11a, 11b, 11c, 11d are schematic diagrams illustrating N node connection lines according to an embodiment of the present application;

FIG. 12 illustrates a schematic diagram of a fourth quantum topology provided by an embodiment of the present application;

fig. 13 is a schematic block diagram of a component structure of a computer terminal for implementing the quantum topology optimization method according to an embodiment of the present application.

Detailed Description

The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the application.

Based on the technical problems known in the prior art, when the quantum algorithm is compiled on the quantum chip, the coupling (namely, the quantum bit logic gate) between a plurality of quantum bits may cross, so that the depth of the quantum algorithm is higher, and the execution effect on the quantum chip with a two-dimensional structure is poor.

For example, referring to fig. 1, a schematic diagram of a quantum topology of a quantum algorithm is shown, which may include a plurality of graph nodes and links between two graph nodes. Wherein, the graph nodes can be used for representing logic bits in a target quantum algorithm, and the connecting lines can be used for representing quantum bit logic gates between two quantum bits. It can be seen that in the quantum topology, there are intersections between many links between the graph nodes 1, 2, 3, 4, 5 and 6.

Fig. 2 shows a quantum topology of a more complex quantum algorithm compared to the quantum topology of the quantum algorithm of fig. 1. That is, when the number of logic bits in the quantum algorithm is large and the number of quantum logic gates to be executed between two logic bits is also large, the quantum topology corresponding to the quantum algorithm is more complex.

The inventor researches and discovers that the quantum chips which can be produced at the present stage belong to middle-small scale chips with noise, and the excessively short quantum state service life and the extremely high error rate can not finish large-scale long-depth operation under the prior art condition. And because the number of bits required by a quantum error correction algorithm (QEC) is too large, the probability of realization in a short period is very small, so that the current quantum calculation can only concentrate on the field without error correction on a small scale. In order to improve the accuracy of the calculation result, the depth of the quantum algorithm needs to be reduced as much as possible.

However, the quantum chip in the related art generally belongs to a two-dimensional structure, and the coupling between the qubits is generally realized through a specific coupling structure (such as capacitance, inductance, resonant cavity, etc.), so that the two coupling structures cannot be crossed in actual implementation, and the cross coupling between logic bits in the quantum algorithm is frequently occurred. Cross-coupling between logic bits in a quantum algorithm needs to be implemented on a quantum chip.

In order to improve the above problems, the inventors have found that, in the course of further studies, a conventional method is currently performed by applying a switching gate to change the mapping relationship between qubits. For example, referring to fig. 2, fig. 3a is a quantum circuit diagram corresponding to a simple quantum algorithm, q1, q2, q3, q4 respectively represent 4 logic bits, and the connection between the logic bits represents two logic bits to which a quantum logic gate needs to be applied; fig. 3b is a two-dimensional lattice structure of a quantum chip corresponding to the quantum algorithm of fig. 3a, Q1, Q2, Q3, Q4 representing quantum bits, and the connection lines between the quantum bits representing a specific coupling structure. Number of logical bits n in a quantum algorithm when executing a quantum program _q And the number of bits n of the quantum chip _Q Obeying n between _q ≤n _Q Each logical bit is mapped onto a qubit. Two logical bits can only be mapped onto two directly connected qubits to perform a two bit gate operation. Otherwise, only switching gates can be used, allowing two logical bits that would otherwise be mapped onto two not directly connected qubits to be remapped onto two directly connected qubits.

Illustratively, in connection with the sequential wiring between Q1, Q2, Q3, Q4 in fig. 3b, a qubit logic gate may be directly applied between Q1 and Q4 in fig. 3a, where a swap gate operation is required to apply a qubit logic gate between Q1 and Q3, such as swapping the positions of Q1 and Q2, and thus applying a qubit logic gate; for another example, a qubit logic gate operation is not possible between q2 and q4, and a swap gate is also applied. It should be noted that the application of the switching gates occurs in pairs, that is, after the application of one switching gate to call the positions of q1 and q2 and the application of the corresponding qubit logic gate, another switching gate needs to be applied to restore the positions of q1 and q 2. Therefore, when the exchange gate is introduced to improve the problem caused by the cross connection of the quantum communication graph, the algorithm depth is increased, and when the number of times of the exchange gate is more, the algorithm running time is obviously prolonged, and a better algorithm execution effect still cannot be achieved.

It should be noted that, in fig. 3b, only the two-dimensional lattice structure of the quantum chip including 4 quantum bits is illustrated, when the number of equivalent quantum bits is large, the number of switching gates to be applied in the quantum algorithm is also greatly increased, so that the complexity of the quantum algorithm is greatly increased, and the fidelity of the calculated result is difficult to be ensured when the subsequent quantum chip runs the quantum algorithm.

It should be added that the number of coupling structures connected to any one qubit on the quantum chip is not infinite, and there is a specific number limit. Because information interaction can be generated between two adjacent quantum bits through a coupling structure, when the coupling structure is connected between one quantum bit and a very large number of adjacent quantum bits, even if two quantum bit logic gates are applied to the quantum bit to be modulated and one of the adjacent quantum bits, other adjacent quantum bits can influence the quantum bit to be modulated through the coupling structure, so that errors occur in the modulation of the quantum bit to be modulated, and quantum algorithms running on the quantum bit to be modulated are influenced, and the fidelity of the quantum algorithms is greatly reduced.

The above prior art solutions have all the drawbacks that the inventors have obtained after they have practiced and studied carefully, and therefore, the discovery process of the above technical problems and the solutions to the problems that the embodiments of the present application hereinafter propose should not be construed as what the inventors have made in the inventive process of the present application.

Based on the technical problems found by the inventor, the embodiment of the application provides an optimization method of a quantum topology graph, which aims at improving cross connection lines and/or nodes to be optimized existing in the quantum topology graph of a conventional quantum algorithm. When a first quantum topological graph corresponding to an equivalent sub-algorithm has a cross connection, determining intermediate nodes in the first quantum topological graph, reserving connection lines between the intermediate nodes and other graph nodes, acquiring connection line weights of the connection lines between the other graph nodes, and deleting the connection lines according to the connection line weights of the connection lines between the other graph nodes so as to acquire a second quantum topological graph which does not contain the cross connection lines; if not, updating the first quantum topological graph into a third quantum topological graph; when the node to be optimized exists in the second quantum topological graph or the third quantum topological graph, determining an optimized sub graph consisting of N sub nodes which are communicated through a connecting line and correspond to the node to be optimized according to a preset mode, wherein the connectivity of all the sub nodes in the optimized sub graph is not greater than the connectivity threshold; and distributing connecting lines between non-optimized nodes and the child nodes to generate an optimized quantum topological graph, wherein the non-optimized nodes are map nodes except the node to be optimized in the second quantum topological graph or the third quantum topological graph. Or may take the form of: when a first quantum topological graph corresponding to the equivalent sub-algorithm has cross connection lines, determining intermediate nodes in the first quantum topological graph, and reserving connection lines between the intermediate nodes and other map nodes to obtain a second quantum topological graph without the cross connection lines; if not, updating the first quantum topological graph into a third quantum topological graph; when the node to be optimized exists in the second quantum topological graph or the third quantum topological graph, determining an optimization subgraph consisting of N sub-nodes which are communicated through a connecting line and correspond to one node to be optimized according to a preset mode; distributing the connection lines between the non-optimized nodes and the child nodes to obtain a fourth quantum topological graph; and recovering the connection lines between the non-optimized nodes in the fourth quantum topological graph to obtain an optimized quantum topological graph. Therefore, when the optimized quantum topological graph without the cross connection lines is realized on the quantum chip with the two-dimensional structure, the depth of the quantum algorithm can be effectively shortened, the running time of the quantum algorithm can be reduced, and the frequency of applying the exchange gate can be reduced in the realization process; and by optimizing the nodes to be optimized exceeding the connectivity threshold of the quantum chip to be applied, when the logic bits in the optimized quantum topological graph are mapped to the quantum bits of the quantum chip, the influence of adjacent quantum bits on the quantum bits to be adjusted through the coupling structure is reduced, and the fidelity of the quantum algorithm is greatly improved.

Some exemplary implementations of the quantum connectivity graph cross-connect processing method described above are described in detail below in conjunction with the accompanying drawings.

Referring to fig. 4, a flow chart of a method for optimizing a quantum topology according to an embodiment of the present application is shown, including:

step S110, a first quantum topology diagram of a target quantum algorithm is acquired.

In this embodiment, the first quantum topology graph may include a plurality of graph nodes and a connection line between two graph nodes, where the graph nodes may be used to represent logic bits in the target quantum algorithm, and the connection line is used to represent a quantum bit logic gate between two quantum bits.

The quantum connectivity map may be obtained based on the number of logical bits in the target quantum algorithm and the number of qubit logic gates applied on any two qubits. Among them, qubits may refer to a physical system that may be in the ground state |0>, the excited state |1>, and the superimposed state (α|0> +β|1 >) at the same time. Mathematically, a qubit can be represented by a state vector over the hilbert space. Quantum circuits are implemented by manipulating several qubits simultaneously.

Quantum circuits are a representation of quantum programs, which may consist of a series of qubits initially in the |0> state followed by a number of quantum logic gates, ending with a measurement operation (not necessarily every bit needs to be measured). In general, each quantum program can be ultimately decomposed into a quantum program consisting of only a basic sequence of quantum logic gates. In addition, the qubit logic gate may refer to some reversible unitary transformations, which may be used to manipulate a number of qubits, so that the qubits evolve toward a target state, and the final state of evolution is the result of quantum computation.

And step S120, judging whether a cross connection line and/or a node to be optimized exist in the first quantum topological graph.

For example, in some possible examples, it may be detected whether the first quantum topology is a planable graph, i.e. whether there are crossing points between the individual wires in the first quantum topology. When any two connecting lines have crossing points, the first quantum topological graph can be judged to have crossing connecting lines; when no cross point exists among all the connecting lines, the fact that the cross connecting lines exist in the quantum communication map can be judged.

Detecting whether spectrum nodes with connectivity greater than the connectivity threshold of the quantum chip to be applied exist in the first quantum topological graph or not, namely detecting the connection line number of each spectrum node connection; it should be noted that, the connectivity threshold of the quantum chip to be applied is determined according to the parameters of the fidelity of the quantum algorithm, for example, the fidelity requirement of the quantum algorithm at the present stage is not less than 97%, and by calculating the influence factor of each adjacent quantum bit on the quantum bit to be modulated through the coupling structure, the number of adjacent quantum bits that can be connected on the quantum bit to be modulated, that is, the connectivity threshold, can be determined. In the embodiment of the present invention, the connectivity threshold may be preset to 4. And when a graph node with connectivity larger than the connectivity threshold exists in the first quantum topological graph, defining the graph node as a node to be optimized.

Step S130, if the first quantum topological graph has a cross connection, determining intermediate nodes in the first quantum topological graph, reserving connection lines between the intermediate nodes and other graph nodes, acquiring connection line weights of the connection lines between the other graph nodes, and deleting the connection lines according to the connection line weights of the connection lines between the other graph nodes so as to acquire a second quantum topological graph without the cross connection lines; if not, updating the first quantum topological graph into a third quantum topological graph;

when the first quantum topological graph has the cross connection, the intermediate nodes in the first quantum topological graph are determined, the connection between the intermediate nodes and other graph nodes is reserved, then the connection weight of the connection between the other graph nodes is calculated, and the connection with low connection weight is preferentially deleted according to the connection weight, so that a second quantum topological graph which does not contain the cross connection is obtained. The connection weight is the thickness of the connection, the thickness represents the number of times of the applied quantum bit logic gate between any two logic bits in the quantum algorithm, and the larger the thickness is, the more times of the applied quantum bit logic gate are represented on the corresponding map node.

Or may take the form of: determining intermediate nodes in the first quantum topological graph, and reserving connecting lines between the intermediate nodes and other graph nodes to obtain a second quantum topological graph which does not contain cross connecting lines; if not, updating the first quantum topological graph into a third quantum topological graph.

When the first quantum topological graph is not a planar graph, the situation that cross connection exists in the quantum communication graph, namely cross coupling needs to be achieved in the corresponding quantum chip structure is indicated, and the actual quantum chip structure is a two-dimensional lattice structure and is a specific structure corresponding to the fact that cross coupling between quantum bits cannot be achieved. In the related art, no optimization is adopted for the cross connection line, namely, the two-dimensional lattice structure of the quantum chip is not changed in the subsequent process of running the quantum algorithm through the quantum chip, but the mapping relation between the quantum bits is changed by applying the switching gate, so that the algorithm depth is increased and the algorithm running time is increased when the number of applied switching gates is excessive.

In this embodiment, when the first quantum topology graph has the cross-connection, the second quantum topology graph that does not include the cross-connection is obtained by determining the intermediate node in the first quantum topology graph and reserving the connection between the intermediate node and the other graph nodes.

For example, in some possible examples, in determining an intermediary node in a first quantum topology graph, the intermediary node may represent a highest priority graph node in the first quantum topology graph, such that the highest priority graph node in the first quantum topology graph may be selected as the intermediary node, and the priority may be calculated in combination with a node value of the graph node in the first quantum topology graph.

For another example, in the process of preserving the connection lines between the intermediate node and the other graph nodes, the connection lines between the other graph nodes except the intermediate node may be selected to be deleted, and in particular, all the connection lines between the other graph nodes may be deleted, or only the cross connection lines between the other graph nodes may be deleted.

And step S140, when the node to be optimized exists in the second quantum topological graph or the third quantum topological graph, determining an optimized sub graph consisting of N sub nodes which are communicated through a connecting line and correspond to the node to be optimized according to a preset mode, wherein the connectivity of all the sub nodes in the optimized sub graph is not greater than the connectivity threshold.

The nodes to be optimized can be processed after the nodes to be optimized which need to be optimized are determined by detecting the connection line number of the nodes connected with each map in the second quantum topological graph or the third quantum topological graph; specifically, for a node to be optimized, the node to be optimized is converted into an optimized subgraph composed of a plurality of sub-nodes connected by connecting lines, the sub-nodes are equivalent to the action of map nodes in the second quantum topological graph or the third quantum topological graph, represent a logic bit, and are connected by connecting lines. And connecting the connecting lines originally connected with the nodes to be optimized through the optimization subgraph.

It is conceivable that, for the node to be optimized, the number of connected wires exceeds the connectivity threshold of the quantum chip, and after the wires connected with the node to be optimized are distributed to each sub-node in the optimization subgraph, the number of connected wires on each sub-node is obviously reduced compared with the number of wires connected with the node to be optimized. Therefore, the number N of the proper child nodes is determined, an optimized sub-graph consisting of N child nodes is formed, the child nodes in the optimized sub-graph replace nodes to be optimized to be connected with other graph nodes, and the connectivity of all the child nodes in the optimized sub-graph after replacement is not greater than a connectivity threshold value. The connectivity of the nodes to be optimized in the second quantum topological graph or the third quantum topological graph is effectively reduced, so that the corresponding optimized topological graph can be realized on a quantum chip.

And step S150, distributing connection lines between non-optimized nodes and the child nodes to generate an optimized quantum topological graph, wherein the non-optimized nodes are map nodes except the node to be optimized in the second quantum topological graph or the third quantum topological graph.

And after determining the nodes to be optimized which need to be optimized by detecting the connection line number of each graph node in the second quantum topological graph or the third quantum topological graph, defining the graph nodes except the nodes to be optimized as non-optimized nodes, namely, not needing to be optimized.

After an optimization sub-graph formed by N sub-nodes which are communicated through connecting lines and correspond to the node to be optimized is determined in a preset mode, the node to be optimized needs to be replaced by the optimization sub-graph, and the connecting lines which are originally connected with the node to be optimized need to be connected to the sub-nodes of the optimization sub-graph one by one, so that the quantum algorithm can effectively realize interaction between two logic bits, namely a quantum logic gate is applied. Therefore, the weight of the connecting lines between other map nodes is determined preferentially, the deleting priority between the connecting lines is determined, the distribution time of the connecting lines is shortened, and the optimization efficiency is improved.

As described above, the coarseness represents the number of applied qubit logic gates between any two of the logic bits in the quantum algorithm. The larger the thickness, the larger the link weight, the higher the corresponding priority. And when the cross connection line of the first quantum topological graph is determined, acquiring priority low and deleting preferentially, wherein the priority deleting is small in thickness and small in connection line weight. In this embodiment, the connection lines between the other map nodes are preferentially deleted, and the connection lines between the intermediate node and the other map nodes are preferentially reserved.

When a plurality of connecting lines with the same weight priority exist, in order to further avoid node optimization caused by high connectivity, the connecting lines corresponding to other map nodes with high connectivity are preferentially deleted.

Corresponding to the scheme: determining intermediate nodes in the first quantum topological graph, and reserving connecting lines between the intermediate nodes and other graph nodes to obtain a second quantum topological graph which does not contain cross connecting lines; if not, updating the first quantum topological graph into a third quantum topological graph. The method can also adopt the following scheme: distributing the connection lines between the non-optimized nodes and the child nodes to obtain a fourth quantum topological graph; the non-optimized nodes are map nodes except the nodes to be optimized in the second quantum topological graph or the third quantum topological graph.

That is, the scheme further generates a fourth quantum topology graph so as to further recover the connection after deleting the connection between the nodes.

The step of distributing the connection lines between the non-optimized node and each sub-node to obtain a fourth quantum topological graph further comprises the following steps: and recovering the connection lines between the non-optimized nodes in the fourth quantum topological graph to obtain an optimized quantum topological graph.

When the cross connection line in the first quantum topological graph is optimized, the connection lines among other graph nodes except the intermediate node are deleted, namely paths for directly applying quantum logic gates among other graph nodes to carry out quantum algorithm are disconnected; in this case, when the quantum logic gate needs to be applied between other spectrum nodes to perform the quantum algorithm, the quantum logic gate needs to be applied to perform the operation only after the exchange gate is applied through the intermediate node.

Therefore, after the fourth quantum topological graph is obtained by optimizing the nodes to be optimized and distributing the connection relation between the non-optimized nodes and the child nodes, the connection line between the non-optimized nodes in the fourth quantum topological graph can be restored, so that the quantum bit logic gate operation can be directly applied between the two map nodes corresponding to the restored connection line, the defects of increasing the depth of a quantum algorithm and prolonging the quantum operation time caused by applying a switching gate are avoided, and the fidelity of the quantum algorithm can be improved. It is to be added that non-optimized nodes in the fourth quantum topological graph correspond to other map nodes except intermediate nodes in the first quantum topological graph; and when restoring the connection between the non-optimized nodes in the fourth quantum topological graph, the rule that the cross connection cannot occur needs to be followed, namely, the cross connection does not exist in the optimized quantum topological graph.

In this way, the cross connection line is eliminated through optimization, so that the optimized quantum topological graph which does not contain the cross connection line can be realized on a quantum chip with a two-dimensional structure; and the nodes with node connectivity greater than the connectivity threshold of the quantum chip in the quantum topology graph are optimized, so that one quantum bit and as few adjacent quantum bits as possible execute two-quantum bit logic gates, the influence of the two-quantum bit logic gates applied on a plurality of quantum bits on the quantum bit is reduced, the regulation precision of the quantum bit is improved, the effect of the two-quantum bit logic gates applied on a single quantum bit in the quantum algorithm can accurately run on the quantum chip, and further the complex quantum algorithm is realized on the quantum chip.

In one possible implementation manner, in the process of obtaining the first quantum topological graph of the target quantum algorithm, the logic bits in the quantum algorithm and the times of the quantum bit logic gates applied to any two logic bits can be obtained, then, based on the times of the quantum bit logic gates applied to any two quantum bits, an adjacency matrix can be obtained, as shown in fig. 5, wherein the values 0 and 1 … 6 of the horizontal axis and the vertical axis represent the logic bits in the target quantum algorithm, and the values of the crossing positions of the horizontal axis and the vertical axis represent the times of the quantum logic gates applied to the corresponding two logic bits; further, the adjacent matrix is converted into a first quantum topology map, wherein the first quantum topology map corresponding to the adjacent matrix of fig. 5 is shown in fig. 1.

However, in one possible implementation, a plurality of qubit logic gates are applied between two logic bits in succession, and when the number of statistics obtains the adjacency matrix, the number of qubit logic gates applied between the two logic bits may be counted only once. Because the first qubit logic gate between the two qubits can be applied, the subsequent successive qubit logic gates can be applied directly without applying any swap gate operation.

Continuing back to the first quantum topology shown in fig. 1, it can be found that the wire has a thickness representing the number of applied qubit logic gates between any two of the logic bits in the quantum algorithm, i.e. the corresponding values in the adjacency matrix in fig. 5.

In one possible embodiment, the inventors found during the research that, given the different value of each graph node in the first quantum topology graph, in optimizing the cross-connect line, it is necessary to avoid modifying the high value graph node in the first quantum topology graph as much as possible, otherwise, excessive switching operations may be introduced in the following process. Based on this, for step S130, this may be achieved by the following exemplary sub-steps, described in detail below.

Acquiring connectivity, weight and/or dispersity of all map nodes in the first quantum topological graph; the intermediary nodes are determined based on connectivity, weight, and/or dispersion.

In the first quantum topological graph, connectivity is the number of wires connected with each spectrum node, weight is the sum of the coarseness of all wires connected with each spectrum node, and dispersity is the variance of the coarseness of all wires connected with each spectrum node. After connectivity, weight, and/or dispersion of all map nodes in the first quantum topology map are obtained, intermediary nodes may be determined based on connectivity, weight, and/or dispersion. Exemplary steps are as follows:

and selecting the map node with the largest connectivity as the intermediate node.

As shown in fig. 1 or fig. 2, the connectivity measures the interaction relationship between two spectrum nodes, so that the greater the connectivity, the higher the value of the spectrum node in the quantum algorithm, and when optimizing the intersection line in the first quantum topological graph, the node needs to be selected as an intermediate node, and the intermediate node is reserved.

And when the connectivity of a plurality of map nodes is the same, selecting the map node with the largest weight as the intermediate node.

The inventor finds that under certain specific situations, the connectivity of a plurality of spectrum nodes in the first quantum topological graph may be the same, for example, when the connectivity of 6 logic bits in fig. 1 is 5, the sum of the times of applying the quantum bit logic gates to the adjacent spectrum nodes needs to be calculated by means of the weight parameter of the spectrum node, namely, the spectrum node with the largest connectivity.

Further, the inventor also found that in another specific case, the connectivity and the weight of the map nodes may be the same, and on this basis, the intermediate nodes need to be determined by further combining the dispersity of the map nodes.

If the first quantum topology represented in fig. 1 is taken as an example, when the intermediate nodes in the first quantum topology are determined to be map nodes 6 through the above exemplary steps, the intersecting lines in the first quantum topology may be optimized based on the intermediate nodes.

And reserving connecting lines between the intermediate nodes and other map nodes, and deleting the connecting lines between the other map nodes except the intermediate nodes to obtain a second quantum topological graph which does not contain cross connecting lines.

As shown in fig. 6, when the graph node 6 in fig. 1 is determined to be an intermediate node through the above-described exemplary steps, the connection lines between the graph node 6 and the graph nodes 1, 2, 3, 4, and 5 may be reserved, and the connection lines between the graph nodes 1, 2, 3, 4, and 5 other than the peripheral connection lines may be deleted, so as to obtain a second quantum topology map not including the cross connection lines, that is, the second quantum topology map shown in fig. 6.

In another possible example, the inventor considers that some other graph nodes do not have cross-links, so as to keep more links as much as possible, and thus reduce subsequent switch gate operations, and can selectively recover the links between other graph nodes except for the intermediate node. The method comprises the following specific steps:

and sequentially selecting the deleted connecting lines according to the sequence from the large roughness to the small roughness, and filling back the fourth quantum topological graph.

As described above, the coarseness represents the number of times of the logic gates of the qubit applied between any two logic bits in the quantum algorithm, and the larger the coarseness is, the more the number of times of the logic gates of the qubit applied on the corresponding map node is, and the higher the value in the fourth quantum topology map is, so when restoring the deleted connection lines, the deleted connection lines need to be sequentially selected according to the order from the larger coarseness to the smaller coarseness, and the fourth quantum topology map needs to be filled.

Checking whether a cross connection line exists in the fourth quantum topological graph after updating according to the connection line selected currently after filling the fourth quantum topological graph, and if so, recording the fourth quantum topological graph before updating as the optimized quantum topological graph; and if not, recording the updated fourth quantum topological graph as the optimized quantum topological graph.

As shown in fig. 7, when restoring the deleted connection line, it needs to check whether there is a cross connection line in the fourth quantum topology, if there is a cross connection line in the fourth quantum topology after restoring a certain connection line, the connection line needs to be abandoned and cannot be filled back into the fourth quantum topology.

By optimizing the cross-connection line existing in the first quantum topology, a second quantum topology as shown in fig. 6 is obtained, and it can be found that the connectivity of the graph node 6 in fig. 6 is 5, and the connectivity threshold of the quantum chip (i.e. the value 4 described above) has been exceeded, so that optimization of the graph node exceeding the connectivity threshold is also required.

As further shown in fig. 6, in one possible implementation manner, for the second quantum topological graph, only the connection between the intermediate node and other spectrum nodes is reserved, that is, the connectivity of the other spectrum nodes is 1, and when determining the intermediate node, the spectrum node with the highest connectivity is selected as the intermediate node, so that when determining the node to be optimized, it is first required to determine whether the intermediate node is the node to be optimized.

In one possible implementation manner, the inventor finds that the node to be optimized in the second quantum topological graph or the third quantum topological graph can be replaced by an optimization sub graph consisting of N sub nodes to be connected with other graph nodes, so that the connectivity of the node to be optimized in the second quantum topological graph or the third quantum topological graph is effectively reduced.

In one possible implementation manner, one sub-node is sequentially increased until the connectivity of N sub-nodes in the generated optimized sub-graph is not greater than the connectivity threshold, and the optimized sub-graph is connected with the non-optimized node through a connection line, where N is a positive integer greater than 1.

Taking fig. 6 as an example, the connectivity of the graph nodes 6 is greater than the connectivity threshold, and the graph nodes 1, 2, 3, 4 and 5 are determined to be nodes to be optimized, and all the rest are non-optimized nodes. In the implementation, each time a child node is incremented, namely, first, an optimized sub-graph of 2 child nodes connected through a connection line is generated for one node to be optimized, as shown in fig. 8.

In fig. 8, the optimization subgraph is composed of child nodes 7 and 8, and at this time, the connection lines of the other graph nodes 1, 2, 3, 4 and 5 with the nodes to be optimized are connected to the optimization subgraph, that is, the connection lines of the child nodes 7 and 8 with the graph nodes 1, 2, 3, 4 and 5 are distributed according to 2 and 3 or 3 and 2, so that the connectivity of the child nodes is not greater than the connectivity threshold.

Fig. 8 illustrates, as one possible embodiment, only a second quantum topology or a third quantum topology of 6 logical bit compositions. In another possible example, if the number of logical bits is greater, and the connectivity of the node to be optimized is greater than the connectivity threshold, only one child node is added, so that the connectivity of the node to be optimized cannot be reduced below the connectivity threshold, and a plurality of child nodes need to be added.

With reference to fig. 9, it is expected that adding one child node to form an optimized sub-graph cannot ensure that the connectivity of the generated child node is not greater than the connectivity threshold, 1, 2, 3 or more child nodes need to be added in sequence to form the optimized sub-graph, and in the adding process, it is further required to determine whether the connectivity of the child nodes in the optimized sub-graph after adding one child node at a time is not greater than the connectivity threshold. Through the mode of sequentially increasing one child node, an optimized subgraph meeting the connectivity threshold requirement is finally obtained, and the number N of the child nodes can be guaranteed to be in accordance with the requirement and minimum. Wherein, for the second quantum topological graph or the third quantum topological graph, the number of times of switching gates applied between non-optimized nodes needs to be increased, and the more the number of sub-nodes are increased, the more the number of times of corresponding switching gates is increased. The number N of the sub-nodes in the optimized sub-graph is determined in a sequential increasing mode, so that the number N of the sub-nodes is guaranteed to be the smallest and meets the requirement, and the running time of the quantum algorithm is prevented from being prolonged due to the fact that a great number of switching gates are increased. In another possible embodiment, a further method for determining the number N of sub-nodes in an optimized sub-graph is provided. And calculating the number N of the child nodes corresponding to the node to be optimized based on a preset formula. The formula is as follows:

Wherein X represents a connectivity threshold, d represents connectivity of the node to be optimized, N is the number of child nodes, and k is a constant.

Taking fig. 9 as an example, the node to be optimized is a graph node 8, and n=2.33 can be calculated by removing the constant 1 from k by using the above formula. In the implementation, N is a positive integer, so N is a value of 3, and the number of child nodes corresponding to the node 8 to be optimized can be 3. The resulting optimized sub-graph consisting of 3 child nodes is shown in fig. 10.

Based on the above example, after the number N of sub-nodes in the optimized sub-graph is determined, the connection relationship between the N sub-nodes needs to be further determined, and the connectivity of the N sub-nodes may be different according to the connection relationship.

Specifically, the method for determining the connection relationship between the N sub-nodes connected by the connection line includes the following steps:

traversing all connection relations among the N sub-nodes.

As shown in fig. 11, taking the optimization sub-graph in fig. 10 as an example, the optimization sub-graph includes 3 sub-nodes, and then the connection relationships between the corresponding 3 sub-nodes are shown in fig. 11a, 11b, 11c, and 11 d. For different connection relations, after all the child nodes in the optimized sub-graph are connected with non-optimized nodes, the connectivity of all the child nodes is different, so that after the number N of specific child nodes is determined, the connection relations of the N child nodes need to be traversed, and all the connection relations are listed.

And screening out an optimized subgraph consisting of N child nodes communicated through the connecting lines.

After the connection relation among the N sub-nodes is determined through traversal, the connection mode which meets the requirement, namely that the connectivity of all the sub-nodes is not larger than the connectivity threshold value, and meanwhile cross connection lines in the optimized sub-graph is avoided.

After the connection relations of the N sub-nodes in the optimized sub-graph are determined, the connection relations between the N sub-nodes and the non-optimized nodes are not determined, and the connection lines between the non-optimized nodes and the sub-nodes in the optimized sub-graph are required to be distributed. The specific steps are as follows:

obtaining a coupling strength matrix and a distance matrix of each non-optimized node; the sum of the number of the quantum bit logic gates applied between two non-optimized nodes of the first quantum topological graph and the number of the switching gates added after the non-optimized nodes are connected with the sub-nodes can be used for representing the value of the non-optimized nodes in the first quantum topological graph; the distance matrix characterizes distances between the non-optimized node and each of the child nodes.

For example, in one possible implementation, in the first quantum topology graph, when the non-optimized node is directly connected to the node to be optimized (i.e., the intermediate node), and the non-optimized node is optimized into the optimized sub-graph including the sub-nodes, the two non-optimized nodes that are originally connected to the same graph node (to be optimized) are equivalent to each other, and when the non-optimized nodes are connected to different sub-nodes in the optimized sub-graph, a switch gate operation needs to be applied. Thus, a coupling strength matrix I of two non-optimized nodes is obtained _ml Not only is the number of times W of application of the qubit logic gates of the two non-optimized nodes in the first quantum topology diagram obtained _ml It is also necessary to obtain the number S of switch gates added after the two non-optimized nodes are connected to the child nodes in the optimized subgraph _ml . Specific:

I _ml ＝αW _ml +(1-α)S _ml

where α is the combining weight, taking a constant value, such as 0.5.

Taking the second quantum topology shown in FIG. 10 as an example, except for calculating the coupling strength matrix I of non-optimized nodes _ml Distance matrix D of non-optimized nodes is also calculated _mi Specifically, distances between the non-optimized node 1 and the child nodes 9, 10 and 11 are calculated respectively, and a distance matrix of 3 distance values is formed. Wherein m and l represent non-optimized nodes and can be positive integers of 1-7; i represents a child node and may be a positive integer from 9 to 11.

And obtaining the weighted distance between the non-optimized node and each child node based on the coupling strength matrix and the distance matrix.

For any non-optimized node, the corresponding coupling strength matrix I can be calculated _ml And D _mi The weighted distance between any non-optimal node and each child node may be obtained.

Taking fig. 10 as an example, when the weighting of non-optimal node 1 needs to be calculated When the distance is kept, respectively calculating the coupling strength matrix I of the non-optimized node 1, the non-optimized point 2, the non-optimized point 3, the non-optimized point 4, the non-optimized point 5, the non-optimized point 6 and the non-optimized point 7 ₁₂ 、I ₁₃ 、I ₁₄ 、I ₁₅ 、I ₁₆ 、I ₁₇ In the calculation of distance matrix D between non-optimized node 1 and sub-node 9, sub-node 10 and sub-node 11 respectively ₁₉ 、D ₁ ₁₀ 、D ₁ ₁₁ 。

When the weighted distance of the non-optimized node 2 needs to be calculated, the coupling strength matrix I of the non-optimized node 2 and the non-optimized point 1, the non-optimized point 3, the non-optimized point 4, the non-optimized point 5, the non-optimized point 6 and the non-optimized point 7 are calculated respectively ₂₁ 、I ₂₃ 、I ₂₄ 、I ₂₅ 、I ₂₆ 、I ₂₇ In the calculation of distance matrix D between non-optimized node 2 and sub-node 9, sub-node 10 and sub-node 11 respectively ₂₉ 、D ₂ ₁₀ 、D ₂ ₁₁ . The method for calculating the weighted distance L of other non-optimized nodes is the same and will not be described in detail.

And sequentially distributing and connecting the non-optimized nodes to the child nodes with the smallest weighting distances according to the sequence from the big coupling strength matrix to the small coupling strength matrix of the non-optimized nodes.

Taking the second quantum topology diagram shown in fig. 10 as an example, the connection relationship shown in fig. 11a is adopted by traversing the connection relationship between the 3 selected child nodes. Obtaining a coupling strength matrix I of 7 non-optimized nodes _ml 、I _m2 、I _m3 、I _m4 、I _m5 、I _m6 、I _m7 And obtain a ranking from big to small: i _ml >I _m6 >I _m3 >I _m2 >I _m7 >I _m5 >I _m4 。

According to the sequence of the coupling strength matrix, firstly, the non-optimized node 1 is distributed, the weighted distances L19, L10 and L111 of the non-optimized node 1 and the sub-nodes 9, 10 and 11 are calculated through a weighted distance formula, and the sub-node with the minimum weighted distance value is determined to be connected with the non-optimized node 1; similarly, the weighted distances between the node and the sub-node 9, the sub-node 10 and the sub-node 11 are calculated for other non-optimal nodes according to the sequence of the coupling strength matrix from large to small, and the node with the smallest weighted distance is connected.

It should be added that, after a child node is connected to a non-optimized node, the current connectivity of the child node will increase by 1, when the connectivity of the child node reaches the connectivity threshold, when calculating the weighted distance of the node to be optimized, it is not necessary to calculate the weighted distances between other nodes to be optimized and the child node, and only the weighted distances between other nodes to be optimized and other child nodes except the child node need to be calculated, and the minimum value is selected. Fig. 12 is an effect diagram after assignment to nodes to be optimized in the second quantum topology or the third quantum topology of fig. 10.

Based on the same inventive concept, the embodiment of the application provides a quantum topological graph optimizing device, and the embodiment can divide functional modules of the quantum topological graph optimizing device according to the embodiment of the method executed by the computer terminal. For example, each functional module may be divided corresponding to each function, or two or more functions may be integrated in one processing module. The integrated modules may be implemented in hardware or in software functional modules. It should be noted that, in the embodiment of the present application, the division of the modules is schematic, which is merely a logic function division, and other division manners may be implemented in actual implementation. For example, in the case of dividing each functional module by the corresponding function, the quantum topology optimization apparatus in the present embodiment is only one apparatus schematic diagram. The quantum topology optimization device may include an acquisition module, a judgment module, a cross processing module, a determination module, an allocation module and a recovery module, and the functions of each functional module of the quantum topology optimization device are respectively described in detail below.

The device comprises an acquisition module, a logic bit acquisition module and a quantum bit logic gate acquisition module, wherein the acquisition module is used for acquiring a first quantum topological graph of a target quantum algorithm, the first quantum topological graph comprises a plurality of spectrum nodes and a connecting line between two spectrum nodes, the spectrum nodes are used for representing logic bits in the target quantum algorithm, and the connecting line is used for representing a quantum bit logic gate between two logic bits. It is understood that the acquisition module may be used to perform step S110 described above.

The judging module is used for judging whether a cross connection line and/or a node to be optimized exist in the first quantum topological graph, wherein the node to be optimized is a graph node with connectivity greater than a connectivity threshold value of a quantum chip to be applied in the first quantum topological graph. It will be appreciated that the determination module may be used to perform step S120 described above, and reference may be made to the details of implementation of the determination module 112 regarding step S120 described above.

The intersection processing module is used for determining intermediate nodes in the first quantum topological graph, reserving the connection lines between the intermediate nodes and other graph nodes, acquiring the connection line weight of the connection lines between the other graph nodes, and deleting the connection lines according to the connection line weight of the connection lines between the other graph nodes so as to acquire a second quantum topological graph without the intersection connection lines if the first quantum topological graph has the intersection connection lines; if not, updating the first quantum topological graph into a third quantum topological graph. It will be appreciated that the cross-processing module may be used to perform step S130 described above, and reference may be made to the details of step S130 regarding the implementation of the cross-processing module.

The determining module is used for determining an optimized sub-graph formed by N sub-nodes which are communicated through a connecting line and correspond to the node to be optimized according to a preset mode when the node to be optimized exists in the second quantum topological graph or the third quantum topological graph, wherein the connectivity of all the sub-nodes in the optimized sub-graph is not greater than the connectivity threshold. It will be appreciated that the determination module may perform step S140 described above, and reference may be made to the details of step S140 for detailed implementation of the determination module

The generation module is used for distributing connection lines between non-optimized nodes and the child nodes to generate an optimized quantum topological graph, wherein the non-optimized nodes are map nodes except the nodes to be optimized in the second quantum topological graph or the third quantum topological graph. It will be appreciated that the allocation module may be used to perform step S150 described above, and reference may be made to the details of step S150 regarding the implementation of the allocation module.

Based on the same inventive concept, the embodiment of the application also provides a computer terminal for executing the quantum topology optimization method, which can comprise a quantum topology optimization device, a machine-readable storage medium and a processor.

In this embodiment, the machine-readable storage medium and the processor are both located in the computer terminal and are separately provided. However, it should be understood that the machine-readable storage medium may also be separate from the computer terminal and accessible by the processor through the bus interface. In the alternative, the machine-readable storage medium may be integral to the processor, such as a cache and/or general purpose registers.

The quantum topology optimization apparatus may include software functional modules (e.g., an acquisition module, a determination module, a cross-processing module, a determination module, an allocation module, and a recovery module) stored on a machine-readable storage medium, which when executed by a processor, implement the quantum topology optimization method provided by the foregoing method embodiments.

Because the computer terminal provided in the embodiment of the present application is another implementation form of the quantum topology optimization method embodiment executed by the computer terminal, and the computer terminal may be used to execute the quantum topology optimization method provided in the method embodiment, the technical effects that can be obtained by the computer terminal may refer to the method embodiment and will not be described herein.

Compared with the prior art, the method has the advantages that compared with the prior art, the first quantum topological graph of the target quantum algorithm is obtained, the first quantum topological graph comprises a plurality of spectrum nodes and connecting lines between the two spectrum nodes, wherein the spectrum nodes are used for representing logic bits in the target quantum algorithm, and the connecting lines are used for representing quantum bit logic gates between the two logic bits; judging whether a cross connection line and/or a node to be optimized exist in the first quantum topological graph, wherein the node to be optimized is a graph node with connectivity greater than a connectivity threshold of a quantum chip to be applied in the first quantum topological graph; if the first quantum topological graph has the cross connection line, determining intermediate nodes in the first quantum topological graph, and reserving connection lines between the intermediate nodes and other graph nodes to obtain a second quantum topological graph which does not contain the cross connection line; if not, updating the first quantum topological graph into a third quantum topological graph; when the node to be optimized exists in the second quantum topological graph or the third quantum topological graph, determining an optimized sub graph consisting of N sub nodes which are communicated through a connecting line and correspond to the node to be optimized according to a preset mode, wherein the connectivity of all the sub nodes in the optimized sub graph is not greater than the connectivity threshold; distributing the connection lines between the non-optimized nodes and the child nodes to obtain a fourth quantum topological graph; the non-optimized nodes are map nodes except the nodes to be optimized in the second quantum topological graph or the third quantum topological graph; and recovering connecting lines between non-optimized nodes in the fourth quantum topological graph to obtain an optimized quantum topological graph, and optimizing the target quantum algorithm according to the optimized quantum topological graph. The cross connection line in the optimized quantum topological graph corresponds to a coupling structure (capacitance, inductance, resonant cavity and the like) crossed among a plurality of quantum bits on the quantum chip, the quantum chip with a two-dimensional structure cannot be realized, and the optimized quantum topological graph without the cross connection line can be realized on the quantum chip with the two-dimensional structure by optimizing and eliminating the cross connection line; in addition, the frequency of applying the switching gate can be reduced in the implementation process, so that the execution effect of the quantum algorithm is improved; and by optimizing the nodes to be optimized exceeding the connectivity threshold of the quantum chip to be applied, when the logic bits in the optimized quantum topological graph are mapped to the quantum bits of the quantum chip, the influence of adjacent quantum bits on the quantum bits to be adjusted through the coupling structure is reduced, and the fidelity of the quantum algorithm is greatly improved.

The foregoing detailed description of the construction, features and advantages of the invention will be presented based on the embodiments shown in the drawings, but the invention is not limited to the preferred embodiments of the invention, but is intended to cover all modifications and equivalent embodiments within the spirit and scope of the invention as defined by the appended claims.

Claims

1. A method of quantum topology optimization, the method comprising:

2. The method of quantum topology optimization of claim 1, wherein the step of determining an intermediary node in the first quantum topology if the first quantum topology has a cross-connect, comprises:

Selecting a map node with the maximum connectivity as the intermediate node;

3. The method of claim 2, wherein the links in the first quantum topology have a thickness, the thickness representing the number of times of application of the qubit logic gates between any two of the logic bits in the quantum algorithm, the step of obtaining the link weights of the links between each other graph node and performing link deletion according to the link weights of the links between each other graph node to obtain a second quantum topology that does not include cross links, further comprising:

4. A quantum topology optimization method according to claim 3, wherein the step of determining the links to be deleted from the intersecting links of the first quantum topology according to the priority of the links between the nodes of each other graph specifically comprises:

5. The quantum topological graph optimization method according to claim 1, wherein the step of determining an optimization sub-graph composed of N sub-nodes connected by a connection corresponding to the node to be optimized according to a preset manner includes:

6. The quantum topology optimization method according to claim 5, wherein the step of determining an optimization sub-graph composed of N sub-nodes connected by a connection corresponding to the node to be optimized according to a preset manner further comprises:

traversing all connection relations among the N sub-nodes;

7. The quantum topology optimization method of any one of claims 1-6, wherein the step of obtaining the first quantum topology of the target quantum algorithm comprises:

8. A quantum topology optimization apparatus, the apparatus comprising:

9. A computer terminal comprising a machine-readable storage medium having stored therein a computer program and a processor arranged to run the computer program to perform the quantum topology optimization method of any of claims 1-7.

10. A computer readable storage medium, characterized in that the computer readable storage medium has stored therein a computer program which, when executed by a computer, implements the quantum topology optimization method of any of claims 1-7.