CN112379981A - Lock-free synchronization method for distributed real-time simulation task - Google Patents
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Abstract
The invention provides a lock-free synchronization method for a distributed real-time simulation task, which is characterized by comprising the following steps of: the main task and each corresponding slave task form a pair of main and slave tasks respectively; the main task acquires accurate time by accessing a high-precision clock source to control the simulation step length; initializing all main tasks and slave tasks; starting all tasks, enabling all master-slave tasks to enter circular synchronization at the starting time, and synchronously executing the master task and the slave task in each pair of the master-slave tasks. The invention aims to provide a lock-free synchronization method for distributed real-time simulation tasks, aiming at the defects of the prior art and solving the problems of high simulation task synchronization resource overhead, large simulation step size and the like in the conventional high-performance real-time simulation system.
Description
Technical Field
The invention relates to the technical field of computer simulation, in particular to a lock-free synchronization method for distributed real-time simulation tasks.
Background
The real-time simulation technology is a simulation method with completely consistent simulation time and real time, namely, the real time passes by a time quantum of delta T, and a real-time simulation system also runs the time quantum of delta T. Corresponding to real-time simulation are super real-time simulation (simulation time is less than real time) and under real-time simulation (simulation time is greater than real time).
The one-to-one relation between the simulation time and the real time is simulated in real time, so that the simulation method can be applied to off-line simulation and on-line simulation. By combining with an actual device, the real-time simulation technology can most appropriately simulate various running states of a real system in a semi-physical simulation system. Through real-time simulation, on one hand, a relatively real system environment is simulated for the optimization design and verification functions of designers, and on the other hand, huge risks caused by serious faults or misoperation during real system testing or experiments are avoided. Therefore, real-time simulation is widely applied in the fields of electric power systems, aerospace, automobiles and the like.
The real-time simulation system runs the simulation tasks step by step according to the fixed step length, the simulation tasks in each step length carry out the simulation operation of the system, and the simulation tasks ensure the real-time performance of each simulation step length by ensuring the consistency of the real time. Generally, the smaller the simulation step size, the higher the simulation precision, and the finer the simulation of the real system, so that the error with the real system is also smaller.
The simulation content is divided into individual tasks, and the tasks are distributed to different computing nodes to run in a distributed mode, so that the problem that the computing power of the single computing node is insufficient can be solved. Distributed real-time simulation generally solves the problem of synchronization between multiple tasks: 1) the simulation time of each task needs to be consistent with the real time, and the real-time performance is met; 2) all tasks need to start and end uniformly, and data consistency is met.
On one hand, distributed simulation requires calculation to be distributed to different nodes, overall calculation performance is increased, and synchronous overhead (delay) between tasks is increased for ensuring consistency between tasks; on the other hand, the existing distributed simulation task synchronization generally adopts timers and message communication mechanisms (such as semaphores, pipes, sockets and the like) provided by an operating system, and the timers and the communication methods are not specially prepared for the simulation task with high real-time performance and have poor real-time performance. For example, some timing or communication methods may block the CPU or lock resources, cause the CPU to switch to perform other tasks or sleep, or increase task switching time, or increase response delay.
Busy, etc. (a program occupies the CPU by continuously polling a clock or a variable) can effectively reduce application response delay and enhance instantaneity, but has the problem of high computational resource overhead, and long-time busy, etc. can cause the CPU to reduce frequency or enter a power saving mode, thereby reducing the computational resource utilization rate.
In distributed simulation, a synchronization method of a simulation task influences the size of a simulation step and the utilization rate of computing resources, and how to realize the synchronization method with small simulation step and low resource occupancy rate is a key technology of distributed real-time simulation.
Disclosure of Invention
The invention aims to provide a lock-free synchronization method for distributed real-time simulation tasks, aiming at the defects of the prior art and solving the problems of high simulation task synchronization resource overhead, large simulation step size and the like in the conventional high-performance real-time simulation system.
The invention provides a lock-free synchronization method for a distributed real-time simulation task, which is characterized by comprising the following steps of:
A. the main task and each corresponding slave task form a pair of main and slave tasks respectively; the main task and the subordinate task are processes or threads with different functional roles in the computer and independently run in a computing unit;
B. the main task acquires accurate time to control the simulation step length by accessing a high-precision clock source provided by an operating system, and the main task and the auxiliary task share the consistent high-precision clock;
C. initializing all main tasks and slave tasks;
D. starting all tasks, wherein all master and slave tasks enter cycle synchronization at the starting time, and a master task and a slave task in each pair of master and slave tasks are synchronously executed;
E. and if any master-slave task is overtime, namely the running time exceeds the expectation, the master-slave task is busy and the overtime task is finished.
In the technical scheme, each task has a waiting signal and a continuing signal; the task can continue to run only when the waiting signal and the continuing signal which are held by the task meet the continuing condition, otherwise, the task always waits for the continuing condition to meet; each task modifies only its own wait signal and the continue signals of other tasks or modifies only its own continue signal and the wait signals of other tasks.
In the above technical solution, each pair of master-slave tasks is executed in different independent computing units, and different independent computing units execute each pair of master-slave tasks in parallel at the same time. The present invention treats multiple CPUs or multiple CPU cores as multiple compute units. Or a plurality of FPGA board cards on the same host participate in calculation together.
In the above technical solution, the step B specifically includes the following steps:
and initializing a waiting signal and a continuing signal of each task, and respectively assigning initial values to the waiting signal and the continuing signal.
In the above technical solution, in step D, the main task cycle synchronization includes the following steps:
(1.1) updating the waiting signal of the master task and the continuing signals of all the slave tasks;
(1.2) executing the main task content;
(1.3) waiting until a time point Ts + i Δ T by the task, wherein the waiting mode is dormancy or continuous acquisition time judgment; wherein Ts is the start time, i is the number of task cycles, and Δ T is the simulation step length;
(1.4) the main task judges whether a task continuous execution condition is met or not by the numerical values of the waiting signal and the continuous signal of the task, if so, the task is continuously executed, otherwise, the task is continuously judged;
(1.5) jump to step 1.1.
In the above technical solution, in the step D, the slave task cycle synchronization includes the following steps:
(2.1) judging whether a task continuous execution condition is met or not from the task through the numerical values of the waiting signal and the continuing signal, if so, continuing execution, and otherwise, continuously judging the task;
(2.2) executing the slave task content;
(2.3) updating the slave task waiting signal and the master task continuing signal;
(2.4) jump to step 2.1.
In the above technical solution, in the step D, if the slave task cycle synchronization execution process is interrupted by the outside, all tasks are destroyed and the storage space occupied by the wait signal and the continue signal is released, and the simulation task is directly exited.
In the above technical solution, the wait signal and the continue signal are storage variables shared between the master task and the slave task; the master task and the slave task realize lock-free synchronization through a reader-writer mode, and only one writer exists for any signal variable at a certain time.
In the above technical solution, in the step E, the task timeout synchronization includes the following steps:
(3.1) until a time point Ts + i Δ T, if the main task or the slave task finds that the self waiting signal and the continuing signal do not meet the task continuing execution condition, the main task or the slave task is regarded as one time-out;
(3.2) once the time is out, the task is busy and polls the numerical values of the waiting signal and the continuing signal until the task continuing execution condition is met;
and if the task is overtime, the simulation step size and the next synchronization time are not changed (no matter whether the ith simulation step size is overtime or not, the (i +1) th synchronization time point is Ts + (i +1) × Delta T).
The invention provides a lock-free synchronization method and a lock-free synchronization device for distributed real-time simulation tasks, wherein a master task and a slave task realize two-stage synchronization, the first stage realizes coarse-grained synchronization between tasks through high-precision dormancy, and the second stage realizes complete synchronization by using the condition that the cost of a CPU is high and busy and the like, because the time of a second node is very small, the resource cost is far less than that of busy and the like, and the real-time performance is superior to the timing and communication mechanism provided based on an operating system. In a word, the method can realize the small-step-size real-time simulation of a microsecond level by using the high-precision clock, and simultaneously solves the problems of high simulation task synchronization resource overhead, large simulation step size and the like in the conventional high-performance real-time simulation system.
Drawings
FIG. 1 is a schematic diagram of a master task and a slave task of the present invention;
FIG. 2 is a flowchart illustrating the cycle synchronization steps of the master task and the slave task according to the present invention.
Detailed Description
The invention will be further described in detail with reference to the following drawings and specific examples, which are not intended to limit the invention, but are for clear understanding.
As shown in fig. 1, the present invention provides a lock-free synchronization method for distributed real-time simulation task, which is characterized by comprising the following steps:
A. the main task and each corresponding slave task form a pair of main and slave tasks respectively;
B. the main task acquires accurate time by accessing a high-precision clock source to control the simulation step length;
C. initializing all main tasks and slave tasks;
D. starting all tasks, wherein all master and slave tasks enter cycle synchronization at the starting time, and a master task and a slave task in each pair of master and slave tasks are synchronously executed;
E. and if any master-slave task is overtime, namely the running time exceeds the expectation, the master-slave task is busy and the overtime task is finished.
The high-precision clock source is provided by software of an operating system (the bottom layer of the high-precision clock source also corresponds to a hardware clock) instead of directly using a clock signal generated by the hardware clock; the high-precision clocks of the master task and the slave task are subjected to clock synchronization, and the master task and the slave task can share the same clock; the synchronization of tasks is based on the synchronization of clocks, but the synchronization of clocks does not guarantee the synchronization of tasks, and the running time of the tasks can be jittered due to environmental changes. The master task and the slave task of the invention are threads or processes running on independent computing units, and can not realize notification and synchronization by a direct calling mode.
The high-precision clock applied by the invention needs the common support of hardware and an operating system: on one hand, a physical high-frequency clock (such as a TSC clock and an HPET clock) for generating high-precision time exists in the computer; on the other hand, software of the operating system is required to support these high-precision clocks and guarantee real-time performance. The application layer may use a high precision clock to obtain precise time with a small offset from the real time. However, the general clock can only provide lower time precision for upper layer applications due to low frequency, poor precision and weak real-time performance of the operating system.
The master-slave tasks of the invention are distributed to different independent computing units: for example, different processes (threads) are allocated to different CPU cores of the multi-core CPU for respective computations. The method is distributed to independent computing cores, on one hand, distributed simulation needs are needed, namely computing is distributed to a plurality of nodes to reduce computing time, on the other hand, one task can independently occupy a CPU core, task switching time is reduced, and task instantaneity is enhanced.
The real-time simulation task comprises a plurality of tasks running on an independent computing unit, wherein the tasks comprise 1 main task and n other tasks (n is more than or equal to 1), the main task and each other task form a pair of main and auxiliary tasks, one group of the main and auxiliary tasks are Tm and Ts, and the simulation step length is 10 microseconds (delta T is 10 us). As shown in fig. 1, the master task may obtain precise time by accessing a high-precision clock source. Each task (master or slave) holds a pair of signals, namely a wait signal and a continue signal, and the task continues to run only when the wait signal and the continue signal held by the task meet a continue condition, otherwise the continue condition is always waited for to meet. Each task modifies only its own wait signal and the other tasks 'continue signals (or only its own continue signal and the other tasks' wait signals).
The independent computing unit is a general-purpose or special-purpose processor unit with computing capability, such as a CPU core, a CPU hyper-thread, an FPGA, a GPU core, and the like, and a plurality of CPUs or a plurality of CPU cores can be regarded as a plurality of computing units. Or a plurality of FPGA board cards on the same host participate in calculation together. Different independent computing units may execute programs in parallel at the same time.
The tasks (peer task, master task, and slave task) refer to independently executable programs, such as processes, threads, or a piece of independently executable program code on an operating system. The master task controls the simulation step size and controls the execution and waiting of the slave task through the waiting and continuing signals.
The high-precision clock source is a digital clock with high time precision and accuracy and low time jitter, and can provide timing and timing functions for tasks running on a computing unit, such as a TSC clock and an HPET clock of an X86 processor, a frequency clock of an FPGA and the like. The precision and the jitter of the high-precision clock source are adaptive to the size of the simulation step length. The smaller the step size, the higher the clock source accuracy. An operating system is generally limited to a simulation step minimum value according to hardware and software, and in an actual situation, the simulation step size is manually set according to the model size and the task requirement (partially by experience). Once a certain fixed step size is chosen, the task will model-wise emulate (guaranteed by high precision clocks and applications) constantly at that fixed step size. The criteria for manually selecting the fixed simulation step size are: 1) greater than the simulation step minimum; 2) the required simulation operation can be completed within the fixed simulation step length.
The signals (wait signal and continue signal) are storage variables shared between tasks, such as volatile (shared) shared memory variables, etc.
The master task and the slave task realize lock-free synchronization through a reader-writer mode, and only one writer exists in any signal variable at a certain moment, so that lock-free access to key data is guaranteed.
An initialization step comprising the sub-steps of:
initializing a master task Tm waiting signal Tm. wait ═ 0 and a continuation signal Tm. continuation ═ 1, and initializing a slave task waiting signal ts.wait ═ 0 and a continuation signal ts.continuation ═ 1;
starting all peer-to-peer tasks, entering cycle synchronization at the time of starting time Ts, and executing step 2;
(2.1) the main task cycle synchronization comprises the steps of:
(2.1.1) adding 1 to the main task waiting signal, namely + + Tm.wait; add 1 from the task continuation signal, i.e. + ts.continue;
(2.1.2) executing the main task content, namely running the simulation program code in the main task;
(2.1.3) in the i-th loop, the sleep function clock _ sleep () is executed to a time point Ts +. DELTA.T.i., Ts +10 i.
(2.1.4) the main task judges whether the continuous execution condition of the task is met, and the continuous execution condition is the following inequality
Tm.continue>Tm.wait
If the execution is satisfied, continuing to execute, otherwise, if the task is overtime, entering a task overtime synchronization step, and continuously judging whether the execution condition is satisfied in the overtime step;
(2.1.5) jump to step 2.1.1.
(2.2) slave task cycle synchronization comprising the steps of:
(2.2.1) judging whether a task continuous execution condition is met from the task, wherein the continuous execution condition is the following inequality
Ts.continue>Ts.wait
If the continuous execution is satisfied, otherwise, the task continuously judges whether the continuous execution condition is satisfied;
(2.2.2) executing the slave task content, i.e. running the slave task emulating program code;
(2.2.3) adding 1 to the slave task waiting signal, namely + + Ts.wait, and adding 1 to the master task continuing signal, namely + + Tm.continue;
(2.2.4) jump to step 2.2.1.
Wherein the task timeout synchronization comprises the steps of:
(3.1) until a time point Ts + i Δ T, judging that the main task or the slave task does not meet the task continuous execution condition of the waiting signal and the continuous signal of the main task or the slave task, and regarding the main task or the slave task as one-time overtime;
(3.2) once the time is out, the task is busy and polls the numerical values of the waiting signal and the continuing signal until the task continuing execution condition is met;
wherein, whether the task is overtime or not does not change the simulation step length and the next synchronization time; whether the ith simulation step is overtime or not, the (i +1) th synchronization time point is Ts + (i +1) deltaT.
(3) And finishing the step, when the execution process of the step 2 is interrupted by the outside, executing the step, destroying the task Ts and the task Tm, and releasing the storage space occupied by the waiting signals Tm.wait and Ts.wait and the continuing signals Tm.continue and Ts.continue.
Details not described in this specification are within the skill of the art that are well known to those skilled in the art.
Claims (9)
1. A lock-free synchronization method facing to a distributed real-time simulation task is characterized by comprising the following steps:
A. the main task and each corresponding slave task form a pair of main and slave tasks respectively; the main task and the subordinate task are processes or threads with different functional roles in the computer and independently run in a computing unit;
B. the main task acquires accurate time to control the simulation step length by accessing a high-precision clock source provided by an operating system, and the main task and the auxiliary task share the consistent high-precision clock;
C. initializing all main tasks and slave tasks;
D. starting all tasks, wherein all master and slave tasks enter cycle synchronization at the starting time, and a master task and a slave task in each pair of master and slave tasks are synchronously executed;
E. and if any master-slave task is overtime, namely the running time exceeds the expectation, the master-slave task is busy and the overtime task is finished.
2. The lock-free synchronization method for distributed real-time simulation tasks according to claim 1, wherein each task holds a wait signal and a continue signal; the task can continue to run only when the waiting signal and the continuing signal which are held by the task meet the continuing condition, otherwise, the task always waits for the continuing condition to meet; each task modifies only its own wait signal and the continue signals of other tasks or modifies only its own continue signal and the wait signals of other tasks.
3. The lock-free synchronization method for distributed real-time simulation tasks according to claim 1, wherein each pair of master-slave tasks is executed by a different independent computing unit, and the different independent computing units execute each pair of master-slave tasks in parallel at the same time.
4. The lock-free synchronization method for the distributed real-time simulation task according to claim 2, wherein the step B specifically comprises the following steps:
and initializing a waiting signal and a continuing signal of each task, and respectively assigning initial values to the waiting signal and the continuing signal.
5. The lock-free synchronization method for distributed real-time simulation tasks according to claim 4, wherein in step D, the cycle synchronization of the main task comprises the following steps:
(1.1) updating the waiting signal of the master task and the continuing signals of all the slave tasks;
(1.2) executing the main task content;
(1.3) waiting until a time point Ts + i Δ T by the task, wherein the waiting mode is dormancy or continuous acquisition time judgment; wherein Ts is the start time, i is the number of task cycles, and Δ T is the simulation step length;
(1.4) the main task judges whether a task continuous execution condition is met or not by the numerical values of the waiting signal and the continuous signal of the task, if the task continuous execution condition is met, the task is overtime; wherein the continuous execution condition is that the continuous signal value of the main task is greater than the waiting signal value of the main task;
(1.5) jump to step 1.1.
6. The lock-free synchronization method for distributed real-time simulation tasks according to claim 5, wherein the step D, the slave task cycle synchronization comprises the following steps:
(2.1) judging whether a task continuous execution condition is met or not from the task through the numerical values of the waiting signal and the continuing signal, if so, continuing execution, and otherwise, continuously judging the task; wherein the condition of continuing execution is that the value of the continuing signal of the slave task is greater than the value of the waiting signal of the slave task;
(2.2) executing the slave task content;
(2.3) updating the slave task waiting signal and the master task continuing signal;
(2.4) jump to step 2.1.
7. The lock-free synchronization method for distributed real-time simulation tasks according to claim 6, wherein in the step D, if the synchronous execution process from the task cycle is interrupted by the outside, all tasks are destroyed and the memory space occupied by the waiting signal and the continuing signal is released, and the simulation task is directly exited.
8. The lock-free synchronization method for distributed real-time simulation tasks according to claim 7, wherein the wait signal and the continue signal are storage variables shared between the master task and the slave task; the master task and the slave task realize lock-free synchronization through a reader-writer mode, and only one writer exists for any signal variable at a certain time.
9. The lock-free synchronization method for distributed real-time simulation tasks according to claim 5, wherein in the step E, the task timeout synchronization comprises the following steps:
(3.1) until a time point Ts + i Δ T, judging that the main task or the slave task does not meet the task continuous execution condition of the waiting signal and the continuous signal of the main task or the slave task, and regarding the main task or the slave task as one-time overtime;
(3.2) once the time is out, the task is busy and polls the numerical values of the waiting signal and the continuing signal until the task continuing execution condition is met;
wherein, whether the task is overtime or not does not change the simulation step length and the next synchronization time; whether the ith simulation step is overtime or not, the (i +1) th synchronization time point is Ts + (i +1) deltaT.
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| CN114779878A (en) * | 2022-04-25 | 2022-07-22 | 南方电网科学研究院有限责任公司 | System and method for calculating simulation step length time of power system |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113746931A (en) * | 2021-09-10 | 2021-12-03 | 联想(北京)有限公司 | Data synchronization method and device |
| CN114779878A (en) * | 2022-04-25 | 2022-07-22 | 南方电网科学研究院有限责任公司 | System and method for calculating simulation step length time of power system |
| CN114779878B (en) * | 2022-04-25 | 2023-03-03 | 南方电网科学研究院有限责任公司 | System and method for calculating simulation step length time of power system |
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