CN112379967A - Simulator detection method, device, equipment and medium - Google Patents
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Abstract
The embodiment of the disclosure provides a simulator detection method, a simulator detection device and a simulator detection medium, wherein the simulator detection method comprises the following steps: determining a system architecture of an operating system of the terminal device; determining a central processor identification instruction corresponding to a system architecture of an operating system; acquiring relevant parameters of a processor of the terminal equipment by executing a central processing unit identification instruction; it is determined whether the processor is a simulator based on the correlation parameter. In the embodiment of the present disclosure, because the values of some parameters of the real processor and the simulator are different, whether the processor is the simulator or not may be determined based on the obtained parameters; furthermore, the related parameters are acquired based on the identification instruction of the central processing unit and do not depend on files and attribute characteristics which are relatively easy to be tampered by the outside, so that the simulator and the real terminal equipment can be further ensured to be accurately distinguished.
Description
Technical Field
The present disclosure relates to the field of computer technologies, and in particular, to a simulator detection method, apparatus, device, and medium.
Background
The simulator can also be called as a simulation program, and refers to a program which mainly simulates the functions and instruction systems of a hardware processor through software so that a computer or other multimedia platforms (a palm computer and a mobile phone) can run software on other platforms. The simulator and the real software have different processing modes, so that the detection of the simulator is a very important index to avoid the problem of causing misjudgment. However, when the android system version is in the period of 5.0 to 6.0, a mobile phone with a part of the same architecture as that of the simulator has been proposed, and since the mobile phone needs to translate and analyze an instruction set when executing an instruction, the file and attribute characteristics of the mobile phone are quite similar to those of the simulator, and at this time, if the mobile phone and the simulator are distinguished based on the file and attribute characteristics of the mobile phone, there is a problem that accurate distinguishing cannot be achieved.
Disclosure of Invention
This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.
In a first aspect, an embodiment of the present disclosure provides a simulator detection method, including:
determining a system architecture of an operating system of the terminal device;
determining a central processing unit Identity (cpu id) corresponding to a system architecture of an operating system;
acquiring relevant parameters of a processor of the terminal equipment by executing a central processing unit identification instruction;
it is determined whether the processor is a simulator based on the correlation parameter.
In a second aspect, an embodiment of the present disclosure provides a simulator testing apparatus, including:
the system architecture determining module is used for determining the system architecture of the operating system of the terminal equipment;
the system comprises a relevant parameter acquisition module, a central processing unit identification module and a terminal equipment, wherein the relevant parameter acquisition module is used for determining a central processing unit identification instruction corresponding to a system architecture of an operating system and acquiring relevant parameters of a processor of the terminal equipment by executing the central processing unit identification instruction of the operating system;
and the simulator judging module is used for determining whether the processor is a simulator or not based on the relevant parameters.
In a third aspect, the present disclosure provides an electronic device comprising a processor and a memory;
a memory for storing computer operating instructions;
a processor for performing the method as shown in any of the first aspect of the embodiments of the present disclosure by invoking computer operational instructions.
In a fourth aspect, the present disclosure provides a computer readable medium having stored thereon at least one instruction, at least one program, set of codes or set of instructions, which is loaded and executed by a processor to implement a method as shown in any one of the first aspect of embodiments of the present disclosure.
The technical scheme provided by the embodiment of the disclosure has the following beneficial effects:
in the embodiment of the present disclosure, a system architecture of an operating system of a terminal device may be determined, a central processing unit identification instruction corresponding to the system architecture of the operating system is determined, then a relevant parameter of a processor is obtained through the central processing unit identification instruction, and whether the processor is a simulator is determined based on the relevant parameter, since values of some parameters of a real processor and the simulator are different, whether the processor is a simulator may be determined based on the obtained parameter; furthermore, the related parameters are acquired based on the identification instruction of the central processing unit and do not depend on files and attribute characteristics which are relatively easy to be tampered by the outside, so that the simulator and the real terminal equipment can be further ensured to be accurately distinguished.
Drawings
The above and other features, advantages and aspects of various embodiments of the present disclosure will become more apparent by referring to the following detailed description when taken in conjunction with the accompanying drawings. Throughout the drawings, the same or similar reference numbers refer to the same or similar elements. It should be understood that the drawings are schematic and that elements and features are not necessarily drawn to scale.
FIG. 1 is a schematic flow chart illustrating a method for detecting a simulator according to an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of related information in an embodiment of the disclosure;
FIG. 3 is a schematic diagram illustrating a complete flow of a simulator detection method according to an embodiment of the present disclosure;
FIG. 4 is a schematic structural diagram of a simulator detection apparatus according to an embodiment of the present disclosure;
fig. 5 is a schematic structural diagram of an electronic device in an embodiment of the disclosure.
Detailed Description
Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present disclosure are shown in the drawings, it is to be understood that the present disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but rather are provided for a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the disclosure are for illustration purposes only and are not intended to limit the scope of the disclosure.
It should be understood that the various steps recited in the method embodiments of the present disclosure may be performed in a different order, and/or performed in parallel. Moreover, method embodiments may include additional steps and/or omit performing the illustrated steps. The scope of the present disclosure is not limited in this respect.
The term "include" and variations thereof as used herein are open-ended, i.e., "including but not limited to". The term "based on" is "based, at least in part, on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Relevant definitions for other terms will be given in the following description.
It should be noted that the terms "first", "second", and the like in the present disclosure are only used for distinguishing different devices, modules or units, and are not used for limiting the devices, modules or units to be determined as different devices, modules or units, and are not used for limiting the sequence or interdependence relationship of the functions executed by the devices, modules or units.
It is noted that references to "a", "an", and "the" modifications in this disclosure are intended to be illustrative rather than limiting, and that those skilled in the art will recognize that "one or more" may be used unless the context clearly dictates otherwise.
The names of messages or information exchanged between devices in the embodiments of the present disclosure are for illustrative purposes only, and are not intended to limit the scope of the messages or information.
An embodiment of the present disclosure provides a method for discriminating a simulator based on an intel architecture, as shown in fig. 1, the method may include:
step S110, determining a system architecture of an operating system of the terminal device.
The system architecture refers to a specific architecture of a processor applied by an operating system of the terminal device, and for example, the system architecture may be an intel architecture.
In an embodiment of the present disclosure, determining a system architecture of an operating system of a terminal device includes:
acquiring header data of an ELF (Executable and Linkable Format) file of an operating system;
the system architecture of the terminal device is determined based on the header data.
In practical applications, generally, the header data of the file of the operating system of the terminal device may characterize the system architecture of the operating system of the terminal device, and based on this, in the embodiment of the present disclosure, when determining the system architecture of the terminal device, the header data of the ELF file of the operating system may be acquired, and then the system architecture may be determined based on the header data of the ELF file. For example, if the architecture of the header data of the ELF file is intel architecture, it can be determined that the system architecture of the terminal device is intel architecture. If the structure of the header data of the ELF file is not an intel structure, it is described that the system structure of the terminal device is not an intel structure, and there is no case that the real terminal device and the simulator cannot be distinguished.
Step S120, determining a central processing unit identification instruction corresponding to the system architecture of the operating system.
Optionally, after determining the system architecture of the operating system, the central processing unit identification instruction corresponding to the system architecture of the operating system may be determined. For example, when the system architecture is intel architecture, the corresponding cpu recognizes that the instruction is a cupid instruction that the intel architecture can execute.
And step S130, acquiring relevant parameters of a processor of the terminal equipment by executing the central processing unit identification instruction.
Wherein the relevant parameters refer to data parameters that can be used to determine whether the processor of the terminal device is a simulator. Optionally, after determining the central processing unit identification instruction corresponding to the system architecture of the operating system, the relevant parameter may be obtained by executing the central processing unit identification instruction.
In step S140, it is determined whether the processor is a simulator based on the relevant parameters.
Optionally, after the related parameters are obtained, it may be determined whether the processor is a simulator based on the obtained related parameters. For example, in practical applications, when it is determined that the system architecture is an intel (intel) system architecture, which indicates that there may be a case where it is impossible to distinguish whether the system architecture is a real terminal device or a simulator, the cpu id instruction of the intel architecture may be executed to obtain relevant parameters of a processor of the terminal device, and then it is determined whether the system architecture is a simulator based on the obtained relevant parameters.
In the embodiment of the present disclosure, a system architecture of an operating system of a terminal device may be determined, a central processing unit identification instruction corresponding to the system architecture of the operating system is determined, then a relevant parameter of a processor is obtained through the central processing unit identification instruction, and whether the processor is a simulator is determined based on the relevant parameter, since values of some parameters of a real processor and the simulator are different, whether the processor is a simulator may be determined based on the obtained parameter; furthermore, the related parameters are acquired based on the identification instruction of the central processing unit and do not depend on files and attribute characteristics which are relatively easy to be tampered by the outside, so that the simulator and the real terminal equipment can be further ensured to be accurately distinguished.
In an optional embodiment of the present disclosure, acquiring header data in an executable and linkable format of an operating system includes:
acquiring a full path of a linker file of the terminal equipment through a maps (memory module mapping) file of an operating system;
analyzing the files in the full path of the linker file;
determining executable and linkable format files from the files according to the file format types;
and analyzing the executable and linkable format files according to the file data format to obtain the header data.
Optionally, an optional manner of obtaining header data of an ELF file of an operating system is provided in this disclosure, for example, a full path of a linker file of a terminal device may be obtained through a maps file of the operating system, and then the full path of the obtained linker file is analyzed to obtain files in the full path, where file format types of the files in the full path may be different, and each file has an identifier for identifying a file format type to which the file format type belongs; correspondingly, the executable and linkable format files can be determined from the files in the full path according to the file format type identifiers corresponding to the files in the full path, the executable and linkable format files obtained by analysis at this time have data in a plurality of file data formats, each data has a format identifier for identifying the file data format to which the data belongs, and at this time, which data is/are the header data is/are determined from the data obtained by analysis according to the format identifier of each data.
In an optional embodiment of the present disclosure, identifying an instruction by a central processing unit executing an operating system to obtain a relevant parameter of a processor of a terminal device includes:
executing the central processing unit identification instruction by running an executive program in the assets (resource file) to acquire relevant parameters of a processor of the terminal equipment.
In practical applications, the assets file is used for storing various resource files of an application program in the terminal device, and the assets file comprises an execution file for executing different instructions; correspondingly, when the central processing unit identification instruction needs to be executed, the executive program in the assets file can be released and run first, and then the central processing unit identification instruction is executed through the released and run executive program, so that the relevant parameters of the processor of the terminal device are obtained.
In an embodiment of the present disclosure, the related parameter may include at least one of:
the processor model, the number of logical processors, the value of PeMoCounters, and the value of HV _ BIT (back gate value for virtual machines).
In an embodiment of the disclosure, determining whether the processor is a simulator based on the correlation parameter includes:
determining whether the processor is a simulator when the relevant parameter is determined to meet any one of the following specified conditions, wherein the specified conditions comprise:
any one of the number of the logic processors and the value of the performance counter is 0, the back door value of the virtual machine is 1, and the equipment model is a non-specified equipment model.
In practical applications, the obtained related information may include various information, and thus, when determining whether the processor is a simulator based on the related parameters, various situations may exist. For example, when any one of the obtained number of logical processors and the value of the performance counter is 0, it may be determined that the current processor is the simulator, or when the value of HV _ BIT is 1, it may be determined that the current processor is the simulator, or when the device model is a non-specified device model, it may be determined that the current processor is the simulator. Wherein the specified device model may include currently known Intel processors such as: including but not limited to atom processors, race processors, genine Intel and spreadrum, etc., that is, when the obtained device model is not atom processors, race processors, genine Intel and spreadrum, if any of the logical processor number and the performance counter value is 0 or the HV _ BIT value is 1, the feature of the device is the simulator feature at this time, it can be determined that the current processor is a simulator, otherwise it can be classified as a newly added trusted Intel processor.
It should be noted that, when it is determined that the processor is a simulator through one of the relevant parameters, other values may be used to determine whether the processor is a value of the relevant parameter of the simulator, and in this case, the value is also a value when the processor is a simulator. For example, when the current processor is determined to be a simulator by taking the HV _ BIT value as 1, the acquired device model is also necessarily a non-specified model.
In an example, as shown in fig. 2, assuming that the system architecture is an intel architecture, when the processor of the terminal device is a simulator, the device model (shown in an area a in fig. 2) obtained by the CPU id instruction is the same as the device model (shown in an area B in fig. 2) of a host PC (Personal Computer) end of the simulator, which is "intel (r) core (tm) i7-9750H CPU @2.60 GHz", and in addition, other information, such as version information, memory information and the like, of the host PC end of the simulator is also shown in fig. 2.
It should be noted that, if the system architecture of the operating system of the terminal device is an intel system architecture, at this time, when determining whether the terminal device is a simulator, the central processing unit is required to identify an instruction, and therefore, when using the method provided by the embodiment of the present disclosure, it is required to ensure that the terminal device can support an instruction set of an arm (Advanced RISC machine, reduced instruction set central processing unit) architecture.
For better understanding of the method provided by the embodiment of the present disclosure, the following provides a detailed description of the scheme in combination with an actual scenario, in this example, a system architecture of an operating system of a terminal device is an intel architecture, as shown in fig. 3, and the method specifically includes:
step S401, acquiring a full path of a linker file of the terminal equipment through a maps file of an operating system;
step S402, analyzing the full path of the linker file to obtain the head data of the ELF file;
step S403, determining whether the system architecture of the terminal equipment is an intel system architecture or not based on the head data, if so, executing step S404, otherwise, executing step S407;
step S404, running an executive program in the assets resource file;
step S405, a cpu id instruction is executed to obtain relevant parameters of a processor of the terminal equipment;
step S406, determining whether the processor is a simulator or not based on the relevant parameters;
step S407, the system architecture of the terminal device is not the intel system architecture.
Based on the same principle as the method shown in fig. 1, an embodiment of the present disclosure further provides a simulator detection apparatus 30, as shown in fig. 4, the simulator detection apparatus 30 may include a system architecture determining module 310, a related parameter acquiring module 320, and a simulator determining module 330, where:
a system architecture determination module 310, configured to determine a system architecture of an operating system of the terminal device;
a relevant parameter obtaining module 320, configured to determine a central processing unit identification instruction corresponding to a system architecture of the operating system, and obtain a relevant parameter of a processor of the terminal device by executing the central processing unit identification instruction of the operating system;
a simulator decision module 330 for determining whether the processor is a simulator based on the relevant parameters.
In an embodiment of the present disclosure, when determining the system architecture of the operating system of the terminal device, the system architecture determination module is specifically configured to:
acquiring head data of executable and linkable format files of an operating system;
the system architecture of the terminal device is determined based on the header data.
In an embodiment of the present disclosure, when acquiring header data of a linkable format file of an operating system, the system architecture determination module is specifically configured to:
acquiring a full path of a linker file of the terminal equipment through a memory module mapping file of an operating system;
analyzing the full path of the memory module mapping file;
determining executable and linkable format files from the files according to the file format types;
and analyzing the executable and linkable format files according to the file data format to obtain the header data.
In an embodiment of the present disclosure, when the related parameter acquiring module identifies an instruction by executing a central processing unit of an operating system to acquire a related parameter of a processor of a terminal device, the related parameter acquiring module is specifically configured to:
and executing the central processing unit identification instruction by executing the executive program in the resource file to acquire the relevant parameters of the processor of the terminal equipment.
In an embodiment of the disclosure, the relevant parameters include at least one of:
the processor model, the number of logical processors, the value of the performance counter, and the value of the backgate value of the virtual machine.
In an embodiment of the disclosure, when determining whether the processor is a simulator based on the relevant parameter, the simulator determination module is specifically configured to:
determining the processor as a simulator when the relevant parameter is determined to meet any one of the following specified conditions, wherein the specified conditions comprise:
the number of the logic processors is 0 or the value of the performance counter is 0, the back door value of the virtual machine is 1, and the equipment model is a non-specified equipment model.
The simulator detection device of the embodiment of the present disclosure may execute the simulator detection method provided by the embodiment of the present disclosure, and the implementation principles thereof are similar, the actions executed by each module in the simulator detection device of each embodiment of the present disclosure correspond to the steps in the simulator detection method of each embodiment of the present disclosure, and for the detailed functional description of each module of the simulator detection device, reference may be specifically made to the description in the corresponding simulator detection method shown in the foregoing, and details are not repeated here.
Based on the same principle as the method shown in the embodiments of the present disclosure, embodiments of the present disclosure also provide an electronic device, which may include but is not limited to: a processor and a memory; a memory for storing computer operating instructions; and the processor is used for executing the method shown in the embodiment by calling the computer operation instruction.
Based on the same principle as the method shown in the embodiment of the present disclosure, an embodiment of the present disclosure further provides a computer-readable storage medium, where at least one instruction, at least one program, a code set, or an instruction set is stored in the computer-readable storage medium, and the at least one instruction, the at least one program, the code set, or the instruction set is loaded and executed by a processor to implement the method shown in the embodiment, which is not described herein again.
Referring now to FIG. 5, a block diagram of an electronic device 600 suitable for use in implementing embodiments of the present disclosure is shown. The terminal device in the embodiments of the present disclosure may include, but is not limited to, a mobile terminal such as a mobile phone, a notebook computer, a digital broadcast receiver, a PDA (personal digital assistant), a PAD (tablet computer), a PMP (portable multimedia player), a vehicle terminal (e.g., a car navigation terminal), and the like, and a stationary terminal such as a digital TV, a desktop computer, and the like. The electronic device shown in fig. 5 is only an example, and should not bring any limitation to the functions and the scope of use of the embodiments of the present disclosure.
The electronic device includes: a memory and a processor, wherein the processor may be referred to as the processing device 601 hereinafter, and the memory may include at least one of a Read Only Memory (ROM)602, a Random Access Memory (RAM)603 and a storage device 608 hereinafter, which are specifically shown as follows:
as shown in fig. 5, electronic device 600 may include a processing means (e.g., central processing unit, graphics processor, etc.) 601 that may perform various appropriate actions and processes in accordance with a program stored in a Read Only Memory (ROM)602 or a program loaded from a storage means 608 into a Random Access Memory (RAM) 603. In the RAM 603, various programs and data necessary for the operation of the electronic apparatus 600 are also stored. The processing device 601, the ROM 602, and the RAM 603 are connected to each other via a bus 604. An input/output (I/O) interface 605 is also connected to bus 604.
Generally, the following devices may be connected to the I/O interface 605: input devices 606 including, for example, a touch screen, touch pad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, etc.; output devices 607 including, for example, a Liquid Crystal Display (LCD), a speaker, a vibrator, and the like; storage 608 including, for example, tape, hard disk, etc.; and a communication device 609. The communication means 609 may allow the electronic device 600 to communicate with other devices wirelessly or by wire to exchange data. While fig. 5 illustrates an electronic device 600 having various means, it is to be understood that not all illustrated means are required to be implemented or provided. More or fewer devices may alternatively be implemented or provided.
In particular, according to an embodiment of the present disclosure, the processes described above with reference to the flowcharts may be implemented as computer software programs. For example, embodiments of the present disclosure include a computer program product comprising a computer program carried on a non-transitory computer readable medium, the computer program containing program code for performing the method illustrated by the flow chart. In such an embodiment, the computer program may be downloaded and installed from a network via the communication means 609, or may be installed from the storage means 608, or may be installed from the ROM 602. The computer program, when executed by the processing device 601, performs the above-described functions defined in the methods of the embodiments of the present disclosure.
It should be noted that the computer readable medium in the present disclosure can be a computer readable signal medium or a computer readable storage medium or any combination of the two. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples of the computer readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the present disclosure, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. In contrast, in the present disclosure, a computer readable signal medium may comprise a propagated data signal with computer readable program code embodied therein, either in baseband or as part of a carrier wave. Such a propagated data signal may take many forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: electrical wires, optical cables, RF (radio frequency), etc., or any suitable combination of the foregoing.
In some embodiments, the clients, servers may communicate using any currently known or future developed network Protocol, such as HTTP (HyperText Transfer Protocol), and may interconnect with any form or medium of digital data communication (e.g., a communications network). Examples of communication networks include a local area network ("LAN"), a wide area network ("WAN"), the Internet (e.g., the Internet), and peer-to-peer networks (e.g., ad hoc peer-to-peer networks), as well as any currently known or future developed network.
The computer readable medium may be embodied in the electronic device; or may exist separately without being assembled into the electronic device.
Computer program code for carrying out operations for the present disclosure may be written in any combination of one or more programming languages, including but not limited to an object oriented programming language such as Java, Smalltalk, C + +, and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet service provider).
The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
The modules or units described in the embodiments of the present disclosure may be implemented by software or hardware. Wherein the designation of a module or unit does not in some cases constitute a limitation of the unit itself.
The functions described herein above may be performed, at least in part, by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: field Programmable Gate Arrays (FPGAs), Application Specific Integrated Circuits (ASICs), Application Specific Standard Products (ASSPs), systems on a chip (SOCs), Complex Programmable Logic Devices (CPLDs), and the like.
In the context of this disclosure, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
According to one or more embodiments of the present disclosure, there is provided a simulator detection method including:
determining a system architecture of an operating system of the terminal device;
determining a central processor identification instruction corresponding to a system architecture of an operating system;
acquiring relevant parameters of a processor of the terminal equipment by executing a central processing unit identification instruction;
it is determined whether the processor is a simulator based on the correlation parameter.
According to one or more embodiments of the present disclosure, determining a system architecture of an operating system of a terminal device includes:
acquiring head data of executable and linkable format files of an operating system;
the system architecture of the terminal device is determined based on the header data.
According to one or more embodiments of the present disclosure, acquiring header data of an executable and linkable format of an operating system includes:
acquiring a full path of a linker file of the terminal equipment through a memory module mapping file of an operating system;
analyzing the files in the full path of the linker file;
determining executable and linkable format files from the files according to the file format types;
and analyzing the executable and linkable format files according to the file data format to obtain the header data. .
According to one or more embodiments of the present disclosure, acquiring relevant parameters of a processor of a terminal device by executing a central processing unit identification instruction includes:
and executing the central processing unit identification instruction by operating the executive program in the resource file to acquire the relevant parameters of the processor of the terminal equipment.
According to one or more embodiments of the present disclosure, the relevant parameters include at least one of:
the processor model, the number of logical processors, the value of the performance counter, and the value of the backgate value of the virtual machine.
In accordance with one or more embodiments of the present disclosure, determining whether a processor is a simulator based on a correlation parameter includes:
determining the processor as a simulator when the relevant parameter is determined to meet any one of the following specified conditions, wherein the specified conditions comprise:
the number of the logic processors is 0 or the value of the performance counter is 0, the back door value of the virtual machine is 1, and the equipment model is a non-specified equipment model.
According to one or more embodiments of the present disclosure, there is provided a simulator detection apparatus including:
the system architecture determining module is used for determining the system architecture of the operating system of the terminal equipment;
the system comprises a relevant parameter acquisition module, a central processing unit identification module and a terminal equipment, wherein the relevant parameter acquisition module is used for determining a central processing unit identification instruction corresponding to a system architecture of an operating system and acquiring relevant parameters of a processor of the terminal equipment by executing the central processing unit identification instruction of the operating system;
and the simulator judging module is used for determining whether the processor is a simulator or not based on the relevant parameters.
According to one or more embodiments of the present disclosure, the system architecture determination module, when determining the system architecture of the operating system of the terminal device, is specifically configured to:
acquiring head data of executable and linkable format files of an operating system;
the system architecture of the terminal device is determined based on the header data.
According to one or more embodiments of the present disclosure, the system architecture determination module, when acquiring header data of an executable and linkable format file of an operating system, is specifically configured to:
acquiring a full path of a linker file of the terminal equipment through a memory module mapping file of an operating system;
analyzing the full path of the memory module mapping file;
determining executable and linkable format files from the files according to the file format types;
and analyzing the executable and linkable format files according to the file data format to obtain the header data.
According to one or more embodiments of the present disclosure, when the related parameter acquiring module identifies and acquires the related parameter of the processor of the terminal device by executing the central processing unit of the operating system, the related parameter acquiring module is specifically configured to:
and executing the central processing unit identification instruction by running the executive program in the assets resource file to acquire the relevant parameters of the processor of the terminal equipment.
According to one or more embodiments of the present disclosure, the relevant parameters include at least one of:
the processor model, the number of logical processors, the value of the performance counter, and the value of the backgate value of the virtual machine.
According to one or more embodiments of the present disclosure, the simulator determination module, when determining whether the processor is a simulator based on the relevant parameter, is specifically configured to:
determining the processor as a simulator when the relevant parameter is determined to meet any one of the following specified conditions, wherein the specified conditions comprise:
the number of the logic processors is 0 or the value of the performance counter is 0, the back door value of the virtual machine is 1, and the equipment model is a non-specified equipment model.
According to one or more embodiments of the present disclosure, there is provided an electronic device including:
a processor and a memory;
a memory for storing computer operating instructions;
and the processor is used for executing the method of any one of the simulator detection methods by calling the computer operation instruction.
According to one or more embodiments of the present disclosure, there is provided a computer-readable medium storing at least one instruction, at least one program, set of codes, or set of instructions, which is loaded and executed by a processor to implement a method of any one of the simulator detection methods.
The foregoing description is only exemplary of the preferred embodiments of the disclosure and is illustrative of the principles of the technology employed. It will be appreciated by those skilled in the art that the scope of the disclosure herein is not limited to the particular combination of features described above, but also encompasses other embodiments in which any combination of the features described above or their equivalents does not depart from the spirit of the disclosure. For example, the above features and (but not limited to) the features disclosed in this disclosure having similar functions are replaced with each other to form the technical solution.
Further, while operations are depicted in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order. Under certain circumstances, multitasking and parallel processing may be advantageous. Likewise, while several specific implementation details are included in the above discussion, these should not be construed as limitations on the scope of the disclosure. Certain features that are described in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination.
Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.
Claims (10)
1. A simulator testing method, comprising:
determining a system architecture of an operating system of the terminal device;
determining a central processor identification instruction corresponding to a system architecture of the operating system;
acquiring relevant parameters of a processor of the terminal equipment by executing the central processing unit identification instruction;
determining whether the processor is a simulator based on the correlation parameter.
2. The method of claim 1, wherein determining the system architecture of the operating system of the terminal device comprises:
acquiring the head data of the executable and linkable format file of the operating system;
determining a system architecture of the terminal device based on the header data.
3. The method of claim 2, wherein obtaining header data in an executable and linkable format of the operating system comprises:
acquiring the full path of a linker file of the terminal equipment through a memory module mapping file of the operating system;
analyzing the files in the full path of the linker file;
determining executable and linkable format files from the files according to file format types;
and analyzing the executable and linkable format file according to the file data format to obtain the header data.
4. The method of claim 1, wherein the obtaining of the relevant parameters of the processor of the terminal device by executing the central processor identification instruction comprises:
and executing the central processing unit identification instruction by operating an executive program in the resource file so as to acquire relevant parameters of the processor of the terminal equipment.
5. The method of claim 1, wherein the related parameters comprise at least one of:
the processor model, the number of logical processors, the value of the performance counter, and the value of the backgate value of the virtual machine.
6. The method of claim 5, wherein determining whether the processor is a simulator based on the correlation parameter comprises:
determining the processor as a simulator when determining that the relevant parameter meets any one of the following specified conditions, wherein the specified conditions include:
the number of the logic processors is 0 or the value of the performance counter is 0, the back door value of the virtual machine is 1, and the equipment model is a non-specified equipment model.
7. A simulator testing apparatus comprising:
the system architecture determining module is used for determining the system architecture of the operating system of the terminal equipment;
a relevant parameter obtaining module, configured to determine a central processing unit identification instruction corresponding to a system architecture of the operating system, and obtain a relevant parameter of a processor of the terminal device by executing the central processing unit identification instruction of the operating system;
and the simulator judging module is used for determining whether the processor is a simulator or not based on the relevant parameters.
8. The apparatus according to claim 7, wherein the system architecture determination module, when determining the system architecture of the operating system of the terminal device, is specifically configured to:
acquiring the head data of the executable and linkable format file of the operating system;
determining a system architecture of the terminal device based on the header data.
9. An electronic device, comprising:
a processor and a memory;
the memory is used for storing computer operation instructions;
the processor is used for executing the method of any one of claims 1 to 6 by calling the computer operation instruction.
10. A computer readable medium having stored thereon at least one instruction, at least one program, a set of codes, or a set of instructions, which is loaded and executed by a processor to implement the method of any of claims 1 to 6.
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