CN112367279A - Routing method and system based on two-dimensional mesh structure multi-core chipset - Google Patents
Routing method and system based on two-dimensional mesh structure multi-core chipset Download PDFInfo
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- CN112367279A CN112367279A CN202011188249.1A CN202011188249A CN112367279A CN 112367279 A CN112367279 A CN 112367279A CN 202011188249 A CN202011188249 A CN 202011188249A CN 112367279 A CN112367279 A CN 112367279A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/15—Interconnection of switching modules
- H04L49/1507—Distribute and route fabrics, e.g. sorting-routing or Batcher-Banyan
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/74—Address processing for routing
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/10—Packet switching elements characterised by the switching fabric construction
- H04L49/109—Integrated on microchip, e.g. switch-on-chip
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Abstract
The invention relates to a routing method and a system based on a two-dimensional mesh structure multi-core chipset. The method comprises the following steps: acquiring a source chip address, a destination chip address and a destination node address of a message to be transmitted; judging whether the destination chip address is the same as the source chip address to obtain a first judgment result; if the first judgment result is yes, routing a node router corresponding to the destination node address in a chip corresponding to the source chip address to finish the transmission of the message to be transmitted; if the first judgment result is negative, routing the chip corresponding to the destination chip address, and routing the node router corresponding to the destination node address in the chip corresponding to the destination chip address to complete the transmission of the message to be transmitted. The invention realizes the consistency of the communication method between the multi-core chips and the network-on-chip communication method in the multi-core chips, shortens the delay of messages during cross-chip transmission and reduces the development cost of system hardware and software.
Description
Technical Field
The invention relates to the technical field of communication, in particular to a routing method and a routing system based on a two-dimensional mesh structure multi-core chipset.
Background
Because the frequency of the single-core chip is increased to bring excessive heat and the performance of the chip cannot be synchronously improved, the single-core chip is gradually replaced by the multi-core chip, the multi-core chip is formed by integrating a plurality of complete computing cores in one chip, and the multi-core chip utilizes the plurality of computing cores to execute tasks in parallel to improve the performance of the chip.
A Network-on-Chip (NoC) provides on-Chip communication with high bandwidth, low delay and low power consumption, and is an efficient on-Chip interconnection communication technology, a computational core is used as a node to be connected to the on-Chip Network to form an on-Chip Network structure multi-core Chip, the on-Chip Network structure multi-core Chip adopts message communication, and an on-Chip router is used for forwarding a message, but the existing on-Chip Network based multi-core Chip communication method has poor expandability; because the network is not layered, when the message is transmitted across chips, the message needs to pass through the network on chip of a plurality of chips, so that the passing route nodes are excessive, and the message delay is large; and the number of message header slices used for routing is uncertain, and when the number of crossed chips is large, more message header slices are needed, and the communication overhead is large. Therefore, the prior art has the defects of delay of messages during cross-chip transmission and high development cost of system hardware and software.
Disclosure of Invention
The invention aims to provide a routing method and a system based on a two-dimensional mesh structure multi-core chipset, which realize the consistency of a communication method between multi-core chips and a network-on-chip communication method in the multi-core chips, shorten the delay of messages during cross-chip transmission and reduce the development cost of system hardware and software.
In order to achieve the purpose, the invention provides the following scheme:
a routing method based on a two-dimensional mesh structure multi-core chipset comprises the following steps:
acquiring a source chip address, a destination chip address and a destination node address of a message to be transmitted;
judging whether the destination chip address is the same as the source chip address or not to obtain a first judgment result;
if the first judgment result is yes, routing a node router corresponding to the destination node address in a chip corresponding to the source chip address to finish the transmission of the message to be transmitted;
and if the first judgment result is negative, routing the chip corresponding to the destination chip address, and routing the node router corresponding to the destination node address in the chip corresponding to the destination chip address to finish the transmission of the message to be transmitted.
Optionally, the routing a node router corresponding to the destination node address in a chip corresponding to the source chip address to complete transmission of the packet to be transmitted specifically includes:
filling the destination node address to a second destination address, wherein the second destination address is empty initially;
and routing the router corresponding to the destination node address in the chip corresponding to the source chip address according to the second destination address through the network on chip to finish the transmission of the message to be transmitted.
Optionally, the routing is performed on a chip corresponding to the destination chip address, and a node router corresponding to the destination node address is routed in the chip corresponding to the destination chip address, so as to complete transmission of the packet to be transmitted, specifically:
the message to be transmitted is transmitted to a board level network;
routing a chip corresponding to the destination chip address;
and routing the node router corresponding to the destination node address in the chip corresponding to the destination chip address to complete the transmission of the message to be transmitted on the board-level network.
Optionally, the forwarding the message to be transmitted to the board level network specifically includes:
filling a chip routing node address corresponding to the source chip address to a second destination address, wherein the second destination address is empty initially;
routing to a chip router corresponding to the chip routing node address according to the second destination address through a network on chip;
and after receiving the message to be transmitted, the chip router corresponding to the chip routing node address forwards the message to be transmitted to a board level network.
Optionally, the routing a node router corresponding to the destination node address in a chip corresponding to the destination chip address to complete transmission of the packet to be transmitted on the board level network, specifically:
filling the destination node address to a second destination address, wherein the second destination address is empty initially;
and routing the router corresponding to the destination node address in the chip corresponding to the destination chip address according to the second destination address through the network on chip to finish the transmission of the message to be transmitted on the board level network.
A routing system based on a two-dimensional mesh structure multi-core chipset comprises:
the address acquisition module is used for acquiring a source chip address, a destination chip address and a destination node address of a message to be transmitted;
the first judgment module is used for judging whether the destination chip address is the same as the source chip address to obtain a first judgment result;
a first transmission module, configured to route, in a chip corresponding to the source chip address, a node router corresponding to the destination node address if the first determination result is yes, so as to complete transmission of the packet to be transmitted;
and the second transmission module is used for routing the chip corresponding to the destination chip address if the first judgment result is negative, and routing the node router corresponding to the destination node address in the chip corresponding to the destination chip address to complete the transmission of the message to be transmitted.
Optionally, the first transmission module includes:
a first padding unit, configured to pad the destination node address to a second destination address, where the second destination address is initially empty;
and the first on-chip transmission unit is used for routing the router corresponding to the destination node address in the chip corresponding to the source chip address according to the second destination address through the network on chip to complete the transmission of the message to be transmitted.
Optionally, the second transmission module includes:
the first board level transmission unit is used for transmitting the message to be transmitted to a board level network;
the routing unit is used for routing the chip corresponding to the destination chip address;
and the second board-level transmission unit is used for routing the node router corresponding to the destination node address in the chip corresponding to the destination chip address to complete the transmission of the message to be transmitted on the board-level network.
Optionally, the first board-level transmission unit includes:
a second filling unit, configured to fill a chip routing node address corresponding to the source chip address to a second destination address, where the second destination address is initially empty;
the second on-chip transmission unit is used for routing to a chip router corresponding to the chip routing node address according to the second destination address through an on-chip network;
and the third board-level transmission unit is used for transmitting the message to be transmitted to a board-level network after the chip router corresponding to the chip routing node address receives the message to be transmitted.
Optionally, the second board-level transmission unit includes:
a third padding unit, configured to pad the destination node address to a second destination address, where the second destination address is initially empty;
and the third on-chip transmission unit is used for routing the router corresponding to the destination node address in the chip corresponding to the destination chip address according to the second destination address through the on-chip network, so as to complete the transmission of the message to be transmitted on the board-level network.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects: the invention uses the board level network to form the multi-core chip group to work cooperatively, judges whether the message to be transmitted is transmitted to other chips according to the judgment whether the source chip address and the destination chip address of the message to be transmitted are the same or not, connects a plurality of multi-core chips to realize cross-chip transmission, realizes the consistency of the communication method among the multi-core chips and the on-chip network communication method in the multi-core chips, and reduces the development cost of system hardware and software.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without inventive exercise.
Fig. 1 is a flowchart of a routing method based on a two-dimensional mesh structure multi-core chipset according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a message header slice of a message to be transmitted according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a two-dimensional mesh-structured multi-core chipset according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a routing system based on a two-dimensional mesh-structured multi-core chipset according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Example 1
As shown in fig. 1, the routing method based on a two-dimensional mesh structure multi-core chipset provided in this embodiment includes:
101: and acquiring a source chip address, a destination chip address and a destination node address of the message to be transmitted.
102: and judging whether the destination chip address is the same as the source chip address to obtain a first judgment result.
103: and if the first judgment result is yes, routing the node router corresponding to the destination node address in the chip corresponding to the source chip address to finish the transmission of the message to be transmitted.
104: and if the first judgment result is negative, routing the chip corresponding to the destination chip address, and routing the node router corresponding to the destination node address in the chip corresponding to the destination chip address to finish the transmission of the message to be transmitted.
The method comprises the following steps of routing a node router corresponding to the destination node address in a chip corresponding to the source chip address to complete transmission of the message to be transmitted, specifically:
and filling the destination node address to a second destination address, wherein the second destination address is empty initially.
And routing the router corresponding to the destination node address in the chip corresponding to the source chip address according to the second destination address through the network on chip to finish the transmission of the message to be transmitted.
The routing of the chip corresponding to the destination chip address and the routing of the node router corresponding to the destination node address in the chip corresponding to the destination chip address to complete the transmission of the message to be transmitted specifically include:
and forwarding the message to be transmitted to a board level network.
And routing the chip corresponding to the destination chip address.
And routing the node router corresponding to the destination node address in the chip corresponding to the destination chip address to complete the transmission of the message to be transmitted on the board-level network.
The method for forwarding the message to be transmitted to the board level network specifically comprises the following steps:
and filling the chip routing node address corresponding to the source chip address to a second destination address, wherein the second destination address is empty initially.
And routing to a chip router corresponding to the chip routing node address according to the second destination address through a network on chip, wherein the chip router corresponding to the chip routing node address is used for communicating with chip routers corresponding to chip routing node addresses of other chips.
And after receiving the message to be transmitted, the chip router corresponding to the chip routing node address forwards the message to be transmitted to a board level network.
The method comprises the following steps of routing a node router corresponding to the destination node address in a chip corresponding to the destination chip address to complete transmission of a message to be transmitted on the board level network, specifically:
and filling the destination node address to a second destination address, wherein the second destination address is empty initially.
And routing the router corresponding to the destination node address in the chip corresponding to the destination chip address according to the second destination address through the network on chip to finish the transmission of the message to be transmitted on the board level network.
The embodiment also provides a routing method based on a multi-core chipset with a two-dimensional mesh structure in an actual application process, as shown in fig. 2, a structure of a header slice of a packet to be transmitted is provided, where the header slice for routing in the packet includes a source address rewritten by software, a destination address 1 rewritten by software, and a destination address 2 (a second destination address) rewritten by hardware. The source address and the destination address 1 rewritten by software are composed of a chip address and a node address, and the destination address 2 rewritten by hardware only contains the node address. When a processor on a routing node initiates communication, software fills a source address and a destination address 1 of a message header slice, and a hardware circuit automatically fills a destination address 2 according to a chip address of the destination address 1 until the routing information of the message is filled. The message is then sent to the network for transmission to the destination node via inter-node and inter-chip routers.
Fig. 3 is a schematic structural diagram of a two-dimensional mesh-structured multi-core chipset according to an embodiment of the present invention, and referring to fig. 3, the communication architecture includes two networks, where a router of one network and a physical connection between routers are both implemented in a chip to form a common two-dimensional mesh-structured network-on-chip, and a router in the network-on-chip is connected to different functional units through dedicated network interfaces, where the functional units may be processing cores, memory controllers, or dedicated computing nodes; the router of another duplicate network is realized in a chip, and the physical connection between the routers is realized on a printed circuit board, so that a two-dimensional mesh structure network is formed. The two-dimensional mesh structure board level network is utilized to realize data communication of a multi-core chipset consisting of a plurality of chips on the printed circuit board.
The router is the basis for forming a network communication architecture, the router in the scheme is divided into two types, one type is called a node router, and a common network-on-chip router structure is adopted and used for forming a network-on-chip in a chip; the other is called a chip router, which is used for forming a board-level network of a chip set to realize cross-chip transmission of messages. Because the data transmission of the printed circuit board level is different from the data transmission in the chip, and has higher requirements on the aspects of data bit width, check sum signal integrity and the like, the chip router supports a corresponding board level data transmission protocol, but in the view of a message routing principle, the chip router can be regarded as a combination of 2 routers, on one hand, the chip router and the adjacent node router in the chip form a network on chip, and on the other hand, the chip router and the chip router of the adjacent chip form a board level network. When processing network-on-chip communication, the chip router observes the node address of the message header slice, and when processing board-level network communication, the chip router observes the chip address of the message header slice. Typically, the overhead of implementing a board level communication protocol is large, so each chip usually contains only one chip router.
And according to a common XY routing algorithm of a two-dimensional mesh structure, the node router of each chip and the chip routers of all chip sets are addressed according to two-dimensional coordinates respectively. The chip router is connected to the network-on-chip and the board-level network at the same time, so that the chip router has a chip address and a node address at the same time; the node router is provided with only node addresses.
Where NR denotes a Node Router (NR), and CR denotes a Chip Router (CR). The chip router has 2 coordinates, one is the node coordinate and one is the chip coordinate. Taking the chip router of chip 00 as an example, the node coordinate is 33, and the chip coordinate is 00.
Assuming that a message is routed from a source chip coordinate 00, a source node coordinate 12 to a destination chip coordinate 32 and a destination node coordinate 20, the whole routing process is as follows:
since the destination chip coordinate 32 is not equal to the source chip coordinate 00, indicating that the packet needs to be transmitted across chips, the node hardware automatically fills the destination address 2 of the packet header slice into the chip router node coordinate 33 of the chip 00.
The message is routed to the chip router through the network on chip of chip 00.
The chip router of the chip 00 judges that the target chip coordinate 32 of the target address 1 is different from the chip coordinate 00 of the chip router, and judges that the message is a cross-chip message, namely the message is sent to a board level network.
The message is routed in the board level network to the destination chip coordinate 32 by depending on the destination chip coordinate of the destination address 1 through the board level network.
After receiving the message, the chip router of the chip 32 compares the message with the chip coordinate 32 of the chip, finds that the message belongs to the chip 32, immediately and automatically copies the node coordinate 20 of the destination address 1 to the destination address 2, and simultaneously sends the message to the network on chip.
The message is routed through the network on chip of the chip 32 to the destination address 20, until the message transmission is complete.
As shown in fig. 4, this embodiment further provides a routing system based on a two-dimensional mesh structure multi-core chipset, corresponding to the routing method based on a two-dimensional mesh structure multi-core chipset, where the routing system includes:
the address obtaining module a1 is configured to obtain a source chip address, a destination chip address, and a destination node address of a packet to be transmitted.
The first determining module a2 is configured to determine whether the destination chip address is the same as the source chip address, so as to obtain a first determination result.
A first transmission module a3, configured to, if the first determination result is yes, route the node router corresponding to the destination node address in the chip corresponding to the source chip address, and complete transmission of the packet to be transmitted.
And a second transmission module a4, configured to route the chip corresponding to the destination chip address if the first determination result is negative, and route the node router corresponding to the destination node address in the chip corresponding to the destination chip address, so as to complete transmission of the packet to be transmitted.
As an optional implementation, the first transmission module includes:
a first padding unit, configured to pad the destination node address to a second destination address, where the second destination address is initially empty.
And the first on-chip transmission unit is used for routing the router corresponding to the destination node address in the chip corresponding to the source chip address according to the second destination address through the network on chip to complete the transmission of the message to be transmitted.
As an optional implementation, the second transmission module includes:
and the first board-level transmission unit is used for transmitting the message to be transmitted to a board-level network.
And the routing unit is used for routing the chip corresponding to the destination chip address.
And the second board-level transmission unit is used for routing the node router corresponding to the destination node address in the chip corresponding to the destination chip address to complete the transmission of the message to be transmitted on the board-level network.
As an optional implementation manner, the first board-level transmission unit includes:
and the second filling unit is used for filling the chip routing node address corresponding to the source chip address to a second destination address, and the second destination address is empty initially.
And the second on-chip transmission unit is used for routing to the chip router corresponding to the chip routing node address according to the second destination address through the on-chip network.
And the third board-level transmission unit is used for transmitting the message to be transmitted to a board-level network after the chip router corresponding to the chip routing node address receives the message to be transmitted.
As an optional implementation manner, the second board-level transmission unit includes:
and the third filling unit is used for filling the destination node address to a second destination address, and the second destination address is empty initially.
And the third on-chip transmission unit is used for routing the router corresponding to the destination node address in the chip corresponding to the destination chip address according to the second destination address through the on-chip network, so as to complete the transmission of the message to be transmitted on the board-level network.
In the embodiment, the multi-core chip set is formed to work cooperatively by using the special board-level network, and the multi-core chips are connected by using the high-speed board-level communication protocol, so that cross-chip transmission is realized, the consistency of a communication method among the multi-core chips and a network-on-chip communication method in the multi-core chips is realized, and the development cost of system hardware and software is reduced.
Example 2:
after the multi-core chipset communication system in embodiment 1 is constructed, this embodiment provides a more detailed method for efficiently routing packets between any nodes:
step 1: when a processor on the source routing node initiates a communication, the software populates the source and destination addresses 1 of the slice of the header.
Step 2: the source address comprises a source chip address and a source node address, and the destination address comprises a destination chip address and a destination node address.
And step 3: then the hardware circuit of the source node judges whether the destination chip address is the same as the source chip address, if so, the node address of the destination address 1 is copied to the destination address 2, and the step 4 is entered; if not, the destination address 2 is filled as the node address of the chip router, and the step 5 is entered.
And 4, step 4: the message is routed to the destination node through the network on chip according to the destination address 2, and the communication is completed.
And 5: the message is routed to a destination node through the network on chip according to the destination address 2, and the destination node at this time is a chip router.
Step 6: after receiving the message, the chip router finds that the chip address contained in the destination address 1 is inconsistent with the chip address of the chip router, transfers the message to a board level network, and then utilizes the chip address of the destination address 1 to route the message to the chip router of the destination chip through the board level network.
And 7: after receiving the message, the chip router of the destination chip copies the node address of the destination address 1 to the destination address 2, and transfers the message to the network on chip, and then utilizes the node address of the destination address 2 to route to the destination node of the destination chip through the network on chip, until the routing communication is finished.
In the embodiment, the multi-core chip set is formed to work cooperatively by using the special board-level network, and the multi-core chips are connected by using the high-speed board-level communication protocol, so that cross-chip transmission is realized, the consistency of a communication method among the multi-core chips and a network-on-chip communication method in the multi-core chips is realized, and the development cost of system hardware and software is reduced.
From the technical implementation perspective, the network-on-chip and the board level network may adopt other network structures such as a Ring structure, besides the two-dimensional mesh structure, and the routing algorithms corresponding to different network structures are different, and the routing scheme proposed in this patent may be modified for the two-dimensional mesh structure and may be used for communication of multi-core chipsets of other structures.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The principles and embodiments of the present invention have been described herein using specific examples, which are provided only to help understand the method and the core concept of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed. In view of the above, the present disclosure should not be construed as limiting the invention.
Claims (10)
1. A routing method based on a two-dimensional mesh structure multi-core chipset is characterized by comprising the following steps:
acquiring a source chip address, a destination chip address and a destination node address of a message to be transmitted;
judging whether the destination chip address is the same as the source chip address or not to obtain a first judgment result;
if the first judgment result is yes, routing a node router corresponding to the destination node address in a chip corresponding to the source chip address to finish the transmission of the message to be transmitted;
and if the first judgment result is negative, routing the chip corresponding to the destination chip address, and routing the node router corresponding to the destination node address in the chip corresponding to the destination chip address to finish the transmission of the message to be transmitted.
2. The routing method according to claim 1, wherein the node router corresponding to the destination node address is routed in the chip corresponding to the source chip address to complete transmission of the packet to be transmitted, specifically:
filling the destination node address to a second destination address, wherein the second destination address is empty initially;
and routing the router corresponding to the destination node address in the chip corresponding to the source chip address according to the second destination address through the network on chip to finish the transmission of the message to be transmitted.
3. The routing method based on the two-dimensional mesh-structure multi-core chipset according to claim 1, wherein the routing is performed on a chip corresponding to the destination chip address, and a node router corresponding to the destination node address is routed in a chip corresponding to the destination chip address, so as to complete transmission of the packet to be transmitted, specifically:
the message to be transmitted is transmitted to a board level network;
routing a chip corresponding to the destination chip address;
and routing the node router corresponding to the destination node address in the chip corresponding to the destination chip address to complete the transmission of the message to be transmitted on the board-level network.
4. The routing method according to claim 3, wherein the forwarding of the packet to be transmitted to a board level network specifically comprises:
filling a chip routing node address corresponding to the source chip address to a second destination address, wherein the second destination address is empty initially;
routing to a chip router corresponding to the chip routing node address according to the second destination address through a network on chip;
and after receiving the message to be transmitted, the chip router corresponding to the chip routing node address forwards the message to be transmitted to a board level network.
5. The routing method based on the two-dimensional mesh-structure multi-core chipset according to claim 3, wherein the node router corresponding to the destination node address is routed in the chip corresponding to the destination chip address to complete transmission of the packet to be transmitted on the board level network, specifically:
filling the destination node address to a second destination address, wherein the second destination address is empty initially;
and routing the router corresponding to the destination node address in the chip corresponding to the destination chip address according to the second destination address through the network on chip to finish the transmission of the message to be transmitted on the board level network.
6. A routing system based on a two-dimensional mesh structure multi-core chipset is characterized by comprising the following components:
the address acquisition module is used for acquiring a source chip address, a destination chip address and a destination node address of a message to be transmitted;
the first judgment module is used for judging whether the destination chip address is the same as the source chip address to obtain a first judgment result;
a first transmission module, configured to route, in a chip corresponding to the source chip address, a node router corresponding to the destination node address if the first determination result is yes, so as to complete transmission of the packet to be transmitted;
and the second transmission module is used for routing the chip corresponding to the destination chip address if the first judgment result is negative, and routing the node router corresponding to the destination node address in the chip corresponding to the destination chip address to complete the transmission of the message to be transmitted.
7. The routing system according to claim 6, wherein the first transmission module comprises:
a first padding unit, configured to pad the destination node address to a second destination address, where the second destination address is initially empty;
and the first on-chip transmission unit is used for routing the router corresponding to the destination node address in the chip corresponding to the source chip address according to the second destination address through the network on chip to complete the transmission of the message to be transmitted.
8. The routing system according to claim 6, wherein the second transmission module comprises:
the first board level transmission unit is used for transmitting the message to be transmitted to a board level network;
the routing unit is used for routing the chip corresponding to the destination chip address;
and the second board-level transmission unit is used for routing the node router corresponding to the destination node address in the chip corresponding to the destination chip address to complete the transmission of the message to be transmitted on the board-level network.
9. The routing system according to claim 8, wherein the first board-level transmission unit comprises:
a second filling unit, configured to fill a chip routing node address corresponding to the source chip address to a second destination address, where the second destination address is initially empty;
the second on-chip transmission unit is used for routing to a chip router corresponding to the chip routing node address according to the second destination address through an on-chip network;
and the third board-level transmission unit is used for transmitting the message to be transmitted to a board-level network after the chip router corresponding to the chip routing node address receives the message to be transmitted.
10. The routing system according to claim 8, wherein the second board-level transmission unit comprises:
a third padding unit, configured to pad the destination node address to a second destination address, where the second destination address is initially empty;
and the third on-chip transmission unit is used for routing the router corresponding to the destination node address in the chip corresponding to the destination chip address according to the second destination address through the on-chip network, so as to complete the transmission of the message to be transmitted on the board-level network.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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