CN112367066A - Signal conditioning system and method applied to non-polar dual bus - Google Patents
Signal conditioning system and method applied to non-polar dual bus Download PDFInfo
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Abstract
The invention provides a signal conditioning system and a method applied to a non-polar dual bus, wherein a rectifying circuit rectifies a first signal in a first bus and a second signal in a second bus to obtain a third signal, the level of the third signal is equal to the absolute value of the level difference between the first signal and the second signal, a reference voltage circuit samples the third signal to obtain a high-level signal of the third signal, and a reference voltage signal is obtained according to the high-level signal.
Description
Technical Field
The present invention relates to the field of signal conditioning technologies, and in particular, to a system and a method for conditioning a signal applied to a non-polar dual bus.
Background
The double-bus is a technology that a power supply line and a signal line are combined into one, and signals and power supply share one bus. No polarity means no positive or negative. The non-polarity dual bus is the two buses which can ensure normal communication no matter the two buses are connected in the positive direction and the reverse direction.
As shown in fig. 1 and 2, the non-polar dual bus system employs a dual-power-squared version of Vbus _ H and Vbus _ L. Ideally, the voltage difference between the two power supply buses Bus1 and Bus2 is a square wave. As shown in fig. 1, the non-polar dual Bus system allows the Bus1 to have a level higher than the level of Bus2 with Bus2 being the reference ground, as shown in fig. 2, and allows the Bus2 to have a level higher than the level of Bus1 with Bus1 being the reference ground.
As shown in FIG. 3, according to the absolute value of the difference between Bus1 and Bus2, | Bus1-Bus2 |, a digital signal with a constant amplitude and a variation trend opposite to | Bus1-Bus2 | is obtained, and the process is called signal conditioning. However, the conventional signal conditioning method is easy to cause errors in signal conditioning results, and further output wrong signals to cause misoperation.
Disclosure of Invention
Accordingly, the present invention provides a signal conditioning system and method applied to a non-polar dual bus to reduce errors of signal conditioning results.
In order to achieve the purpose, the invention provides the following technical scheme:
a signal conditioning system for application to a non-polar dual bus, the non-polar dual bus comprising a first bus for transmitting a first signal and a second bus for transmitting a second signal, the signal conditioning system comprising:
the rectifying circuit is used for rectifying the first signal and the second signal to obtain a third signal, and the level of the third signal is equal to the absolute value of the level difference value of the first signal and the second signal;
the reference voltage circuit is used for sampling the third signal to obtain a high-level signal of the third signal and obtaining a reference voltage signal according to the high-level signal, wherein the reference voltage signal is equal to the average value of the high-level signal and a low-level signal of the third signal;
and the comparator is used for comparing the third signal with the reference voltage signal to obtain a fourth signal, wherein the fourth signal is a digital signal, and the fourth signal changes along with the change of the third signal. Optionally, the reference voltage circuit includes a sampling unit, a first processing unit, and a second processing unit;
the sampling unit is used for sampling a high-level signal in the third signal;
the first processing unit is used for obtaining a low level signal of the third signal according to the high level signal, obtaining a first reference current and a second reference current according to the low level signal, and transmitting the first reference current and the second reference current to the second processing unit;
the second processing unit is used for obtaining a reference voltage signal according to the high level signal, the first reference current and the second reference current.
Optionally, the second processing unit includes a second error amplifier, fourth to twelfth transistors, a second resistor, and a third resistor; the first processing unit includes a third error amplifier, thirteenth to seventeenth transistors, and a fourth resistor;
a first input end of the second error amplifier inputs a high-level signal in the third signal, an output end of the second error amplifier is connected with gates of a fourth transistor, a fifth transistor and a sixth transistor, and a second input end of the second error amplifier is connected with a second end of the fourth transistor;
first ends of the fourth transistor, the fifth transistor, the sixth transistor, the eleventh transistor and the twelfth transistor are connected with a reference voltage end, and a second end of the fourth transistor is connected with a first end of a second resistor; a second end of the second resistor, a second end of the third resistor, a second end of the seventh transistor, a second end of the eighth transistor, a second end of the ninth transistor and a second end of the tenth transistor are grounded;
a second end of the fifth transistor is connected with a first end of the seventh transistor, and a second end of the sixth transistor is connected with a first end of the ninth transistor; a gate of the seventh transistor is connected to a gate of the eighth transistor, and a first terminal of the seventh transistor is connected to the gate of the seventh transistor; a gate of the eleventh transistor is connected to a second terminal of the eleventh transistor, and a second terminal of the eleventh transistor is connected to a first terminal of the tenth transistor and a first terminal of the eighth transistor
A gate of the twelfth transistor is connected to a gate of the eleventh transistor; a second end of the twelfth transistor is connected with a first end of the third resistor; a gate of the ninth transistor is connected to a first end of the ninth transistor, and a gate of the ninth transistor is connected to a gate of the tenth transistor;
a first input end of the third error amplifier inputs a low-level signal in the third signal, an output end of the third error amplifier is connected with gates of a thirteenth transistor, a fourteenth transistor and a fifteenth transistor, and a second input end of the third error amplifier is connected with a second end of the thirteenth transistor;
first ends of the thirteenth transistor, the fourteenth transistor and the fifteenth transistor are connected with the reference voltage end, a second end of the thirteenth transistor is connected with a first end of the fourth resistor, and second ends of the fourth resistor, the sixteenth transistor and the seventeenth transistor are grounded;
the second end of the fourteenth transistor is connected to the first end of the sixteenth transistor, the gate of the sixteenth transistor is connected to the first end of the sixteenth transistor and the gate of the seventeenth transistor, the second end of the fifteenth transistor is connected to the first end of the seventh transistor, and the first end of the seventeenth transistor is connected to the first end of the ninth transistor.
Optionally, the power supply further comprises a voltage dividing circuit, wherein the voltage dividing circuit is located between the rectifying circuit and the reference voltage circuit;
the voltage division circuit is used for reducing the level of a third signal output by the rectifying circuit to k times, wherein k is more than 0 and less than 1.
Optionally, a level conversion circuit is further included;
the level conversion circuit is used for carrying out level conversion on the fourth signal to obtain a fifth signal, wherein the amplitude of the fifth signal is different from that of the fourth signal, but the fifth signal changes along with the fourth signal in phase.
Optionally, the power supply further comprises a sampling filter circuit, wherein the sampling filter circuit is located between the rectifying circuit and the reference voltage circuit;
the sampling filter circuit is used for filtering a third signal before sampling.
Optionally, an anti-jitter circuit is further included;
the jitter elimination circuit is used for obtaining a plurality of positive pulse signals according to the rising edge and the falling edge of the fourth signal, enabling the sixth signal to be equal to the fourth signal after the first positive pulse signal is obtained, and enabling the sixth signal to be kept unchanged in a later preset time so as to eliminate the influence of jitter in the fourth signal on the sixth signal.
A signal conditioning method applied to a non-polar dual bus comprises the following steps:
rectifying the first signal and the second signal through a rectifying circuit to obtain a third signal, wherein the level of the third signal is equal to the absolute value of the level difference value of the first signal and the second signal;
sampling a third signal through a reference voltage circuit to obtain a high-level signal of the third signal, and obtaining a reference voltage signal according to the high-level signal, wherein the reference voltage signal is equal to the average value of the high-level signal and a low-level signal of the third signal;
and comparing the third signal with the reference voltage signal through a comparator to obtain a fourth signal, wherein the fourth signal is a digital signal and changes along with the change of the third signal. Optionally, the sampling a third signal by a reference voltage circuit to obtain a high-level signal of the third signal, and obtaining a reference voltage signal according to the high-level signal includes:
sampling a high-level signal in the third signal through a sampling unit;
obtaining a low level signal of the third signal according to the high level signal through a first processing unit, and obtaining a first reference current and a second reference current according to the low level signal;
and obtaining a reference voltage signal according to the high level signal, the first reference current and the second reference current through a second processing unit.
Optionally, before the sampling of the third signal by the reference voltage circuit to obtain a high-level signal of the third signal, the method further includes:
and the level of a third signal output by the rectifying circuit is reduced to k times through a voltage division circuit, wherein k is more than 0 and less than 1.
Optionally, after obtaining the fourth signal, the method further includes:
and performing level conversion on the fourth signal through a level conversion circuit to obtain a fifth signal, wherein the amplitude of the fifth signal is different from that of the fourth signal, but the fifth signal changes in phase with the fourth signal.
Optionally, before sampling the third signal, the method further includes:
filtering the third signal.
Optionally, after obtaining the fourth signal, the method further includes:
obtaining a plurality of positive pulse signals according to the rising edge and the falling edge of the fourth signal;
and after the first positive pulse signal is obtained, making the sixth signal equal to the fourth signal, and keeping the sixth signal unchanged in a later preset time so as to eliminate the influence of jitter in the fourth signal on the sixth signal.
Compared with the prior art, the technical scheme provided by the invention has the following advantages:
the invention provides a signal conditioning system and a method applied to a non-polar dual bus.A rectifying circuit rectifies a first signal in a first bus and a second signal in a second bus to obtain a third signal, the level of the third signal is equal to the absolute value of the level difference between the first signal and the second signal, a reference voltage circuit samples the third signal to obtain a high-level signal of the third signal, and a reference voltage signal is obtained according to the high-level signal.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a timing diagram of one of the Bus1 and Bus2 signals in a non-polar dual Bus;
FIG. 2 is a timing diagram of another Bus1 and Bus2 signal in a non-polar dual Bus;
FIG. 3 is a timing diagram of the | Bus1-Bus2 | signals and the output signals of the conditioning circuit according to the Bus1 and Bus2 signals in the non-polar dual Bus;
FIG. 4 is a graph illustrating a comparison of a reference voltage signal VREF with a high level signal Vbus _ H and a low level signal Vbus _ L obtained in a conventional signal conditioning method;
fig. 5 is a schematic structural diagram of a signal conditioning system according to an embodiment of the present invention;
fig. 6 is a timing diagram of the third signal VB according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a reference voltage circuit according to an embodiment of the present invention;
FIG. 8 is a circuit diagram of a sampling unit in a reference voltage circuit according to an embodiment of the present invention;
FIG. 9 is a circuit diagram of a first processing unit in a reference voltage circuit according to an embodiment of the present invention;
FIG. 10 is a circuit diagram of a second processing unit in the reference voltage circuit according to an embodiment of the present invention;
FIG. 11 is a graph illustrating a comparison of a reference voltage signal VREF with a high level signal Vbus _ H and a low level signal Vbus _ L obtained in a signal conditioning system according to an embodiment of the present invention;
fig. 12 is a schematic structural diagram of a signal conditioning system according to another embodiment of the present invention;
fig. 13 is a schematic structural diagram of a signal conditioning system according to another embodiment of the present invention;
fig. 14 is a schematic structural diagram of a signal conditioning system according to another embodiment of the present invention;
fig. 15 is a schematic structural diagram of a signal conditioning system according to another embodiment of the present invention;
fig. 16 is a schematic structural diagram of a signal conditioning system according to another embodiment of the present invention;
fig. 17 is a timing diagram of signals in a debounce circuit according to an embodiment of the present invention;
fig. 18 is a schematic circuit diagram of a SHOT signal generated in the debounce circuit according to an embodiment of the present invention;
FIG. 19 is a timing diagram of signals at each node in the circuit of FIG. 18;
fig. 20 is a schematic diagram of a partial circuit structure of the jitter elimination circuit for generating the OUT1 signal according to an embodiment of the present invention;
FIG. 21 is a timing diagram of signals at each node in the circuit of FIG. 20;
fig. 22 is a flowchart of a signal conditioning method according to an embodiment of the present invention.
Detailed Description
As background, conventional signal conditioning methods are prone to signal conditioning errors. In the conventional signal conditioning method, Bus1 and Bus2 are rectified by a rectifier bridge to obtain a signal VB, a high-level signal Vbus _ H of the signal VB is sampled by a reference voltage circuit, a fixed value is subtracted on the basis of the Vbus _ H to obtain a reference voltage signal VREF, the VB and the VREF are compared by a comparator to obtain a high-voltage logic signal, for example, when the Vbus _ H is greater than the VREF, a logic 0 is output, when the Vbus _ L is less than the VREF, a logic 1 is output, and then the high-voltage logic signal is converted into a logic signal with a required voltage amplitude by a level conversion circuit.
However, the inventors have found that the reason why the signal conditioning result is prone to errors is mainly that the reference voltage signal VREF is not in the middle of Vbus _ H and Vbus _ L, and as shown in fig. 4, a curve V is obtained by subtracting a fixed value from Vbus _ HREF1, subtracting another fixed value to get curves VREF2, … …. However, this method generates a reference voltage signal VREF that is not exactly midway between Vbus _ H and Vbus _ L over the full signal range. At this time, Vbus _ H and Vbus _ L are closer to VREF, and therefore, it is easier for someone to trigger the comparator by mistake, and if Vbus _ H and VREF are closer, the comparator is likely to output a wrong result. In summary, VREF1, VREF2, and … … are obtained by setting a fixed difference value with Vbus _ H or Vbus _ L, so that the risk of false triggering of the comparator is high, and false signal conditioning results are more likely to occur.
In view of the above, the present invention provides a signal conditioning system and method applied to a non-polar dual bus, so as to overcome the above problems in the prior art, the non-polar dual bus includes a first bus and a second bus, the first bus is used for transmitting a first signal, the second bus is used for transmitting a second signal, the signal conditioning system includes:
the rectifying circuit is used for rectifying the first signal and the second signal to obtain a third signal, and the level of the third signal is equal to the absolute value of the level difference value of the first signal and the second signal;
the reference voltage circuit is used for sampling the third signal to obtain a high-level signal of the third signal and obtaining a reference voltage signal according to the high-level signal, wherein the reference voltage signal is equal to the average value of the high-level signal and the low-level signal in the third signal;
and the comparator is used for comparing the third signal with the reference voltage signal to obtain a fourth signal, the fourth signal is a digital signal, and the fourth signal changes along with the change of the third signal. The invention provides a signal conditioning system and a method applied to a non-polar dual bus.A rectifying circuit rectifies a first signal in a first bus and a second signal in a second bus to obtain a third signal, the level of the third signal is equal to the absolute value of the level difference between the first signal and the second signal, a reference voltage circuit samples the third signal to obtain a high-level signal of the third signal, and a reference voltage signal is obtained according to the high-level signal.
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, so that the above is the core idea of the present invention, and the above objects, features and advantages of the present invention can be more clearly understood. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
An embodiment of the present invention provides a signal conditioning system applied to a non-polar dual Bus, where the non-polar dual Bus includes a first Bus and a second Bus, the first Bus is used to transmit a first signal Bus1, and the second Bus is used to transmit a second signal Bus2, as shown in fig. 5, the signal conditioning system includes:
the rectifying circuit 10 is used for rectifying the first signal Bus1 and the second signal Bus2 to obtain a third signal VB, wherein the level of the third signal VB is equal to the absolute value of the level difference value of the first signal Bus1 and the second signal Bus 2;
the reference voltage circuit 11 is configured to sample the third signal VB to obtain a high level signal Vbus _ H of the third signal VB, and obtain a reference voltage signal VREF according to the high level signal Vbus _ H, where the reference voltage signal VREF is equal to an average value of a low level signal Vbus _ L in the high level signal Vbus _ H and the third signal VB;
and the comparator 12 is used for comparing the third signal VB with the reference voltage signal VREF to obtain a fourth signal OUT0, the fourth signal OUT0 is a digital signal, and the fourth signal OUT0 changes along with the change of the third signal VB.
That is, the rectifier circuit 10 is connected to the first Bus and the second Bus in the non-polar dual Bus, the rectifier circuit 10 rectifies the first signal Bus1 and the second signal Bus2 to obtain the third signal VB, the level of the third signal VB is equal to the absolute value of the level difference between the first signal Bus1 and the second signal Bus2, and the obtained third signal VB is shown in fig. 6 by taking Bus1 and Bus2 shown in fig. 1 as an example.
Then, the reference voltage circuit 11 samples the third signal VB to obtain a high level signal Vbus _ H of the third signal VB, and obtains a reference voltage signal VREF according to the high level signal Vbus _ H, where the reference voltage signal VREF is equal to an average value of a low level signal Vbus _ L in the high level signal Vbus _ H and the third signal VB; the comparator 12 compares the third signal VB with the reference voltage signal VREF to obtain a fourth signal OUT0, the fourth signal OUT0 is a digital signal, and the fourth signal OUT0 varies with the variation of the third signal VB. If VB > VREF, OUT0 is 0, and if VB < VREF, OUT0 is 1, that is, the fourth signal OUT0 is a digital signal composed of 0 and 1.
It should be noted that the rectifying circuit 10 in the embodiment of the present invention may be a rectifying bridge composed of four diodes, and the comparator 12 may be a conventional comparator, which is not described herein again.
In some embodiments of the present invention, as shown in fig. 7, the reference voltage circuit 11 includes a sampling unit 111, a first processing unit 112, and a second processing unit 113.
The sampling unit 111 is configured to sample a high level signal Vbus _ H in the third signal VB; the first processing unit 112 is configured to obtain a low level signal Vbus _ L according to the high level signal Vbus _ H, obtain a first reference current iREF1 and a second reference current iREF2 according to the low level signal Vbus _ L, and transmit the first reference current iREF1 and the second reference current iREF2 to the second processing unit 114; the second processing unit 114 is used for obtaining a reference voltage signal VREF according to the high-level signal Vbus _ H, the first reference current iREF1 and the second reference current iREF 2.
In some embodiments of the present invention, as shown in fig. 8, the sampling unit 111 may include an operational amplifier, and the input terminal of the operational amplifier inputs the third signal VB. Since the output stage of the operational amplifier is very charged and very weak discharged, the output of the operational amplifier can track the high level Vbus _ H of the third signal VB at any time during the high level of the third signal VB, i.e. the output of the operational amplifier will output the high level Vbus _ H of the third signal VB. During other levels of the third signal VB, the output terminal of the operational amplifier still outputs the high level Vbus _ H of the third signal VB because the operational amplifier has a weak discharging capability. Of course, the invention is not limited thereto, and in other embodiments, the sampling unit 111 may use other devices for sampling.
In some embodiments of the present invention, as shown in fig. 9, the first processing unit 113 includes a voltage conversion unit, a third error amplifier AP3, thirteenth to seventeenth transistors M13 to M17, and a fourth resistor R4. Since the difference between the high level Vbus _ H and the low level Vbus _ L is known, the low level Vbus _ L may be converted from the high level Vbus _ H by the voltage conversion unit and input to the third error amplifier AP3, so that the first processing unit 113 outputs a first reference current iREF1 and a second reference current iREF2, where iREF1 ═ k1 ═ Vbus _ L/R, iREF2 ═ k2 ═ Vbus _ L/R, where k1 and k2 are current ratios, alternatively k1 ═ 0.5, and k2 ═ 1.
As shown in fig. 10, the second processing unit 114 includes a second error amplifier AP2, a fourth transistor M4 to a twelfth transistor M12, a second resistor R2, and a third resistor R3, wherein resistance values of the second resistor R2, the third resistor R3, and the fourth resistor R4 are all R.
A first input terminal of the second error amplifier AP2 inputs the high level signal Vbus _ H of the third signal VB, an output terminal of the second error amplifier AP2 is connected to gates of the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6, and a second input terminal of the second error amplifier AP2 is connected to a second terminal of the fourth transistor M4;
first ends of the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the eleventh transistor M11 and the twelfth transistor M12 are connected to the reference voltage terminal VDD, and a second end of the fourth transistor M4 is connected to a first end of the second resistor R2; a second terminal of the second resistor R2, a second terminal of the third resistor R3, a second terminal of the seventh transistor M7, an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10 are grounded;
a second terminal of the fifth transistor M5 is connected to the first terminal of the seventh transistor M7, and a second terminal of the sixth transistor M6 is connected to the first terminal of the ninth transistor M9; a gate of the seventh transistor M7 is connected to a gate of the eighth transistor M8, and a first terminal of the seventh transistor M7 is connected to a gate of the seventh transistor M7; a gate of the eleventh transistor M11 is connected to the second terminal of the eleventh transistor M11, and a second terminal of the eleventh transistor M11 is connected to the first terminal of the tenth transistor M10 and the first terminal of the eighth transistor M8
A gate of the twelfth transistor M12 is connected to a gate of the eleventh transistor M11; a second terminal of the twelfth transistor M12 is connected to the first terminal of the third resistor R3; a gate of the ninth transistor M9 is connected to the first terminal of the ninth transistor M9, and a gate of the ninth transistor M9 is connected to the gate of the tenth transistor M10;
a first input terminal of the third error amplifier AP3 inputs the low level signal Vbus _ L of the third signal VB, an output terminal of the third error amplifier AP3 is connected to gates of the thirteenth transistor M13, the fourteenth transistor M14, and the fifteenth transistor M15, and a second input terminal of the third error amplifier AP3 is connected to a second terminal of the thirteenth transistor M13;
first terminals of a thirteenth transistor M13, a fourteenth transistor M14 and a fifteenth transistor M15 are connected to the reference voltage terminal VDD, a second terminal of the thirteenth transistor M13 is connected to a first terminal of a fourth resistor R4, and second terminals of a fourth resistor R4, a sixteenth transistor M16 and a seventeenth transistor M17 are grounded;
a second terminal of the fourteenth transistor M14 is connected to the first terminal of the sixteenth transistor M16, a gate of the sixteenth transistor M16 is connected to the first terminal of the sixteenth transistor M16 and the gate of the seventeenth transistor M17, a second terminal of the fifteenth transistor M15 is connected to the first terminal of the seventh transistor M7, and a first terminal of the seventeenth transistor M17 is connected to the first terminal of the ninth transistor M9.
As shown in fig. 10, after the high level signal Vbus _ H is input to the second error amplifier AP2, the fifth transistor M5 outputs a current i1, and the sixth transistor M6 outputs a current i2, wherein,
where k3 and k4 are current ratios, the values of k3 and k4 are determined by the width-to-length ratio of the fifth transistor M5 and the sixth transistor M6, and optionally, k 3-k 4-0.5.
In some embodiments, Vbus _ H ∈ [18,24], and Vbus _ L is expressed as:
when Vbus _ H < 18V, Vbus _ L is 9, and let i2-iREF2When is equal to 0, then iB0. At this time, the expression of the reference voltage signal VREF is:
when Vbus _ H is more than or equal to 18V, Vbus _ L is equal to Vbus _ H-9, and order i2-iREF2If is greater than 0, then iBIs greater than 0. At this time, the expression of the reference voltage signal VREF is:
it follows that VREF is always equal to
And will change according to the change of Vbus _ H and Vbus _ L, i.e. VREF is always located between Vbus _ H and Vbus _ L as shown in fig. 11, therefore, when comparator 12 compares third signal VB with reference voltage signal VREF, the occurrence of error can be reducedThe risk of false triggering of the comparator 12 can be reduced, and the probability of error in the signal conditioning result can be reduced.
Based on any of the above embodiments, in some embodiments of the present invention, as shown in fig. 12, the signal conditioning system further includes a voltage divider circuit 13.
Wherein, the voltage dividing circuit 13 is positioned between the rectifying circuit 10 and the reference voltage circuit 11; the voltage divider circuit 13 is used to reduce the level of the third signal VB output by the rectifier circuit 10 to k times, where 0 < k < 1. Namely, the level of the third signal VB is reduced to a range which can be borne by a low-voltage device, and then most functional circuits can be built by using the low-voltage device, so that the area of a chip where the signal conditioning system is located is reduced, and the cost is reduced.
Based on this, the reference voltage circuit 11 will sample the third signal kxvb to obtain the high level signal kxvbus _ H and the low level signal kxvbus _ L of the third signal kxvb, and obtain the reference voltage signal VREF according to the high level signal kxvbus _ H and the low level signal kxvbus _ L, where the reference voltage signal VREF is equal to the average value of the high level signal kxvbus _ H and the low level signal kxvbus _ L; and the comparator 12 is used for comparing the third signal k × VB with the reference voltage signal VREF to obtain a fourth signal OUT0, the fourth signal OUT0 is a digital signal, and the fourth signal OUT0 changes along with the change of the third signal VB.
In some embodiments of the present invention, the voltage of the third signal VB may be controlled before obtaining the fourth signal OUT0, so that the amplitude of the finally output fourth signal OUT0 meets the requirement, but the present invention is not limited thereto, and in other embodiments of the present invention, the fourth signal OUT0 may be level-converted after obtaining the fourth signal OUT0, so that the amplitude of the finally output fifth signal OUT meets the requirement.
In other embodiments of the present invention, as shown in fig. 13, the signal conditioning system further comprises a level shifter circuit 14, wherein the level shifter circuit 14 is configured to level shift the fourth signal OUT0 to obtain a fifth signal OUT having a different magnitude than the fourth signal OUT0 but varying in phase with the fourth signal OUT 0.
On the basis of any of the above embodiments, the signal conditioning system in the embodiment of the present invention further includes a sampling filter circuit, where the sampling filter circuit is located between the rectifier circuit 10 and the reference voltage current 11, and the sampling filter circuit is configured to filter the third signal VB before sampling.
In some embodiments of the present invention, as shown in fig. 14, the sampling filter circuit includes a first sampling filter circuit 15, and the first sampling filter circuit 15 is located between the voltage dividing circuit 13 and the reference voltage circuit 11; the first sampling filter circuit 15 is used for filtering the third signal VB output by the voltage dividing circuit 13 and transmitting it to the comparator 12 and the reference voltage circuit 11.
Since the non-polar dual bus is a signal line, the signal is easily interfered in the long distance transmission process, and the non-polar dual bus is a power line, the power line itself can generate some glitches or fluctuations of the transmitted signal due to the influence of the load, and therefore, the third signal VB or k × VB is noisy. Based on this, in the embodiment of the present invention, the sampling filter circuit is used to filter the third signal VB or k × VB to remove the interference signal in the third signal VB or k × VB, so as to obtain the signal VB _ OK or k × VB _ OK.
It should be noted that, in some embodiments of the present invention, the sampling filter circuit may replace the sampling unit 111 to sample the third signal VB or k × VB, so as to obtain the high-level signal Vbus _ H or k × Vbus _ H.
In other embodiments of the present invention, as shown in fig. 15, the sampling filter circuit may further include a second sampling filter circuit 18, and the second sampling filter circuit 18 is located between the rectifier circuit 10 and the reference voltage circuit 11; the second sampling filter circuit 18 is used for filtering the third signal VB output by the rectifying circuit 10 and transmitting it to the comparator 12 and the reference voltage circuit 11.
Since the non-polar dual bus is a signal line and a power line, and therefore is susceptible to interference during long-distance transmission, or generates some glitches or fluctuations due to the influence of a load, the sampling filter circuit may not be able to completely filter OUT these interference factors, and therefore, on the basis of any of the above embodiments, as shown in fig. 16, the signal conditioning system further includes a jitter elimination circuit 21 to eliminate the adverse effect of jitter in the fourth signal OUT0 on the signal conditioning result through the jitter elimination circuit 21, in order to further reduce the influence of these interference factors on the signal conditioning result.
As shown in fig. 17, the jitter elimination circuit 21 is configured to obtain a plurality of positive pulse signals SHOT according to rising and falling edges of the fourth signal OUT0, and after obtaining a first positive pulse signal, make the sixth signal OUT1 equal to the fourth signal OUT0, and make the sixth signal OUT1 constant for a preset time Td later, so as to prevent jitter in the fourth signal OUT0 from being transferred to the sixth signal OUT 1.
Because the jitter occurs immediately after the correct edge in time, the positive pulse corresponding to the correct edge occurs first and the positive pulse corresponding to the jitter factor occurs immediately after. Based on this, the jitter elimination circuit 21 sets OUT1 to OUT0 after the first positive pulse signal occurs, and then masks OUT1 from changing during a reasonable preset time Td, that is, keeps OUT1 unchanged during the preset time Td, so that the positive pulses caused by other jitter factors during the preset time Td are masked, and the correctness of the output result is ensured.
The specific value of Td may be set according to a specific application scenario, and the present invention is not limited thereto. Note that after Td, OUT1 is still equal to OUT0, such as OUT1 is equal to the high level of OUT0, until after the next positive pulse signal, OUT1 is equal to OUT0, such as OUT1 is equal to the low level of OUT 0.
It should be further noted that in some embodiments of the present invention, a plurality of positive pulse signals SHOT may be obtained according to the rising edge and the falling edge of the fourth signal OUT0 by the circuit shown in fig. 18, and the timing diagram of the signals at the respective nodes A, B, SHOT-A, SHOT-B and SHOT in the circuit shown in fig. 18 is shown in fig. 19. In some embodiments of the present invention, after obtaining the first positive pulse signal, the circuit shown in fig. 20 makes the sixth signal OUT1 equal to the fourth signal OUT0, and makes the sixth signal OUT1 constant for a predetermined time Td, and a timing diagram of signals of the respective nodes RAMP, TSN, TSP and OUT1 in the circuit shown in fig. 20 is shown in fig. 21.
Of course, the invention is not limited to this, and in other embodiments, the jitter cancellation circuit with other structures may be used to implement the jitter cancellation function.
An embodiment of the present invention further provides a signal conditioning method applied to a non-polar dual bus, which is applied to the signal conditioning system according to any of the above embodiments, and as shown in fig. 22, the signal conditioning method includes:
s101: rectifying the first signal and the second signal by a rectifying circuit to obtain a third signal, wherein the level of the third signal is equal to the absolute value of the level difference value of the first signal and the second signal;
the rectifying circuit 10 is connected to the first Bus and the second Bus in the non-polar dual Bus, the rectifying circuit 10 rectifies the first signal Bus1 and the second signal Bus2 to obtain a third signal VB, the level of the third signal VB is equal to the absolute value of the difference between the levels of the first signal Bus1 and the second signal Bus2, and the obtained third signal VB is shown in fig. 6 by taking Bus1 and Bus2 shown in fig. 1 as an example. It should be noted that the rectifier circuit 10 in the embodiment of the present invention may be a rectifier bridge composed of four diodes.
S102: sampling the third signal through a reference voltage circuit to obtain a high-level signal of the third signal, and obtaining a reference voltage signal according to the high-level signal, wherein the reference voltage signal is equal to the average value of the high-level signal and a low-level signal of the third signal;
after obtaining the third signal VB, the reference voltage circuit 11 samples the third signal VB to obtain a high level signal Vbus _ H of the third signal VB, and obtains a reference voltage signal VREF according to the high level signal Vbus _ H, where the reference voltage signal VREF is equal to an average value of the high level signal Vbus _ H and a low level signal Vbus _ L in the third signal VB.
In some embodiments of the present invention, the obtaining the high level signal Vbus _ H of the third signal VB by sampling the third signal VB through the reference voltage circuit 11, and the obtaining the reference voltage signal VREF according to the high level signal Vbus _ H includes:
sampling a high level signal Vbus _ H in the third signal VB through a sampling unit;
obtaining a low level signal Vbus _ L of a third signal VB through the first processing unit according to the high level signal Vbus _ H, obtaining a first reference current and a second reference current according to the low level signal Vbus _ L, and transmitting the first reference current and the second reference current to the second processing unit;
and obtaining a reference voltage signal VREF through the second processing unit according to the high-level signal Vbus _ H, the first reference current and the second reference current.
The specific process of obtaining the reference voltage signal VREF is the same as that of the above embodiment, and is not described herein again.
S103: and comparing the third signal with the reference voltage signal through the comparator to obtain a fourth signal, wherein the fourth signal is a digital signal and changes along with the change of the third signal.
After obtaining the reference voltage signal VREF, the comparator 12 compares the third signal VB with the reference voltage signal VREF to obtain a fourth signal OUT0, the fourth signal OUT0 is a digital signal, and the fourth signal OUT0 varies with the variation of the third signal VB. If VB > VREF, OUT0 is 0, and if VB < VREF, OUT0 is 1, that is, the fourth signal OUT0 is a digital signal composed of 0 and 1.
On the basis of any of the foregoing embodiments, in some embodiments of the present invention, before obtaining the high-level signal Vbus _ H of the third signal VB by sampling the third signal VB through the reference voltage circuit, the method further includes:
the level of a third signal VB output by the rectifying circuit is reduced to k times through the voltage division circuit, and k is more than 0 and less than 1.
Of course, the invention is not limited thereto, and in other embodiments of the invention, after obtaining the fourth signal OUT0, the method further includes:
the fourth signal OUT0 is level-converted by a level conversion circuit to obtain a fifth signal OUT having a different magnitude than the fourth signal OUT0, but which varies in phase with the fourth signal OUT 0.
On the basis of any of the foregoing embodiments, in some embodiments of the present invention, before sampling the third signal VB, the method further includes: the third signal VB is filtered.
In the embodiment of the present invention, the third signal VB may be filtered by the first application filter circuit, or the third signal VB may be filtered by the first application filter circuit and the second application filter circuit.
On the basis of any of the above embodiments, in some embodiments of the present invention, after obtaining the fourth signal OUT0, the method further includes:
obtaining a plurality of positive pulse signals SHOT according to the rising edge and the falling edge of the fourth signal OUT 0;
after the first positive pulse signal is obtained, the sixth signal OUT1 is made equal to the fourth signal OUT0, and the sixth signal OUT1 is made constant within a preset time later, so as to eliminate the effect of jitter in the fourth signal OUT 0.
As shown in fig. 17, the jitter elimination circuit 21 obtains a plurality of positive pulse signals SHOT according to the rising edge and the falling edge of the fourth signal OUT0, and after obtaining the first positive pulse signal, makes the sixth signal OUT1 equal to the fourth signal OUT0, and makes the sixth signal OUT1 constant for a preset time Td thereafter, so as to eliminate the effect of jitter in the fourth signal OUT 0.
Because the jitter occurs immediately after the correct edge in time, the positive pulse corresponding to the correct edge occurs first and the positive pulse corresponding to the jitter factor occurs immediately after. Based on this, the jitter elimination circuit 21 sets OUT1 to OUT0 after the first positive pulse signal occurs, and then masks OUT1 from changing during a reasonable preset time Td, that is, keeps OUT1 unchanged during the preset time Td, so that the positive pulses caused by other jitter factors during the preset time Td are masked, and the correctness of the output result is ensured.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (13)
1. A signal conditioning system for a non-polar dual bus, the non-polar dual bus comprising a first bus and a second bus, the first bus configured to transmit a first signal and the second bus configured to transmit a second signal, the signal conditioning system comprising:
the rectifying circuit is used for rectifying the first signal and the second signal to obtain a third signal, and the level of the third signal is equal to the absolute value of the level difference value of the first signal and the second signal;
the reference voltage circuit is used for sampling the third signal to obtain a high-level signal of the third signal and obtaining a reference voltage signal according to the high-level signal, wherein the reference voltage signal is equal to the average value of the high-level signal and a low-level signal of the third signal;
and the comparator is used for comparing the third signal with the reference voltage signal to obtain a fourth signal, wherein the fourth signal is a digital signal, and the fourth signal changes along with the change of the third signal.
2. The system of claim 1, wherein the reference voltage circuit comprises a sampling unit, a first processing unit, and a second processing unit;
the sampling unit is used for sampling a high-level signal in the third signal;
the first processing unit is used for obtaining a low level signal of the third signal according to the high level signal, obtaining a first reference current and a second reference current according to the low level signal, and transmitting the first reference current and the second reference current to the second processing unit;
the second processing unit is used for obtaining a reference voltage signal according to the high level signal, the first reference current and the second reference current.
3. The system according to claim 2, wherein the second processing unit includes a second error amplifier, fourth to twelfth transistors, a second resistor, and a third resistor; the first processing unit includes a third error amplifier, thirteenth to seventeenth transistors, and a fourth resistor;
a first input end of the second error amplifier inputs a high-level signal in the third signal, an output end of the second error amplifier is connected with gates of a fourth transistor, a fifth transistor and a sixth transistor, and a second input end of the second error amplifier is connected with a second end of the fourth transistor;
first ends of the fourth transistor, the fifth transistor, the sixth transistor, the eleventh transistor and the twelfth transistor are connected with a reference voltage end, and a second end of the fourth transistor is connected with a first end of a second resistor; a second end of the second resistor, a second end of the third resistor, a second end of the seventh transistor, a second end of the eighth transistor, a second end of the ninth transistor and a second end of the tenth transistor are grounded;
a second end of the fifth transistor is connected with a first end of the seventh transistor, and a second end of the sixth transistor is connected with a first end of the ninth transistor; a gate of the seventh transistor is connected to a gate of the eighth transistor, and a first terminal of the seventh transistor is connected to the gate of the seventh transistor; a gate of the eleventh transistor is connected to a second terminal of the eleventh transistor, and a second terminal of the eleventh transistor is connected to a first terminal of the tenth transistor and a first terminal of the eighth transistor
A gate of the twelfth transistor is connected to a gate of the eleventh transistor; a second end of the twelfth transistor is connected with a first end of the third resistor; a gate of the ninth transistor is connected to a first end of the ninth transistor, and a gate of the ninth transistor is connected to a gate of the tenth transistor;
a first input end of the third error amplifier inputs a low-level signal in the third signal, an output end of the third error amplifier is connected with gates of a thirteenth transistor, a fourteenth transistor and a fifteenth transistor, and a second input end of the third error amplifier is connected with a second end of the thirteenth transistor;
first ends of the thirteenth transistor, the fourteenth transistor and the fifteenth transistor are connected with the reference voltage end, a second end of the thirteenth transistor is connected with a first end of the fourth resistor, and second ends of the fourth resistor, the sixteenth transistor and the seventeenth transistor are grounded;
the second end of the fourteenth transistor is connected to the first end of the sixteenth transistor, the gate of the sixteenth transistor is connected to the first end of the sixteenth transistor and the gate of the seventeenth transistor, the second end of the fifteenth transistor is connected to the first end of the seventh transistor, and the first end of the seventeenth transistor is connected to the first end of the ninth transistor.
4. The system of claim 1, further comprising a voltage divider circuit between the rectifier circuit and the reference voltage circuit;
the voltage division circuit is used for reducing the level of a third signal output by the rectifying circuit to k times, wherein k is more than 0 and less than 1.
5. The system of claim 1, further comprising a level shifting circuit;
the level conversion circuit is used for carrying out level conversion on the fourth signal to obtain a fifth signal, wherein the amplitude of the fifth signal is different from that of the fourth signal, but the fifth signal changes along with the fourth signal in phase.
6. The system according to any one of claims 1 to 5, further comprising a sampling filter circuit, the sampling filter circuit being located between the rectifier circuit and the reference voltage circuit;
the sampling filter circuit is used for filtering a third signal before sampling.
7. The system of claim 6, further comprising an anti-jitter circuit;
the jitter elimination circuit is used for obtaining a plurality of positive pulse signals according to the rising edge and the falling edge of the fourth signal, enabling the sixth signal to be equal to the fourth signal after the first positive pulse signal is obtained, and enabling the sixth signal to be kept unchanged in a later preset time so as to eliminate the influence of jitter in the fourth signal on the sixth signal.
8. A signal conditioning method applied to a non-polar dual bus is characterized in that the signal conditioning method is applied to the signal conditioning system of any one of claims 1 to 7, and comprises the following steps:
rectifying the first signal and the second signal through a rectifying circuit to obtain a third signal, wherein the level of the third signal is equal to the absolute value of the level difference value of the first signal and the second signal;
sampling a third signal through a reference voltage circuit to obtain a high-level signal of the third signal, and obtaining a reference voltage signal according to the high-level signal, wherein the reference voltage signal is equal to the average value of the high-level signal and a low-level signal of the third signal;
and comparing the third signal with the reference voltage signal through a comparator to obtain a fourth signal, wherein the fourth signal is a digital signal and changes along with the change of the third signal.
9. The method of claim 8, wherein sampling the third signal by a reference voltage circuit to obtain a high level signal of the third signal, and wherein obtaining the reference voltage signal according to the high level signal comprises:
sampling a high-level signal in the third signal through a sampling unit;
obtaining a low level signal of the third signal according to the high level signal through a first processing unit, and obtaining a first reference current and a second reference current according to the low level signal;
and obtaining a reference voltage signal according to the high level signal, the first reference current and the second reference current through a second processing unit.
10. The method of claim 8, wherein before sampling the third signal by the reference voltage circuit to obtain the high level signal of the third signal, further comprising:
and the level of a third signal output by the rectifying circuit is reduced to k times through a voltage division circuit, wherein k is more than 0 and less than 1.
11. The method of claim 8, wherein obtaining the fourth signal further comprises:
and performing level conversion on the fourth signal through a level conversion circuit to obtain a fifth signal, wherein the amplitude of the fifth signal is different from that of the fourth signal, but the fifth signal changes in phase with the fourth signal.
12. The method of any of claims 8-11, further comprising, prior to sampling the third signal:
filtering the third signal.
13. The method of claim 12, wherein obtaining the fourth signal further comprises:
obtaining a plurality of positive pulse signals according to the rising edge and the falling edge of the fourth signal;
and after the first positive pulse signal is obtained, making the sixth signal equal to the fourth signal, and keeping the sixth signal unchanged in a later preset time so as to eliminate the influence of jitter in the fourth signal on the sixth signal.
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