CN112363875A - System defect detection method, device, electronic device and storage medium - Google Patents
System defect detection method, device, electronic device and storage medium Download PDFInfo
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Abstract
The embodiment of the invention discloses a system defect detection method, system defect detection equipment, electronic equipment and a storage medium, relates to the technical field of system verification, and can improve the verification accuracy. The method comprises the following steps: initiating a response test to the test instruction via the data path, wherein the actual response of the test instruction is associated with the processing of the test instruction by the data path; acquiring an expected response result and an actual response test result of the test instruction; and comparing the expected response result of the test instruction with the actual response test result to obtain a system defect detection result. The invention is suitable for detecting defects in a verification system.
Description
Technical Field
The present invention relates to system verification technologies, and in particular, to a method, device, electronic device, and storage medium for detecting system defects.
Background
With the development of integrated circuits and the innovation of advanced processes, the design of chips becomes more and more complex, and the integration level becomes higher and higher, which creates a huge challenge for the verification of System-on-Chip (SOC). In the SOC chip, the CPU is the core of the whole logic operation and control, and whether it is correct or not relates to whether the whole chip can work normally or not. In current server chip design, a south bridge chipset and a north bridge chipset have been integrated with a CPU to form a single SOC chip. The SOC includes a CPU, a control bus, a data bus, a DRAM (Dynamic Random Access Memory) controller, a south bridge, a north bridge, and a peripheral input/output interface. In order to ensure the normal operation of the chip, the correctness of data access and control access of the CPU to other modules in the SOC needs to be verified.
In the prior art, register access and DRAM data access of other modules by a CPU are generally involved, and a 4-core CPU is shown in FIG. 1 as data access of a DRAM. In order to test the correctness of data access, the common method is that a CPU performs read-write operation on the same address, the read-write operation is performed first, and then the read-write operation is performed, and whether the test is successful or not is judged by comparing whether the write data and the read-back data are consistent or not. The specific process is as follows:
firstly, a CPU sends out a memory write instruction, the operation address is A0, the instruction is converted into an SDP packet after being processed by the CPU and sent to a data bus, the operation address is decoded on the data bus, the destination is found to be DRAM, then a series of routing, arbitration and the like are carried out, the SDP packet reaches a DRAM controller, the SDP packet is analyzed by the DRAM controller, the write operation is found, and the operation address and the data are extracted after the transmission of the SDP packet is judged to be correct; because a plurality of Memory blocks are mounted outside the DRAM controller, the operation address needs to be further decoded, a Memory block address, a channel address and the like corresponding to the address a0 are found, and finally, data are written into the address a0 of the DRAM 3;
after the write operation is completed, the CPU initiates a memory read instruction with an operation address of A0, the instruction is converted into an SDP packet by the CPU, enters a data bus, and reaches the DRAM controller after decoding, routing, arbitration and the like; the DRAM controller analyzes the SDP packet, reads the SDP packet, extracts an operation address after judging that the SDP packet is transmitted without errors, further decodes the operation address, and finds a Memory block address, a channel address and the like corresponding to A0; the DRAM controller reads data stored in an external A0 address, combines the data into an SDP response packet, sends the SDP response packet to a data bus, and returns to the CPU after routing and arbitration;
after the CPU obtains the read-back data, the read-back data and the previous write data are compared to judge whether the read-back data is consistent with the previous write data, if the read-back data is consistent with the previous write data, the read-back data is correct, and if the read-back data is inconsistent with the previous write data, the read-back data is wrong.
In the research process, the skilled person finds that the existing test scheme has test risks, and can miss serious design defects bug. Specifically, as shown in fig. 1, when the CPU wants to access the address a0, but the system has a design error, the address a0 is decoded as a1, so: for a write command, the data is routed to finally be written to address a 1; similarly, for the read command, the operation address sent from the CPU is a0, and after passing through the data bus, the operation address is decoded into a1, and finally the content stored in the address a1 in the external DRAM is read back. The CPU judges that the read-write data is correct, but the design bug is missed.
Disclosure of Invention
In view of this, embodiments of the present invention provide a method, an apparatus, an electronic apparatus, and a storage medium for detecting system defects, so as to solve the problem of inaccurate system defect detection in the prior art.
In a first aspect, an embodiment of the present invention provides a system defect detection method, including:
initiating a response test to the test instruction via the data path, wherein the actual response of the test instruction is associated with the processing of the test instruction by the data path;
acquiring an expected response result and an actual response test result of the test instruction;
and comparing the expected response result of the test instruction with the actual response test result to obtain a system defect detection result.
According to a specific implementation manner of the embodiment of the invention, the response test to the test instruction is initiated through the data path, and the response test comprises the following steps:
the first device sends out a test instruction, and after an operation object and an operation action of the test instruction are analyzed through the data path, the analyzed operation object is instructed to execute the operation action.
According to a specific implementation manner of the embodiment of the present invention, the method further includes: the first device generates operation object information and operation result information of the test instruction and sends the generated information to the second device through the data path;
obtaining an expected response result and an actual response test result of the test instruction, including:
the second device takes the operation result information sent by the first device as an expected response result;
and the second device acquires the operation result from the corresponding operation object according to the operation object information sent by the first device as an actual response test result.
According to a specific implementation of the embodiment of the invention, after determining that the actual response of the test instruction is completed, the first device sends the generated information to the second device via the data path.
According to a specific implementation manner of the embodiment of the invention, the first device comprises a CPU; the second device comprises a custom detection module and a custom storage module;
the first device generates operation object information and operation result information of a test instruction, and transmits the generated information to the second device via a data path, including: the CPU generates data carrying the operation object information and the operation result information of the test instruction according to a preset data format, and writes the data into a custom memory module through a data path;
obtaining an expected response result and an actual response test result of the test instruction, including:
the user-defined detection module reads the storage content of the user-defined storage module;
the user-defined detection module takes the operation result information sent by the CPU and stored in the user-defined storage module as an expected response result;
and the custom detection module acquires an operation result from the corresponding operation object according to the operation object information sent by the CPU stored in the custom storage module, and the operation result is used as an actual response test result.
According to a specific implementation manner of the embodiment of the invention, the reading of the custom storage module by the custom detection module comprises the following steps:
and after monitoring that new information from the CPU is written into the custom memory module, the custom detection module reads the newly written memory content of the custom memory module.
According to a specific implementation manner of the embodiment of the invention, the preset data format is the width of the bit number of the CPU processor.
According to a specific implementation manner of the embodiment of the present invention, the operation object of the test instruction includes a memory or a register, and the operation action includes reading data or writing data.
According to a specific implementation manner of the embodiment of the present invention, the preset data format includes:
data length and data type flag information of read or write;
address type flag information of a memory or a register;
reserving a field;
the address of the memory or register, and the data being read or written.
According to a specific implementation manner of the embodiment of the present invention, comparing an expected response result of a test instruction with an actual response test result to obtain a system defect detection result includes:
and the custom detection module compares the expected response result of the test instruction with the actual response test result to obtain a system defect detection result.
According to a specific implementation manner of the embodiment of the present invention, the method further includes:
and after the expected response result of the comparison test instruction is inconsistent with the actual response test result, printing output information indicating that the system has defects.
In a second aspect, an embodiment of the present invention provides a system defect detecting apparatus, including:
a test initiation unit for initiating a response test to the test instruction via the data path, wherein the actual response of the test instruction is associated with the processing of the test instruction by the data path;
the result acquiring unit is used for acquiring an expected response result and an actual response test result of the test instruction;
and the comparison unit is used for comparing the expected response result of the test instruction with the actual response test result to obtain a system defect detection result.
According to a specific implementation manner of the embodiment of the present invention, a test initiation unit is configured to initiate a response test to a test instruction via a data path, and includes:
and sending a test instruction, analyzing an operation object and an operation action of the test instruction through the data path, and indicating the analyzed operation object to execute the operation action.
According to a specific implementation manner of the embodiment of the present invention, the apparatus further includes: the information sending unit is used for generating operation object information and operation result information of the test instruction and sending the generated information to the result acquiring unit through the data path;
the result acquiring unit is used for acquiring an expected response result and an actual response test result of the test instruction, and comprises the following steps:
taking the operation result information sent by the information sending unit as an expected response result;
and acquiring an operation result from the corresponding operation object according to the operation object information sent by the information sending unit as an actual response test result.
According to a specific implementation manner of the embodiment of the invention, after the actual response of the test instruction is determined to be completed, the information sending unit sends the generated information to the result acquiring unit through the data path.
According to a specific implementation manner of the embodiment of the present invention, an information sending unit, configured to generate operation object information and operation result information of a test instruction, and send the generated information to a result obtaining unit through a data path, includes: generating data carrying the operation object information and the operation result information of the test instruction according to a preset data format, and writing the data into a custom memory module through a data path;
the result acquiring unit is used for acquiring an expected response result and an actual response test result of the test instruction, and comprises the following steps: reading the storage content of the custom storage module; taking operation result information sent by the CPU and stored in the custom memory module as an expected response result; and acquiring an operation result from the corresponding operation object according to the operation object information sent by the CPU stored in the custom memory module, and taking the operation result as an actual response test result.
According to a specific implementation manner of the embodiment of the present invention, the result obtaining unit is configured to read a custom memory module, and includes:
and after monitoring that new information from the CPU is written into the custom memory module, reading the newly written memory content of the custom memory module.
According to a specific implementation manner of the embodiment of the present invention, the apparatus further includes:
and the printing unit is used for printing output information indicating that the system has defects after the comparison unit compares the expected response result of the test instruction with the actual response test result to be inconsistent.
In a third aspect, an embodiment of the present invention provides an electronic device, where the electronic device includes: the device comprises a shell, a processor, a memory, a circuit board and a power circuit, wherein the circuit board is arranged in a space enclosed by the shell, and the processor and the memory are arranged on the circuit board; a power supply circuit for supplying power to each circuit or device of the electronic apparatus; the memory is used for storing executable program codes; the processor executes the program corresponding to the executable program code by reading the executable program code stored in the memory, and is used for executing the method of any one of the foregoing implementation modes.
In a fourth aspect, embodiments of the present invention also provide a computer-readable storage medium storing one or more programs, the one or more programs being executable by one or more processors to implement a method as in any one of the preceding implementations.
According to the system defect detection method, the device, the electronic device and the storage medium provided by the embodiment of the invention, after the response test of one test instruction is initiated through the data path, the secondary response of the other corresponding test instruction is not initiated again, but the expected response result of the test instruction is directly obtained to be compared with the actual response test result, and the obtained result is not influenced by the data path and a response object, so that the real working operation condition of the system can be analyzed according to the compared result, the defects existing in the system design can be detected, and the detection accuracy is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic diagram of the general design of a data path defect detection method when a CPU accesses a DRAM in the prior art;
FIG. 2 is a schematic flow chart illustrating a system defect detection method according to an embodiment of the present invention;
FIG. 3 is a schematic diagram illustrating an overall design of a data path defect detection method when a CPU accesses a DRAM according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a data format for writing a Special Memory by a CPU in a specific example according to an embodiment of the present invention;
FIG. 5 is a flowchart illustrating a method for detecting a defect in a data path when a CPU accesses a DRAM according to an embodiment of the present invention;
FIG. 6 is a schematic structural diagram of a system defect detecting apparatus according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of an embodiment of an electronic device according to the present invention.
Detailed Description
Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
It should be understood that the described embodiments are only some embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
For the sake of understanding, first, technical terms related to the embodiments of the present invention will be briefly described.
A CPU: central Processing Unit, Central processor, and operation and control core of computer system.
SOC: System-on-Chip, System-on-a-Chip.
DRAM: dynamic random access Memory (dram), bit0 and bit1 are represented by how much charge is stored by a capacitor.
DUT: design Under Test, Design to be tested, verifying the part of the environment to be tested.
UVM: the Universal Verification Methodology is a Verification development platform framework based on SystemVerilog.
SDP: scalatable Data Port, extensible Data Port, CPU system Data bus transmission protocol.
The technical scheme provided by the embodiment of the invention is described in detail below.
The embodiment of the invention provides a system defect detection method, which is applicable to a design verification scene of a system and is typically applied to the correctness verification of data access or control access of a CPU (central processing unit) to other modules in an SOC (system on chip). Referring to fig. 2, the method specifically includes the following steps 201-203.
In this step, the first device may obtain a test instruction and send the test instruction, where the test instruction is processed by the data path and then sent to the corresponding other device by the data path for response test. The first device may be a dedicated test device externally connected to or embedded in the system, or may be an existing device (e.g., CPU) in the system. The test instruction can be a pre-generated instruction specially used for testing the device under test, or can be an instruction generated by directly multiplexing the system operation process to the device under test. The processing of the test instructions by the datapath includes parsing the test instructions. Illustratively, the data path obtains an operation object corresponding to the test instruction by analyzing the test instruction, and then routes the test instruction to the analyzed operation object for response testing. Whether the analysis result of the test instruction by the data path is correct or not determines whether the test instruction can be correctly responded, and if the analysis of the operation object is wrong, a wrong response test result is generated.
In this step, the expected response result of the test instruction is a response result that the correct operation object should obtain after the test instruction correctly responds, that is, an expected result, which may be stored in the system in advance. The actual response test result of the test instruction is a result actually generated by a correct operation object after the test instruction response test is completed, and the obtaining mode is not obtained in a mode of initiating and responding the instruction any more, and can be obtained by directly accessing the correct operation object by the first device or an additionally arranged second device without a data path.
And step 203, comparing the expected response result of the test instruction with the actual response test result to obtain a system defect detection result.
In particular, if the expected response result of the test instruction and the actual response test result are not consistent, it may be determined that the system has a design defect. Typically, a problem with a data path in a system is detected by ensuring that the design other than the data path is correct during the detection process.
In an exemplary embodiment, in the step 201, initiating a response test to the test instruction via the data path includes: the first device sends out a test instruction, and after an operation object and an operation action of the test instruction are analyzed through the data path, the analyzed operation object is instructed to execute the operation action. The specific analysis process of the data path on the test instruction is the prior art, and is not described herein again.
In an exemplary embodiment, the system defect detecting method further includes: the first device generates operation object information and operation result information of the test instruction, and transmits the generated information to the second device via the data path. And the operation object information and the operation result information of the test instruction are correct information corresponding to the operation object and the operation result. The data path in the exemplary embodiment merely forwards the operand information and the operation result information of the test instruction to the second device, and the forwarding process does not involve the parsing of the instruction and the operand information and the operation result information, and belongs to the simple transmission of information. Accordingly, obtaining the expected response result and the actual response test result of the test instruction comprises:
the second device takes the operation result information sent by the first device as an expected response result;
and the second device acquires the operation result from the corresponding operation object according to the operation object information sent by the first device as an actual response test result.
It can be seen that the actual response test result is the actual operation result of the correct operation object. If the data path design has defects, the correct operation object corresponding to the test instruction is analyzed into other operation objects, which will cause the other operation objects to execute the correct operation action corresponding to the test instruction, and the correct operation object does not execute the correct operation action corresponding to the test instruction all the time in the test, and the operation result is necessarily different from the expected response result.
Preferably, after determining that the actual response of the test instruction is complete, the first device sends the generated information to the second device via the data path. Wherein, determining that the actual response of the test instruction is completed may be: and determining that the test instruction is processed by the data path and is sent to the corresponding other device by the data path, and the other device responds to the completion of the test. The determination process can be realized by adopting the existing any instruction response test completion monitoring technology.
In an exemplary embodiment, the first device includes a CPU; the second device comprises a custom detection module and a custom storage module. The first device generates operation object information and operation result information of a test instruction, and transmits the generated information to the second device via a data path, including: the CPU generates data carrying the operation object information and the operation result information of the test instruction according to a preset data format, and writes the data into the custom memory module through the data path.
Accordingly, obtaining the expected response result and the actual response test result of the test instruction comprises:
the user-defined detection module reads the storage content of the user-defined storage module;
the user-defined detection module takes the operation result information sent by the CPU and stored in the user-defined storage module as an expected response result;
and the custom detection module acquires an operation result from the corresponding operation object according to the operation object information sent by the CPU stored in the custom storage module, and the operation result is used as an actual response test result.
The test instruction may be a read instruction or a write instruction, the operation object includes a memory, a register, or another module (e.g., an encryption/decryption module) controlled by a CPU in the system, and the operation action includes reading data or writing data. Correspondingly, the operation object information of the test instruction is the operation address, and the operation result information is the correct data that should be read from or written into the operation address. Typically, the operating address may be a memory address or a register address, but may also be an access address of other modules controlled by the CPU in the system. Obtaining an operation result from a corresponding operation object according to the operation object information sent by the CPU stored in the user-defined storage module, wherein the operation result comprises the following steps: and accessing the operation address to read actually stored data according to the operation address sent by the CPU and stored in the custom memory module.
Preferably, the user-defined storage module is read by the user-defined detection module, and the method includes: and after monitoring that new information from the CPU is written into the custom memory module, the custom detection module reads the newly written memory content of the custom memory module.
Preferably, to maximize the utilization of the CPU and data bus bandwidth, the predetermined data format is the width of the CPU processor bit number. The preset data format comprises the following steps:
data length and data type flag information of read or write;
address type flag information of a memory or a register;
reserving a field;
the address of the memory or register, and the data being read or written.
In an exemplary embodiment, comparing the expected response result of the test instruction with the actual response test result to obtain the system defect detection result comprises: and the custom detection module compares the expected response result of the test instruction with the actual response test result to obtain a system defect detection result.
On the basis of any of the above schemes, the system defect detection method provided by the embodiment of the invention further comprises the following steps: and after the expected response result of the comparison test instruction is inconsistent with the actual response test result, printing output information indicating that the system has defects. The specific printing process may include: and converting an output character string indicating that the system has defects into an ASCII code data stream, writing the ASCII code data stream into an external storage device of the system through a memory, and reversely decoding the received data stream into the character string in the external storage device.
The system defect detection method provided by the embodiment of the invention adopts direct acquisition instead of multiple times of command initiation and response to acquire an expected response result and compare the expected response result with an actual response test result, and can analyze the real working operation condition of the system according to the comparison result, thereby detecting the defects existing in the system design, improving the detection accuracy and greatly reducing the command processing overhead. In addition, independently of the first device, the second device is independently deployed for data comparison and defect detection, and the processing pressure of the first device can be well relieved.
The following describes the technical solution of the embodiment of the method in detail by using a specific example. The application scenario of this specific example is to verify the correctness of data access of the CPU to the DRAM in the SOC, and in particular, to detect whether the data path is correct or not when the CPU accesses the DRAM without errors in other system designs.
First, some basic knowledge of the verification environment of this particular example is introduced. The verification environment of the specific example is built based on a framework of UVM, and the test case testcase includes two parts: one part is the testcase of UVM, which accomplishes the configuration of the DUT and the control of the simulation process; the other part is the testcase of the CPU, which is a test program written by using C/ASM language, is compiled into a binary code and then is stored in the bootcode, the bootcode is started after the DUT finishes configuration, the binary code is loaded to the CPU for execution, and the testcase of the CPU finishes functional verification to achieve the test purpose.
Fig. 3 shows a complete technical solution of this specific example, where a dashed box is a DUT part, including: CPU module, Data Bus Fabric, DRAM controller module. The CPU test program is testcase written in C/ASM language and runs on CPU core (CPU kernel). The test of the CPU test program to the external DRAM includes reading data, writing data, etc., where the data includes non-aligned data or encrypted data. Specifically, the CPU initiates a response test of the read/write DRAM command through the data path until the DRAM is read/written, the data flow is as shown by a black solid line, and the detailed process is as follows: the read/write command is sent by a CPU core, is converted into an SDP format data packet after being processed and is sent to a data bus, the data bus is provided with an arbitration module, a decoding module and a routing module, the SDP format data packet is decoded and then is routed to a DRAM controller, and after the DRAM controller judges that the SDP format data packet is correct, the carried data is written into a corresponding address of an external DRAM if the SDP format data packet is a write command, and the data of the corresponding address is read back from the external DRAM if the SDP format data packet is a read command.
The prior art reads back data stored at previously written addresses after performing an external DRAM access in a test program, and compares whether the data is consistent. After the improvement of this specific example, this procedure is removed, and instead, the address and data to be compared are written into an external independent Memory space, called Special Memory space, in the test program, where the address and data to be compared correspond to the operation object information and the operation result information of the CPU, and the Special Memory space corresponds to the custom Memory module in the foregoing embodiment. The Special Memory is an exclusive space allocated before the test program runs and is not accessed by other programs. In the UVM verification environment, a ticket module based on systemveilog is developed, which corresponds to the custom detection module in the foregoing embodiment. The Checker module starts to operate after the CPU test program is started, whether the content stored in the Special Memory is modified or not is monitored, if the content stored in the Special Memory is modified, the Checker module reads back the content stored in the Special Memory, analyzes an address and data, then reads the content stored in the position corresponding to the analyzed address in the external DRAM, and compares the content with the data read from the Special Memory. If the data are the same, the test program and the DUT have no errors; and if the data is different, printing error information and ending the simulation process.
When the CPU writes the address and data to be compared into the Special Memory, the written data format is as shown in fig. 4, and the data format is designed to be 64-bit wide in order to maximize the utilization of the CPU and the data bus bandwidth. Because the CPU is a 64-bit processor, 1 data can be written in each instruction cycle, and the instruction overhead can be effectively reduced.
The information for each field is shown in table 1.
TABLE 1 CPU write Special Memory data Format
The flow chart is shown in fig. 5, and the CPU executive program and the Checker module executive program in the test program run independently.
The CPU executes the program flow chart shown in fig. 5 (left), after the program starts, the CPU initiates a response test for reading/writing the DRAM, and after the DRAM is actually read/written, writes the DRAM address expected to be operated by the CPU in the response test this time and the data expected to be read or written in the address into the Special Memory according to the data format shown in fig. 4. After the Special Memory is written, whether the program is finished or not is judged, if not, the response test of the DRAM is continuously initiated and the data writing of the Special Memory is carried out.
The execution flow of the Checker module is as shown in fig. 5 (right), after the program starts, whether new CPU data is written into the Special Memory is monitored, and if so, the newly written Special Memory storage content is read out. And the Checker module analyzes the read content to obtain an expected address and data, reads the data actually stored by the address from the external DRAM, and updates the completion bit in the Special Memory to indicate that the Checker module has been read. Comparing expected data obtained from the Special Memory with actually stored data read from the external DRAM, and if the expected data is consistent with the actually stored data read from the external DRAM, continuing to monitor the new data writing condition; if not, printing error information and ending the simulation.
This particular example provides a complete testing process, in which: on the one hand, after adding the Checker module, a complete end-to-end detection is formed, and the risk of missing a bug in the prior art can be eliminated, for example, if a bug on the data bus decodes address a0 into a1, the CPU issues an instruction to write data to address a0, but the data is finally written to address a1 because of the presence of the bug. By adopting the prior art test, after the CPU sends an instruction for reading the A0 address, the CPU reads back the data stored in the address A1, so the comparison can be passed, but the bug is missed; with the improved method test of this example, the expected address of the CPU writing the Special Memory is A0, so the Checker module will read back the data from the external DRAM A0 address, and find out the inconsistency with the expected data once comparing, thus finding out the bug; on the other hand, in this example, detection codes in a CPU execution program are removed, and instead, the UVM Checker module executes detection, so that the number of executed CPU instructions can be reduced, and the simulation efficiency can be improved, because the access of the Checker module to the Special Memory or the DRAM is in the UVM verification environment, and there is no operation on the DUT, so that the CPU simulation time is not consumed.
Further, with regard to the above example, the following points need to be additionally explained:
the example is not limited to the CPU system of x86 architecture, but can also be applied to ARM, MIPS, RISC-V, etc.;
the example is not limited to single-core CPU system verification, and can also be applied to multi-core CPU and multi-Die CPU system verification;
the example is not limited to CPU control path verification, and the control path can be expanded to read and write check of the register;
the addition of an encryption/decryption module to the verification environment may be extended to the verification of the encryption/decryption logic.
Fig. 6 is a schematic structural diagram of a system defect detecting apparatus according to an embodiment of the present invention, and as shown in fig. 6, the system defect detecting apparatus according to the embodiment may include:
a test initiating unit 601 for initiating a response test to the test instruction via the data path, wherein an actual response of the test instruction is associated with the processing of the test instruction by the data path;
a result obtaining unit 602, configured to obtain an expected response result of the test instruction and an actual response test result;
the comparing unit 603 is configured to compare the expected response result of the test command with the actual response test result to obtain a system defect detection result.
In an exemplary embodiment, the test initiation unit 601, configured to initiate a response test to the test instruction via the data path, includes:
and sending a test instruction, analyzing an operation object and an operation action of the test instruction through the data path, and indicating the analyzed operation object to execute the operation action.
In an exemplary embodiment, the apparatus further comprises: an information sending unit 600, configured to generate operation object information and operation result information of the test instruction, and send the generated information to the result obtaining unit through the data path;
a result obtaining unit 602, configured to obtain an expected response result of the test instruction and an actual response test result, including:
the operation result information sent by the information sending unit 600 is used as an expected response result;
the operation result is acquired from the corresponding operation object as an actual response test result according to the operation object information transmitted by the information transmitting unit 600.
In an exemplary embodiment, after determining that the actual response of the test instruction is completed, the information sending unit 600 sends the generated information to the result obtaining unit 602 via the data path.
In an exemplary embodiment, the information sending unit 600 is configured to generate operation target information and operation result information of a test instruction, and send the generated information to the result obtaining unit via a data path, and includes: generating data carrying the operation object information and the operation result information of the test instruction according to a preset data format, and writing the data into a custom memory module through a data path;
a result obtaining unit 602, configured to obtain an expected response result of the test instruction and an actual response test result, including: reading the storage content of the custom storage module; taking operation result information sent by the CPU and stored in the custom memory module as an expected response result; and acquiring an operation result from the corresponding operation object according to the operation object information sent by the CPU stored in the custom memory module, and taking the operation result as an actual response test result.
In an exemplary embodiment, the result obtaining unit 602 is configured to read a custom memory module, and includes:
and after monitoring that new information from the CPU is written into the custom memory module, reading the newly written memory content of the custom memory module.
In an exemplary embodiment, the apparatus further comprises:
and a printing unit 604, configured to print output information indicating that the system has a defect after the comparison unit 603 compares the expected response result of the test instruction with the actual response test result, wherein the expected response result and the actual response test result are inconsistent.
The system defect detection device provided by the embodiment of the present invention may be used to implement the technical solution of any method embodiment of the present invention, and the implementation principle and technical effect are similar, which are not described herein again.
The embodiment of the invention also provides electronic equipment, which comprises the system defect detection equipment in any one of the embodiments.
Fig. 7 is a schematic structural diagram of an embodiment of an electronic device of the present invention, which can implement the process of the embodiment shown in fig. 2 of the present invention, and as shown in fig. 7, the electronic device may include: the device comprises a shell 71, a processor 72, a memory 73, a circuit board 74 and a power circuit 75, wherein the circuit board 74 is arranged inside a space enclosed by the shell 71, and the processor 72 and the memory 73 are arranged on the circuit board 74; a power supply circuit 75 for supplying power to each circuit or device of the electronic apparatus; the memory 73 is used to store executable program code; the processor 72 executes a program corresponding to the executable program code by reading the executable program code stored in the memory 73, so as to execute the system defect detecting method according to any of the foregoing embodiments.
The specific execution process of the above steps by the processor 72 and the steps further executed by the processor 72 by running the executable program code may refer to the description of the embodiment shown in fig. 2 of the present invention, and are not described herein again.
The electronic device exists in a variety of forms, including but not limited to:
(1) a mobile communication device: such devices are characterized by mobile communications capabilities and are primarily targeted at providing voice, data communications. Such terminals include: smart phones (e.g., iphones), multimedia phones, functional phones, and low-end phones, among others.
(2) Ultra mobile personal computer device: the equipment belongs to the category of personal computers, has calculation and processing functions and generally has the characteristic of mobile internet access. Such terminals include: PDA, MID, and UMPC devices, etc., such as ipads.
(3) A portable entertainment device: such devices can display and play multimedia content. This type of device comprises: audio, video players (e.g., ipods), handheld game consoles, electronic books, and smart toys and portable car navigation devices.
(4) A server: the device for providing the computing service comprises a processor, a hard disk, a memory, a system bus and the like, and the server is similar to a general computer architecture, but has higher requirements on processing capacity, stability, reliability, safety, expandability, manageability and the like because of the need of providing high-reliability service.
(5) And other electronic equipment with data interaction function.
Furthermore, embodiments of the present invention also provide a computer-readable storage medium storing one or more programs, which are executable by one or more processors to implement the method provided by any of the embodiments of the present invention.
It should be noted that, in this document, relational terms such as first and second, and the like are used only for description
One entity or operation is distinguished from another entity or operation by no means required or implied
There may be any such actual relationship or order between the entities or operations. Also, the terms "include", "bag" and the like
The terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. The term "comprising", without further limitation, means that the element so defined is not excluded from the group consisting of additional identical elements in the process, method, article, or apparatus that comprises the element.
All the embodiments in the present specification are described in a related manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment focuses on the differences from the other embodiments.
In particular, as for the apparatus embodiment, since it is substantially similar to the method embodiment, the description is relatively simple, and for the relevant points, reference may be made to the partial description of the method embodiment.
For convenience of description, the above devices are described separately in terms of functional division into various units/modules. Of course, the functionality of the units/modules may be implemented in one or more software and/or hardware implementations of the invention.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (20)
1. A method for system defect detection, the method comprising:
initiating a response test to the test instruction via the data path, wherein the actual response of the test instruction is associated with the processing of the test instruction by the data path;
acquiring an expected response result and an actual response test result of the test instruction;
and comparing the expected response result of the test instruction with the actual response test result to obtain a system defect detection result.
2. The system defect detection method of claim 1, wherein initiating a response test to the test instruction via the data path comprises:
the first device sends out a test instruction, and after an operation object and an operation action of the test instruction are analyzed through the data path, the analyzed operation object is instructed to execute the operation action.
3. The system defect detection method of claim 2, further comprising: the first device generates operation object information and operation result information of the test instruction and sends the generated information to the second device through the data path;
obtaining an expected response result and an actual response test result of the test instruction, including:
the second device takes the operation result information sent by the first device as an expected response result;
and the second device acquires the operation result from the corresponding operation object according to the operation object information sent by the first device as an actual response test result.
4. The system defect detection method of claim 3, wherein the first device sends the generated information to the second device via the data path after determining that the actual response of the test command is complete.
5. The system defect detection method of claim 3, wherein the first device comprises a CPU; the second device comprises a custom detection module and a custom storage module;
the first device generates operation object information and operation result information of a test instruction, and transmits the generated information to the second device via a data path, including: the CPU generates data carrying the operation object information and the operation result information of the test instruction according to a preset data format, and writes the data into a custom memory module through a data path;
obtaining an expected response result and an actual response test result of the test instruction, including:
the user-defined detection module reads the storage content of the user-defined storage module;
the user-defined detection module takes the operation result information sent by the CPU and stored in the user-defined storage module as an expected response result;
and the custom detection module acquires an operation result from the corresponding operation object according to the operation object information sent by the CPU stored in the custom storage module, and the operation result is used as an actual response test result.
6. The system defect detection method of claim 5, wherein the reading of the custom memory module by the custom detection module comprises:
and after monitoring that new information from the CPU is written into the custom memory module, the custom detection module reads the newly written memory content of the custom memory module.
7. The system defect detection method of claim 5, wherein the predetermined data format is a width of a CPU processor bit number.
8. The method of claim 5, wherein the operand of the test command comprises a memory or a register, and the operation action comprises reading data or writing data.
9. The system defect detection method of claim 8, wherein the predetermined data format comprises:
data length and data type flag information of read or write;
address type flag information of a memory or a register;
reserving a field;
the address of the memory or register, and the data being read or written.
10. The method of claim 5, wherein comparing the expected response result of the test command with the actual response test result to obtain the system defect detection result comprises:
and the custom detection module compares the expected response result of the test instruction with the actual response test result to obtain a system defect detection result.
11. The system defect detection method of any of claims 1-10, further comprising:
and after the expected response result of the comparison test instruction is inconsistent with the actual response test result, printing output information indicating that the system has defects.
12. A system defect detection apparatus, the apparatus comprising:
a test initiation unit for initiating a response test to the test instruction via the data path, wherein the actual response of the test instruction is associated with the processing of the test instruction by the data path;
the result acquiring unit is used for acquiring an expected response result and an actual response test result of the test instruction;
and the comparison unit is used for comparing the expected response result of the test instruction with the actual response test result to obtain a system defect detection result.
13. The system defect detection device of claim 12, wherein the test initiation unit is configured to initiate a response test to the test instruction via the data path, and comprises:
and sending a test instruction, analyzing an operation object and an operation action of the test instruction through the data path, and indicating the analyzed operation object to execute the operation action.
14. The system defect detection apparatus of claim 13, wherein the apparatus further comprises: the information sending unit is used for generating operation object information and operation result information of the test instruction and sending the generated information to the result acquiring unit through the data path;
the result acquiring unit is used for acquiring an expected response result and an actual response test result of the test instruction, and comprises the following steps:
taking the operation result information sent by the information sending unit as an expected response result;
and acquiring an operation result from the corresponding operation object according to the operation object information sent by the information sending unit as an actual response test result.
15. The system defect detection apparatus according to claim 14, wherein the information sending unit sends the generated information to the result acquisition unit via the data path after determining that the response of the test instruction is actually completed.
16. The system defect detecting apparatus according to claim 14,
the information sending unit is used for generating the operation object information and the operation result information of the test instruction and sending the generated information to the result acquiring unit through the data path, and comprises the following steps: generating data carrying the operation object information and the operation result information of the test instruction according to a preset data format, and writing the data into a custom memory module through a data path;
the result acquiring unit is used for acquiring an expected response result and an actual response test result of the test instruction, and comprises the following steps: reading the storage content of the custom storage module; taking operation result information sent by the CPU and stored in the custom memory module as an expected response result; and acquiring an operation result from the corresponding operation object according to the operation object information sent by the CPU stored in the custom memory module, and taking the operation result as an actual response test result.
17. The system defect detecting device of claim 16, wherein the result obtaining unit is configured to read the custom memory module, and comprises:
and after monitoring that new information from the CPU is written into the custom memory module, reading the newly written memory content of the custom memory module.
18. The system defect detection apparatus of any of claims 12-17, wherein the apparatus further comprises:
and the printing unit is used for printing output information indicating that the system has defects after the comparison unit compares the expected response result of the test instruction with the actual response test result to be inconsistent.
19. An electronic device, characterized in that the electronic device comprises: the device comprises a shell, a processor, a memory, a circuit board and a power circuit, wherein the circuit board is arranged in a space enclosed by the shell, and the processor and the memory are arranged on the circuit board; a power supply circuit for supplying power to each circuit or device of the electronic apparatus; the memory is used for storing executable program codes; the processor executes a program corresponding to the executable program code by reading the executable program code stored in the memory for performing the method of any of the preceding claims.
20. A computer readable storage medium, characterized in that the computer readable storage medium stores one or more programs which are executable by one or more processors to implement the method of any preceding claim.
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