CN112350731A - Adaptive phase alignment scheme for high speed DAC - Google Patents

Abstract

Methods and systems for implementing an adaptive phase alignment scheme for high-speed DACs are disclosed.

Description

Adaptive phase alignment scheme for high speed DAC

Technical Field

The present description relates generally to integrated circuits and in particular to adaptive phase alignment schemes for high speed digital-to-analog converters (DACs).

Background

For high-speed DACs, the phase alignment between the differential in-phase data (I), quadrature-phase data (Q), and the sampling clock significantly affects the timing margin of the DAC and the overall system performance, such as inter-symbol interference (ISI), signal-to-noise ratio (SNR), and significant bit number (ENOB) degradation. Robust data and clock phase alignment will help improve overall system performance.

Disclosure of Invention

In one aspect, the present application provides an adaptive phase control circuit, the circuit comprising: a pair of Phase Interpolators (PI) configured to adjust a phase of an input clock pulse; a Multiplexer (MUX) circuit configured to receive phase adjusted clocks from the PI and select one of the phase adjusted clocks; an adjustable delay unit configured to adjust a delay of a selected one of the phase-adjusted clocks based on a delay control signal and generate a delay-adjusted signal; a phase detector configured to detect a phase of the delay adjusted signal; and a Digital Signal Processor (DSP) configured to generate the delay control signal.

Drawings

Certain features of the inventive technique are set forth in the appended claims. However, for purposes of explanation, several embodiments of the present technology are set forth in the following figures.

Fig. 1 illustrates an example of an adaptive phase control scheme in accordance with one or more aspects of the present technique.

Fig. 2 illustrates an example of a single edge detection scheme in accordance with one or more aspects of the present technique.

Fig. 3 illustrates an example of data and clock signals for an adaptive phase alignment scheme in accordance with one or more aspects of the present technique.

Fig. 4 illustrates offset contributing factors in an example phase detector block in accordance with one or more aspects of the present technique.

Fig. 5 illustrates an example of an offset effect of a non-zero input reference offset in accordance with one or more aspects of the present technique.

Fig. 6 illustrates example DAC timing tolerances after calibration on different corners in accordance with one or more aspects of the present technique.

FIG. 7 shows example simulation results comparing a double edge detection scheme to a single edge detection scheme of the present technology.

Detailed Description

The detailed description set forth below is intended as a description of various configurations of the present technology and is not intended to represent the only configurations in which the present technology may be practiced. The accompanying drawings are incorporated herein and constitute a part of the detailed description. The detailed description includes specific details for the purpose of providing a thorough understanding of the present technology. However, the present techniques are not limited to the specific details set forth herein and may be practiced using one or more implementations. In one or more instances, structures and components are shown in block diagram form in order to avoid obscuring the concepts of the present technology.

The present technology is directed to methods and systems that include an adaptive phase control block to align delayed divided clocks, such as a differential in-phase clock (CK2TI _ delayed) and a quadrature phase clock (CK2TQ _ delayed), to a master clock (CK 1T). An adjustable delay unit, which can be adaptively varied by the phase interpolator and the DSP, is used to control the timing margin between the data and the clock. The phase block of the present technique includes two separate IQ phase interpolators, two dummy Multiplexers (MUXs), an IQ CK MUX, an adjustable delay unit, a phase detector, and a Digital Signal Processor (DSP). The output of the phase detector is sent to the DSP to control the phase interpolator and the adjustable delay unit. The present phase detector aligns a divided clock (e.g., in differential in-phase (CK2TI) and quadrature phase (CK2TQ) to the same edge of a master clock with a 180 degree phase shift (CK1T) and without a 180 degree phase shift (CKB _1T), wherein the skew variation of the divided clock is comparable to the master clock period.

The phase detector block includes CK1T/CKB _1T MUX, two Current Mode Logic (CML) samplers, a low-speed comparator, and a retimer. The output of the phase detector block is sent to the DSP to control the phase interpolator. The CK1T/CKB _1T MUX, controlled by the phase selection control bit, can be embedded in the first CML sampler with negligible power and speed penalty. The proposed technique achieves tight timing alignment for high speed and low power applications. Furthermore, the proposed technique is independent of any standard or process technique. It should be appreciated that any transceiver, such as an optical, cable, or wireless transceiver, will use a high-speed DAC and perform equalization, demodulation, and other signal processing in the digital domain for robustness. Future products that use high-speed DACs for low-power applications will benefit from the present technology.

An existing phase control loop aligns a delayed divided clock (e.g., in differential in-phase (CK2TI _ delay) and quadrature phase (CK2TQ _ delay) to a primary clock CK1T. an adjustable delay unit is used to control timing margin between data and clock. the phase delay control loop includes two separate IQ phase interpolators, two adjustable delay units, a phase detector, and a DSP. the outputs of the phase detector are sent to the DSP to control the phase interpolator. the delays of the adjustable delay units may be controlled by programmable capacitors, resistors, and current sources Low ratio comparator and retiming. The output of the phase detector is sent to the DSP to control the phase interpolator.

The present technique has several advantageous features compared to existing solutions. For example, the delay of the present technology is adaptively measured by the Phase Interpolator (PI) with negligible hardware overhead, since the PI is reused to check the value of the adjustable delay in the loop, and the disclosed solution is robust against process, voltage and temperature variations, even for high speed applications with tight timing margins. For the replica topology, the IQ paths share the same delay path, no mismatch is generated from the delay unit and the phase detector, and the introduced replica mismatch is small compared to before. The disclosed solution greatly simplifies the design of the phase detector because only one CK2T path is used, which translates to less design effort and chip area. Furthermore, in the single edge detection scheme of the present technique, the phase alignment is insensitive to input reference phase detector offsets, unlike previous double edge detection based on a zero crossing scheme. Also, the gain requirements of the CML sampler are greatly relaxed and the phase alignment is no longer sensitive to offsets generated by subsequent stages. Furthermore, the fact that only the offset from the phase MUX is important greatly simplifies the design and layout effort and enables better phase alignment at lower power consumption, even for higher speed applications.

Fig. 1 illustrates an example of an adaptive phase control scheme in accordance with one or more aspects of the present technique. As shown in FIG. 1, an adaptive phase control scheme aligns delayed divided clocks (e.g., in differential in-phase (CK _2TI _ delay) and quadrature phase (CK _2TQ _ delay) to a master clock CK _ 1T. an adjustable delay unit adaptively changed by the PI and DSP is used to control the timing margin between the data and clock.

Fig. 2 illustrates an example of a single edge detection scheme in accordance with one or more aspects of the present technique. In the single edge detection scheme shown in FIG. 2, the phase detector aligns the divided clock (e.g., in differential in-phase (CK _2TI) and quadrature phase (CK _2TQ) to the same edge of the master clock with and without 180 degree phase shift (CK _1T), with the skew variation of the divided clock being commensurate with the master clock period.

Fig. 3 illustrates an example of data and clock signals for an adaptive phase alignment scheme in accordance with one or more aspects of the present technique. For the data and clock signals shown in fig. 3, the delay is adaptively measured by the PI with negligible hardware overhead, since the PI is reused to check the value of the adjustable delay in the loop. The data is robust against process, voltage and temperature variations, even for high speed applications with tight timing margins. A replica topology as shown in fig. 1 is used and the IQ paths share the same delay path, without mismatch from the delay unit and the phase detector. The introduced copy mismatch is small compared to before. The design of the phase detector is greatly simplified because only one CK2T path is used, which results in less design effort and chip area.

Fig. 4 illustrates offset contributing factors in an example phase detector block in accordance with one or more aspects of the present technique. The phase detector block includes CK1T/CKB _1T MUX, two CML samplers, a low-speed comparator, and a retimer. The output of the phase detector block is sent to the DSP to control the phase interpolator. The CK1T/CKB _1T MUX, controlled by the phase selection control bit, can be embedded in the first CML sampler with negligible power and speed penalty.

Fig. 5 illustrates an example of an offset effect of a non-zero input reference Phase Detector (PD) offset in accordance with one or more aspects of the present technique. For a single edge detection scheme, fig. 5 indicates that the alignment is insensitive to input reference phase detector offsets, unlike existing double edge detection based on a zero-crossing scheme. The gain requirements of the CML sampler are greatly relaxed. The phase alignment is not sensitive to offsets resulting from subsequent stages. Only the offset from the phase MUX is important, which greatly simplifies the design and layout effort. Better phase alignment at lower power consumption is achieved even for higher speed applications.

Fig. 6 illustrates example DAC timing tolerances after calibration on different corners in accordance with one or more aspects of the present technique. The DAC timing margins of fig. 6 show that, for high speed applications, the left and right timing margins may encompass different corners after adaptively delay control calibration.

FIG. 7 shows example simulation results comparing a double edge detection scheme to a single edge detection scheme of the present technology. The simulation results shown in fig. 7 indicate that one sigma of CK2TI/Q mismatch is about 0.017UI for the single edge detection scheme of the present technique, in contrast to 0.12UI for the prior art solutions based on the double edge detection scheme. This shows a more than seven-fold improvement achieved by the single edge detection scheme of the present technology.

Although the discussion above primarily refers to a microprocessor or multi-core processor executing software, one or more implementations are performed by one or more integrated circuits, such as an Application Specific Integrated Circuit (ASIC) or Field Programmable Gate Array (FPGA). In one or more implementations, such integrated circuits execute instructions stored on the circuit itself.

Those of skill in the art will appreciate that the various illustrative blocks, modules, elements, components, methods, and algorithms described herein may be implemented as electronic hardware, computer software, or combinations of both. To illustrate this interchangeability of hardware and software, various illustrative blocks, modules, elements, components, methods, and algorithms have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application. The various components and blocks may be arranged differently (e.g., arranged in a different order, or divided in a different manner) without departing from the scope of the present technology.

It should be understood that any particular order or hierarchy of blocks in the disclosed processes is an illustration of an example methodology. Based upon design preferences, it is understood that the specific order or hierarchy of blocks in the processes may be rearranged and that all illustrated blocks are performed. Any of the blocks may be performed simultaneously. In one or more implementations, multitasking and parallel processing may be advantageous. Moreover, the separation of various system components in the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

As used in the description and any claims of this application, the terms "base station," "receiver," "computer," "server," "processor," and "memory" all refer to electronic or other technical devices. These terms exclude humans or groups of humans. For the purposes of this specification, the term "display" or "displaying" means displaying on an electronic device.

As used herein, the phrase "at least one of" (any of the terms "and" or "separate items) preceding a series of items modifies the list as a whole rather than each member of the list (i.e., each item). The phrase "at least one of" does not require the selection of at least one of each of the items listed; in practice, the phrase provides a meaning that includes at least one of the items and/or at least one of any combination of the items and/or at least one of each of the items. For example, the phrases "at least one of A, B and C" or "at least one of A, B or C" each refer to a alone, B alone, or C alone; A. any combination of B and C; and/or A, B and C.

The adjectives "configured to," "operable to," and "programmed to" do not imply any particular tangible or intangible modification of the subject matter, but are intended to be used interchangeably. In one or more implementations, a processor configured to monitor and control operations or components may also represent a processor programmed to monitor and control operations, or a processor operable to monitor and control operations. Likewise, a processor configured to execute code may be understood as a processor programmed to execute code or operable to execute code.

Phrases such as "aspect" do not imply that such aspect is essential to the present technology or that such aspect applies to all configurations of the present technology. The disclosure relating to an aspect may apply to all configurations, or one or more configurations. One aspect may provide one or more examples of the disclosure. Phrases such as "an aspect" may refer to one or more aspects and vice versa. Phrases such as "an embodiment" do not imply that such embodiment is essential to the present technology or that such embodiment applies to all configurations of the present technology. A disclosure relating to an embodiment may apply to all embodiments, or one or more embodiments. An embodiment may provide one or more examples of the present disclosure. A phrase such as "an embodiment" may refer to one or more embodiments and vice versa. A phrase such as a "configuration" does not imply that such configuration is essential to the present technology or that such configuration applies to all configurations of the present technology. The disclosure relating to a configuration may apply to all configurations, or one or more configurations. A configuration may provide one or more examples of the present disclosure. A phrase such as "configured" may refer to one or more configurations and vice versa.

The word "exemplary" is used herein to mean "serving as an example, instance, or illustration. Any embodiment described herein as "exemplary" or "example" is not necessarily to be construed as preferred or advantageous over other embodiments. Furthermore, to the extent that the terms "includes," "has," or similar terms are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term "comprising" as "comprising" is interpreted when employed as a transitional word in a claim.

All structural and functional equivalents to the elements of the various aspects described throughout this disclosure that are known or later come to be known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the appended claims. Moreover, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is explicitly recited in the claims. Claim elements should not be construed in accordance with the terms of 35u.s.c. § 112 sixth chapter, unless the element is explicitly recited using the phrase "means for.

The previous description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects. Thus, the claims are not intended to be limited to the aspects shown herein, but is to be accorded the full scope consistent with the language claims, wherein reference to an element in the singular is not intended to mean "one and only one" (unless explicitly so stated), but rather "one or more". The term "some" means one or more unless specifically stated otherwise. Pronouns for men (e.g., his) encompass women and neutral gender (e.g., her and it), and vice versa. Headings and sub-headings, if any, are used for convenience only and do not limit the disclosure.

Claims (6)

1. An adaptive phase control circuit, the circuit comprising:

a pair of phase interpolators PI configured to adjust the phase of the input clock pulses;

a multiplexer MUX circuit configured to receive phase adjusted clocks from the PI and select one of the phase adjusted clocks;

an adjustable delay unit configured to adjust a delay of a selected one of the phase-adjusted clocks based on a delay control signal and generate a delay-adjusted signal;

a phase detector configured to detect a phase of the delay adjusted signal; and

a Digital Signal Processor (DSP) configured to generate the delay control signal.

2. The circuit of claim 1, wherein the input clock pulses comprise in-phase I and quadrature-phase Q clocks.

3. The circuit of claim 2, further comprising two dummy MUX circuits configured to provide I-and Q-DAC signals based on phase adjusted I and Q clocks.

4. The circuit of claim 2, wherein the phase detector comprises a single-edge phase detector and includes a phase select MUX, two CML samplers, a low-speed comparator, and a retimer.

5. The circuit of claim 4, wherein the phase select MUX is controlled by a phase select bit.

6. The circuit of claim 4, wherein the phase select MUX is embedded in one of the CML samplers.

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