CN112333070B

CN112333070B - Implementation method of MBUS master station in MBUS gateway

Info

Publication number: CN112333070B
Application number: CN202011227347.1A
Authority: CN
Inventors: 冯建明; 韩路
Original assignee: Jiangyin Lixin Intelligent Device Co ltd
Current assignee: Jiangyin Lixin Intelligent Device Co ltd
Priority date: 2020-11-06
Filing date: 2020-11-06
Publication date: 2022-03-15
Anticipated expiration: 2040-11-06
Also published as: CN112333070A

Abstract

The invention relates to a realization method of an MBUS master station in an MBUS gateway, which comprises a power supply isolation driving circuit, a data transmission conversion circuit, a data receiving and analyzing circuit and a waterproof joint, wherein a stabilized voltage power supply is adopted and isolated by a diode power supply and then used by a bus, a transmission channel is controlled by the high and low level of a processor port to control an optical coupling isolation device to realize the on-off driving of a PMOS (P-channel metal oxide semiconductor) tube so as to control the alternate generation of voltage, thereby realizing the generation of a modulated MBUS transmission instruction; after receiving the MBUS feedback signal, electrorheological voltage sampling is carried out through a small-resistance value sampling resistor, the sampling signal is associated with the power supply voltage of the processor, signal conditioning is carried out through a plurality of analog operational amplifiers, high and low level signals suitable for the port level of the processor are obtained, and the processor analyzes data according to the level change. The invention has the characteristics of high cost-performance ratio, high universality and high anti-interference performance, can be applied to special environments such as underwater and the like through the waterproof joint, and expands the installation position limitation of the MBUS master station and the MBUS slave station.

Description

Implementation method of MBUS master station in MBUS gateway

Technical Field

The invention relates to a realization method of an MBUS master station in an MBUS gateway, which is suitable for gateways of meters such as water meters, gas meters, electric meters and the like of MBUS communication. Belong to intelligent water gauge technical field.

Background

The MBUS (Meter bus) is an instrument bus, is generated at the beginning to meet the requirement of remote meter reading of a utility, is mainly characterized in that two non-polar transmission lines are used for supplying power and transmitting serial data, and is mainly applied to measuring consumption of gas and water in a home. MBUS is a bus for realizing data transmission by voltage modulation, and is divided into 1 master station and a plurality of slave stations, wherein the master station and the slave stations are hung on the bus in a two-wire system parallel connection mode, each slave station transmits collected instrument related data or signals to the master station, common twisted-pair wires can be adopted for connection according to any bus topological structure, the transmission distance is long, the speed is high, the wiring is convenient and simple, and the protocol is flexible and autonomous. The MBUS is a master-slave system, with communication controlled by a master station. The MBUS consists of a master station, a plurality of slave stations and a double-wire connecting cable, wherein the slave stations are connected in parallel on the connecting cable, and the bus can only carry out half-duplex communication. The current consumed by each slave station is constant except for the data state being transmitted.

And the data transmission from the master station to the slave station is realized in a voltage modulation mode. Logic 1(MBUS bus defined as MARK), corresponding to a standard voltage of 36V output on the bus; logic 0(MBUS bus is defined as SPACE), and the output voltage on the bus is 12V lower than MARK voltage, namely the standard voltage of 24V. The master station modulates the bus voltage according to the data content and outputs the modulated bus voltage to the bus through the driver. Data transmission from the slave to the master is encoded by modulating the current consumption of the slave. Logic 1(MARK) is the fixed consumption current of the slave station, and logic 0(SPACE) adds 11-20mA of current on the bus. The data transmission from the master station to the slave station has 12V voltage change, and the data transmission from the slave station to the master station has at least 11mA current change, so that the MBUS bus not only can supply power to the slave station by the master station, but also has strong anti-interference capability.

The master station can be a computer, a portable device or other devices, because the MBUS is in a half-duplex mode, the master station needs to send protocol commands, and the slave station feeds back the protocol commands according to the command content, the design of the master station becomes particularly important, and in some special use environments, the problem of sealing a data connector with the slave station also needs to be paid enough attention, and after all, the MBUS is used for transmitting data in a power modulation mode. There are already dedicated ICs on the meter (slave side), such as TSS721A, etc., but since several hundred slave stations are powered on at the master side and there is no dedicated chip to implement this function, the interface circuit recommended by TI corporation is generally designed as a template, the circuit is very complex, and the overall circuit cost is very high.

With the development of technology, smart meters are widely used, and a meter reader (MBUS master station) communicating with various slave stations is used as an MBUS core, so that the demand is increased. The interface circuit of the MBUS master station is a main module of the meter reading device, the performance of the meter reading device is determined by the quality of the performance of the MBUS master station, and meanwhile, the requirements of cost factors, joint sealing and the like are considered. At present, most meter readers are designed by adopting interface circuit design templates given by TI companies, designers generally directly adopt the interface circuit design templates, but the whole circuit design is complex, the cost is high, and the meter readers are not suitable for the requirements of most people on low-price and high-quality products.

Disclosure of Invention

The invention aims to solve the technical problem of providing a method for realizing the MBUS master station in the MBUS gateway aiming at the prior art, and designs a simple, practical, stable, reliable and low-cost MBUS interface circuit of the master station.

The technical scheme for solving the technical problem is as follows: a master station circuit built by analog devices comprises a power supply isolation circuit, a driving circuit, a data transmission conversion circuit and a data receiving analysis circuit. The power supply isolation driving circuit selects 30V and 18V stabilized power supplies to meet the requirement of 12V voltage difference of the MBUS bus, wherein the 30V high voltage drives the optocoupler to control the PMOS tube by a strong drive, and the PMOS tube is in a normally-on state in a static state, keeps unidirectional conduction through a diode, and keeps a normal state, thereby representing logic '1' of the MBUS bus; 18V low voltage keeps unidirectional conduction through a diode, and when 30V voltage is controlled to be switched off, 18V supplies power to a bus. When the Txd port of the processor is logic '0', the high-speed optical coupling isolation device is controlled to be switched on, the driving voltage output by the optical coupling isolation device controls the PMOS tube to be switched off quickly, the quality requirement of a control signal is met, otherwise, the PMOS tube keeps outputting, and the voltage output by the PMOS tube and 18V voltage form a parallel voltage mode through a diode; the diode is used for preventing high voltage from being connected into a low-voltage circuit in series to cause damage. The data sending conversion is to stabilize the parallel voltage formed by the output voltage of the PMOS tube and the 18V voltage at 18V or 30V through a voltage stabilizing tube, then modulate the parallel voltage, and form an MBUS + instruction signal after the modulated signal is restrained and protected, and send the MBUS + instruction signal to a slave station of the MBUS bus. In the data receiving and analyzing circuit, a response signal MBUS-signal of a slave station of the MBUS bus is a current sensitive signal and is converted into a sampling voltage signal through a sampling resistor, and one path of the sampling voltage signal is directly connected to a forward port of a comparator; and the other path of the analog operational amplifier circuit changes high impedance into a low impedance state through an analog operational amplifier voltage follower, outputs sampling follow voltage, the sampling follow voltage and 100 millivolt power supply voltage are output to a forward input end of an analog operational amplifier in parallel through the output (power supply follow voltage) of the analog operational amplifier voltage follower, the output of the analog operational amplifier is amplified sampling voltage, the amplified sampling voltage is output to a reverse input end of a comparator, the sampling follow voltage and the power supply follow voltage are amplified in parallel, stable voltage always exists on an MBUS bus under a constant current state, when a slave station signal exists, voltage fluctuation of 220 plus 400mV is generated on a 20 ohm resistor, the invention takes the lower limit of the fluctuation of 220mV and takes half voltage which is about 100mV, and the voltage of a constant current part plus 100mV is taken as reference voltage, so that the anti-interference performance is improved. The sampling voltage input to the positive input end of the comparator is compared with the amplified sampling voltage of the inverted input end, the output signal obtains logic '0' or logic '1' through a pull-up resistor, inversion is carried out after voltage stabilization, and the inverted signal is input to an Rxd receiving port of the processor.

Optionally, the high-speed optical coupling isolator device adopts a HCPL314J high-speed optical coupling isolator, pin 2 of the HCPL314J high-speed optical coupling isolator is connected with a power supply of a processor through a current-limiting resistor, pin 3 of the HCPL314J high-speed optical coupling isolator is connected with a transmitting port Txd of the processor, pin 16 of the HCPL314J high-speed optical coupling isolator is connected with a 30V power supply, pin 15 of the HCPL314J high-speed optical coupling isolator is connected with a pin G of a PMOS transistor through a current-limiting resistor, pin 14 of the HCPL314J high-speed optical coupling isolator is grounded, and when a processor bit-based transmission instruction is logic "0", pin 15 of the HCPL314J high-speed optical coupling isolator is driven to have a voltage of 30V; when the processor sends a command of logic '1' according to the bit, the HCPL314J high-speed optical coupler isolator pin 15 outputs low voltage.

Optionally, the PMOS transistor of the invention adopts an AP1510P10GH buck converter, a G pin of the AP1510P10GH buck converter is connected to a pin 15 and a 30V power supply of the HCPL314J high-speed opto-isolator through resistors, an S pin of the AP1510P10GH buck converter is connected to a 30V power supply, a D pin of the AP1510P10GH buck converter is connected to a diode, the diode is FR107, when the G pin of the AP1510P10GH buck converter is lower than the S pin and exceeds a threshold voltage, the S pin and the D pin are turned on, and the 30V power supply is output to the diode.

Optionally, the voltage stabilization for the data transmission conversion of the present invention adopts a TVS diode 1SMB30AT 3.

Optionally, the power protection for the data transmission conversion of the present invention adopts RF600 self-recovery insurance.

Optionally, the sampling resistor of the data receiving and analyzing circuit of the present invention is a 20 Ω resistor, one end of the sampling resistor is grounded, and the other end of the sampling resistor is divided into two paths: one path is connected to the positive input end of the comparator LM393, and the other path is connected to the positive input end of the sampling voltage follower LM358 through a 1M resistor. The reverse input end of the sampling voltage follower LM358 is connected with the output end, and the output end of the sampling voltage follower LM358 is connected with a 100K resistor in series to form sampling voltage; supply voltage follower adopts LM358 fortune to put, and treater power supply passes through 100K and the forward input that 3K resistance partial pressure input to LM358, and treater power is connected to 100K resistance one end, and an end connects LM 358's forward input, and 3K resistance one end ground connection, an end connect LM 358's forward input, supply voltage follower LM 358's reverse input links to each other with the output, and the output forms supply voltage through 100K resistance.

Optionally, the amplifier of the data receiving and analyzing circuit of the present invention employs an LM358 operational amplifier, a forward input end of the LM358 operational amplifier is a sampling voltage and a supply voltage, a reverse input end of the LM358 operational amplifier is connected to 2 100K resistors, one of the 2 100K resistors is connected to an output end of the LM358 operational amplifier, the other is grounded, and an output end of the LM358 operational amplifier has a 10K pull-up resistor, and then is connected in series to a 1K current limiting resistor.

Optionally, the data receiving and analyzing circuit of the present invention adopts a TVS diode ESD33 for voltage stabilization, and the inverter adopts a 74AHC14 chip.

Further, the power supply isolation driving adopts a two-stage power supply control method, and the weak signal of the processor controls the optocoupler device and the PMOS tube to generate 30V voltage.

Further, the data receiving and analyzing circuit obtains the voltage change of the MBUS bus by adopting a method of associating and comparing with a processor power supply, specifically, the voltage of about 100mV is obtained by processing the processor power supply, the voltage obtained by processing the processor power supply and the sampling voltage is fused to obtain one path of comparison voltage, the other path of comparison voltage is obtained by sampling voltage, and the two paths of comparison are carried out to obtain the current level of the MBUS bus.

Furthermore, the waterproof joint adopts a thread locking method and is waterproof by placing a rubber pad inside. The waterproof joint is integrally of a circular structure and comprises a joint A and a joint B, the joint A is integrally of a circular structure and comprises an outer column, a rubber pad, a wiring area and an inner column, the outer column is mainly connected with a component, and external threads are arranged on the outer side of a joint surface; the rubber pad is arranged at the bottommost part of the inner column and is a waterproof rubber pad; the wiring area is used for externally connecting wires; the inner column is internally provided with a female head and a male head terminal, the male head corresponds to MBUS +, and the female head corresponds to MBUS-. The B connector and the A connector are of complementary structures, when the waterproof connector is used, the A connector and the B connector are aligned, the B connector is integrally rotated to go deep into the A connector until a certain torque is achieved, the external cable is connected through a terminal of a wiring area, and waterproof glue is coated to further ensure the waterproof effect.

Compared with the prior art, the invention has the following beneficial effects:

the invention is a method for realizing a MBUS master station communication circuit, which adopts an analog device to build up, thereby greatly reducing the cost; the power supply isolation design and the anti-interference design ensure the circuit safety; multiple operational amplifiers are reasonably used, so that the communication quality is ensured; and the design of a strong waterproof joint ensures the reliable connection with the slave station in severe environment. Preferably, the invention not only solves the problems of power supply and data receiving and transmitting of the MBUS communication instrument, but also can realize the purpose of one master and multiple slaves of the MBUS bus, and realize the remote meter reading function of the MBUS bus instrument.

Drawings

Fig. 1 is an overall circuit schematic diagram of an implementation method of an MBUS master station in an MBUS gateway according to the present invention.

Fig. 2 is a schematic diagram of the power supply isolation driving circuit and the data transmission conversion circuit of the invention in fig. 1.

Fig. 3 is a schematic diagram of the data receiving and analyzing circuit of fig. 1 according to the present invention.

Fig. 4 is a sectional view of the watertight connector of the present invention in fig. 1.

Wherein: a, 1.1 of an outer column; a, 1.2 of rubber pad; a, a wiring area 1.3; a, 1.4 of an inner column; 1.4.1 male head A; a, 1.4.2 of female head; b, 2.1 of an outer column; b, 2.2 parts of rubber pads; b, wiring area 2.3; b, 2.4 of an inner column; b, 2.4.1 of male head; b, 2.4.2 of female head; c: 18V; d: 30V; e: MBUS +; f: MBUS-; g: sampling a voltage; vcc: a processor power supply.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

This example is a method for implementing a MBUS master station in a MBUS gateway, and as shown in FIG. 1, a designed MBUS interface circuit of the master station includes a power supply isolation driving circuit, a data transmission conversion circuit, a data receiving analysis circuit and a waterproof connector, wherein the power supply isolation driving circuit, the data transmission conversion circuit, the data receiving analysis circuit and the waterproof connector are arranged in the MBUS interface circuit

The power supply isolation driving circuit uses 18V and 30V regulated power supplies to meet the power supply requirement of an MBUS bus, the 30V is in a normal existing state, the optocoupler HCPL314J is controlled to be conducted when a processor instruction is in a high level, a PMOS tube is driven to output 30V, and 1SMB30AT3 is adopted AT an output end to suppress and protect voltage, so that the safety of a power supply line is ensured.

The data transmission conversion circuit has the functions of converting the logic state change of the port of the processor into high-low voltage change on the circuit, the circuit adopts a secondary power supply control mode, when the transmitting port of the processor is in logic '0', the optical coupler HCPL314J outputs high voltage, and the transmitting line outputs 18V; when the port of the processor is changed into logic '1', the control optocoupler HCPL314J outputs low voltage, and drives the output of the PMOS tube AP1510P10GH to be regulated and modulated again through voltage stabilization, and then the slave station control instruction is sent.

The data receiving and analyzing circuit has the functions of converting the high-low current change of the MBUS line into the logical state change of a processor port, judging by adopting a comparison method, introducing a 20-ohm sampling resistor at the input end of the MBUS bus to sample current to voltage, and directly adding one path of sampling voltage to the positive input end of the comparator LM 393; the other path of the sampling voltage is subjected to voltage conversion through a voltage follower formed by an operational amplifier LM358(IC 101A); the processor power supply performs voltage conversion through a voltage follower formed by LM358(IC 102A); the output of the operational amplifier LM358(IC101A) and the output of the LM358(IC102A) are connected in parallel, half of the superposed voltage is obtained, then the superposed voltage is added to an amplifier (adopting voltage) end which is 2 times that of the operational amplifier LM358(IC101B), a comparison voltage which is 100 millivolts higher than the bus voltage is obtained, and then the comparison voltage is added to a comparator LM 393; the sampled voltage is compared with the sampled voltage through the comparator LM393, and a signal meeting the performance of the processor port is output after voltage stabilization and inversion are carried out through the pull-up resistor.

Referring to the dotted line part of fig. 2, the power supply isolation driving circuit uses C18V and D30V regulated power supplies to realize the level discrimination of the MBUS voltage drop of 12V, D30V is in a normal existing state, that is, the MBUS line is at a high level at this time, when a low level is required, the processor controls the high-speed strong driving capability optocoupler HCPL314J to output a high level, the PMOS transistor AP1510P10GH is turned off, at this time, the MBUS line is output by C18V and stabilizes the voltage, that is, the MBUS line is at a low level state. Meanwhile, the D30V and the C18V both adopt diodes to realize one-way conduction, so that the power supply is prevented from being damaged; and the voltage suppression and protection are carried out AT the output end of the whole line by adopting 1SMB30AT3, so that the safety of a power supply line is ensured.

Optionally, the high-speed optical coupler isolator is an HCPL314J high-speed optical coupler isolator, pin 2 of the HCPL314J high-speed optical coupler isolator is connected with a power supply of a processor through a 200 Ω current-limiting resistor, pin 3 of the HCPL314J high-speed optical coupler isolator is connected with a transmitting port Txd of the processor, pin 16 of the HCPL314J high-speed optical coupler isolator is connected with a 30V power supply, pin 15 of the HCPL314J high-speed optical coupler isolator is connected with a pin G of a PMOS transistor through a 100 Ω current-limiting resistor, and pin 14 of the HCPL314J high-speed optical coupler isolator is grounded. The HCPL314J high-speed optical coupling isolator is a primary stage controlled by a secondary power supply and is controlled by a transmitting port of a processor, when a bit-wise sending instruction of the processor is logic '0', the HCPL314J high-speed optical coupling isolator outputs high level, and the driving voltage of a pin 15 of the high-speed optical coupling isolator is 30V; when the processor sends a command of logic '1' according to the bit, the HCPL314J high-speed optical coupling isolator outputs low level, and a pin 15 of the HCPL314J high-speed optical coupling isolator outputs low voltage to control a PMOS tube to realize secondary control.

Optionally, the PMOS transistor adopts an AP1510P10GH buck converter, a G pin of the AP1510P10GH buck converter is connected to a pin 15 of the HCPL314J high-speed optical isolator and a power supply of the D30V through a 100K resistor, an S pin of the AP1510P10GH buck converter is connected to a power supply of the D30V, a D pin of the AP1510P10GH buck converter is connected to a diode, the diode is FR107, when a voltage of the G pin of the AP1510P10GH buck converter is lower than a voltage of the S pin and exceeds a threshold value, the S pin and the D pin are turned on, the power supply of the D30V is output to the diode FR107, and the AP1510P10GH is a final control terminal of the power supply.

Referring to fig. 2, the data transmission conversion circuit regulates the parallel voltage of C18V and D30V through TVS diodes, and performs signal modulation through a modulation chip, thereby generating an MBUS + signal.

Optionally, the voltage stabilization for data transmission and conversion in the invention adopts a TVS diode 1SMB30AT3, which ensures that the line voltage is not higher than D30V, and ensures that the slave station is not damaged by the circuit.

Optionally, the protection of the data transmission conversion of the present invention adopts RF600 self-recovery insurance to prevent the bus short circuit from damaging the master station.

Referring to fig. 3, the data receiving and analyzing circuit of the implementation method of the MBUS master station in the MBUS gateway has the functions of converting the high-low voltage change of the MBUS line into the logical state change of the processor port, the circuit adopts a comparison method for judgment, the input is the MBUS bus voltage, because the line senses the current change rule, a sampling resistor is introduced at the input end for sampling the current to the voltage, and 1 path of sampling voltage is directly added to the positive input end of the comparator; the other 1 path of the driving sample voltage is added to the positive input end of the operational amplifier IC101A through a resistor, the inverting input end of the operational amplifier IC101A is connected with the output end to form a voltage follower, and caching and isolation from high impedance to low impedance are completed; the processor power supply is divided by two resistors and is added to the positive input end of the operational amplifier IC102A, the inverting input end of the operational amplifier IC102A is connected with the output end to form a voltage follower, high impedance to low impedance caching and isolation are completed, the output of the IC102A is Vout which is Vcc (R103/(R102 + R103)), wherein Vcc is the processor power supply, the calculation result is 96mV when Vcc is 3.3V, the output of the operational amplifier IC101A and the output of the IC102A are added, and the divided voltage is added to the positive input end of the operational amplifier IC101BThe operational amplifier IC101B is in amplifying mode at its input terminal, and its output is Vout ═ V_{Positive direction input}((R106+ R107)/R106), the operational amplifier IC101B is a 2-fold amplifier, and the output (called the sampling voltage) of the operational amplifier IC101B is applied to the inverting input of the comparator; comparing the sampling voltage with the sampling voltage through a comparator, wherein when the sampling voltage is greater than the sampling voltage, the output of the comparator is changed into Vcc through a pull-up resistor, and when the sampling voltage is less than the sampling voltage, the output of the comparator is changed into about 0V through the pull-up resistor; the output of the comparator is inhibited by a voltage stabilizing tube ESD33 and then is added to an inverter, and the output of the comparator is inverted and then is sent to a processor connection port to obtain real data.

Optionally, the amplifier of the data receiving and analyzing circuit of the present invention employs an LM358 operational amplifier, a forward input end of the LM358 operational amplifier is a sampling voltage and a supply voltage, a reverse input end of the LM358 operational amplifier is connected to 2 100K resistors, one of the 2 100K resistors is connected to an output end of the LM358 operational amplifier, the other resistor is grounded, an output end of the LM358 operational amplifier has a 10K pull-up resistor, and one of the pull-up resistor is connected to a processor power supply and then connected in series to a 1K current limiting resistor.

Optionally, the data receiving and analyzing circuit of the present invention adopts an ESD33 voltage stabilizing chip, one end of the ESD33 voltage stabilizing chip is grounded, and the inverter adopts a 74AHC14 chip, and one of the two is connected to the receiving port of the processor.

Referring to fig. 4, the waterproof joint is of a circular structure and is divided into an a joint 1 and a B joint 2, and the whole waterproof joint is of a circular structure. The joint A is divided into an outer column A1.1, a rubber pad A1.2, a wiring area A1.3 and an inner column A1.4, wherein the outer side of the joint surface of the outer column A is provided with external threads for locking with the internal threads of the joint B; the rubber gasket A1.2 is a waterproof rubber gasket and is tightly attached to the corresponding structure of the inner column B2.4; the wiring area A1.3 is a wiring area of 2 circuits, an outer cover is used for screw fixation, and hot glue is additionally coated to prevent water; the inner column A1.4 is internally provided with a female head A1.4.1 and a male head A1.4.2, the female head A1.4.1 is made of elastic material and is arranged according to the shape of an inverted gourd and is in effective contact with the male head B2.4.1 corresponding to MBUS +, and the male head A1.4.2 is in the shape of an elastic stripe banana and is in effective contact with the female head B2.4.2 corresponding to MBUS-. The joint B is divided into an outer column B2.1, a rubber pad B2.2, a wiring area B2.3 and an inner column B2.4, wherein the inner side of the joint surface of the outer column B2.1 is provided with external threads for locking with the external threads of the joint A; the rubber gasket B2.2 is a waterproof rubber gasket and is tightly attached to the corresponding structure of the inner column A1.4; the wiring area B2.3 is a wiring area of 2 circuits, and is fixed by screws through an outer cover and is waterproof through hot glue coating; the B inner column 2.4 internally comprises a B male head 2.4.1 and a B female head 2.4.2, the B female head 2.4.2 is made of elastic material and is arranged according to the shape of an inverted gourd and corresponds to MBUS-, and the B male head is effectively contacted with the A male head, and the B male head is in the shape of an elastic stripe banana and corresponds to MBUS +, and the B male head is effectively contacted with the A female head. A gap is reserved in the wiring areas A and B, a small amount of moisture can be stored, and evaporation is carried out through heating of the cable. During the use, with A and B joint public female head to good, in the whole rotatory B joint deepened A joint, stop until having certain moment, external cable connects through the terminal in A and B wiring district, adds and scribbles waterproof glue and can further guarantee water-proof effects.

Further, the power supply isolation driving adopts a two-stage power supply control method, and the weak signal of the processor controls the optocoupler device and the PMOS tube to generate D30V voltage. The input is the processor port level, when the processor originating port is in logic '0' (namely low level), the high-speed strong driving capability opto-coupler HCPL314J is in the cut-off state, no driving signal is output, and the whole transmitting line is in the C18V output state; when the port of the processor is changed into logic '1' (namely high level), the high-speed strong-driving-capacity optical coupler HCPL314J is controlled to enter a conducting state, a driving signal is output to drive the PMOS tube AP1510P10GH to output D30V, and at the moment, the whole transmission line is in a D30V output state, so that secondary power control is realized.

Further, the data receiving and analyzing circuit obtains the voltage change of the MBUS bus by a method of associating and comparing with a processor power supply, particularly, because the MBUS-voltage fluctuation of 220mV-400mV appears on a sampling resistor when the voltage changes, the invention adopts a method of taking the lower limit of 220mV to be about 100mV for conditioning, the 100mV voltage is obtained by processing the processor power supply and is fused with the voltage obtained by processing the sampling voltage to obtain one path of comparison voltage, the other path of comparison voltage is obtained by sampling voltage, the two paths of comparison are used for obtaining the current level of the MBUS bus, the power supply of the processor and the MBUS bus voltage are effectively integrated and conditioned, and the anti-interference performance of the line is ensured.

Furthermore, the waterproof joint adopts a thread locking method and is waterproof by placing a rubber pad inside.

Test example:

the circuit of the invention is in butt joint test with the LXS-20D electronic intelligent water meter of Hangzhou competitive bidding, the meter is read once every second, ten minutes are read continuously, the feedback information is completely correct, and the transmitting and receiving circuit completely meets the use requirement.

In addition to the above embodiments, the present invention also includes other embodiments, and any technical solutions formed by equivalent transformation or equivalent replacement should fall within the scope of the claims of the present invention.

Claims

1. A method for realizing an MBUS master station in an MBUS gateway is characterized in that: drive circuit, data transmission converting circuit, data reception analytic circuit are kept apart including the power supply to and with the supporting water joint who uses of slave station data transmission, wherein:

the power supply isolation driving circuit is controlled by the processor to control the strong driving optocoupler to switch on and off the high-voltage power supply, and prevents the power supply from flowing backwards through the series diode;

the data transmission conversion circuit is controlled by the level of a processor port, the strong drive optocoupler senses and controls the level change to realize the on-off of the drive power supply, and then the PMOS tube realizes the alternate change of the high-low voltage power supply, and 12V differential pressure is formed after voltage stabilization and modulation;

the data receiving and analyzing circuit has the functions of realizing level conversion, converting the MBUS bus level into a processor port allowable level, completing the conversion by adopting a comparison method, converting a current signal into a voltage signal through a sampling resistor as a reference voltage of a comparator, comparing the voltage signal with the fluctuation voltage generated during MBUS bus communication and the processor power supply voltage, and performing voltage stabilization and phase inversion on the output of the comparator so that the processor can obtain correct data meeting the port level requirement;

the waterproof joint adopts a rubber gasket and a long water channel design and is safely connected with the slave station;

the strong driving optical coupler device adopts a HCPL314J high-speed optical coupler isolator, a pin 2 of the HCPL314J high-speed optical coupler isolator is connected with a power supply of a processor through a 200 omega current-limiting resistor, a pin 3 of the HCPL314J high-speed optical coupler isolator is connected with a transmitting port Txd of the processor, a pin 16 of the HCPL314J high-speed optical coupler isolator is connected with a 30V power supply, a pin 15 of the HCPL314J high-speed optical coupler isolator is connected with a pin G of a PMOS (P-channel metal oxide semiconductor) tube through a 100 omega current-limiting resistor, and a pin 14 of the HCPL314J high-speed optical coupler isolator is grounded.

2. The method of claim 1, wherein the method comprises: the power supply isolation driving circuit adopts a secondary power supply control mode, a primary high-speed strong-driving-capacity optocoupler HCPL314J device is controlled by a processor to realize voltage isolation and drive output of a secondary control signal, and a secondary PMOS (P-channel metal oxide semiconductor) tube AP1510P10GH is adopted to realize fast switching of high voltage.

3. The method of claim 1, wherein the method comprises: the power supply isolation driving circuit uses 18V and 30V regulated power supplies to form 12V voltage difference, diodes are respectively connected to prevent current backflow, and the whole output adopts 1SMB30AT3 to carry out voltage suppression and protection.

4. The method of claim 1, wherein the method comprises: the HCPL314J high-speed optical coupling isolator is a primary stage controlled by a secondary power supply and is controlled by a transmitting port of a processor, and when a bit-wise sending instruction of the processor is logic '0', a pin 15 of the HCPL314J high-speed optical coupling isolator outputs high voltage; when the processor sends a command in a bit-by-bit mode to be logic '1', the pin 15 of the HCPL314J high-speed optical coupling isolator outputs low voltage to control a PMOS tube to realize secondary control.

5. The method of claim 4, wherein the method comprises: the PMOS tube adopts an AP1510P10GH buck converter, a G pin of the AP1510P10GH buck converter is respectively connected with a pin 15 of the HCPL314J high-speed optical coupling isolator and a D30V power supply through a 100K resistor, an S pin of the AP1510P10GH buck converter is connected with a D30V power supply, a D pin of the AP1510P10GH buck converter is connected with a diode, the diode is FR107, when the G pin of the AP1510P10GH buck converter is lower than an S pole and exceeds a threshold voltage, the S pin and the D pin are conducted, the D30V power supply is output to the diode FR107, and the AP1510P10GH buck converter is a final control end of the power supply.

6. The method of claim 1, wherein the method comprises: the data receiving and analyzing circuit samples signals in an electrorheological voltage mode, a sampling resistor is 20 ohms, the resistance voltage variation caused by signal variation is 220-plus-400 mV, bus voltage + lower limit 220mV is divided by half 100mV and used as reference voltage to enter a comparator, and 100mV is generated by the power supply voltage of a processor.

7. The method of claim 1, wherein the method comprises: the data receiving and analyzing circuit adopts a 20 omega resistor as a sampling resistor, one end of the sampling resistor is grounded, and the other end of the sampling resistor is divided into two paths: one path is connected to the positive input end of the comparator LM393, the other path is connected to the positive input end of the sampling voltage follower LM358 through a 1M resistor, the reverse input end of the sampling voltage follower LM358 is connected with the output end, and the output end of the sampling voltage follower LM358 is connected with a 100K resistor in series to form sampling voltage; supply voltage follower adopts LM358 fortune to put, and treater power supply passes through 100K and the forward input of 3K resistance partial pressure input to LM358, and treater power is connected to 100K resistance one end, and an end connects LM 358's forward input, and 3K resistance one end ground connection, an end connect LM 358's forward input, and supply voltage follower LM 358's reverse input links to each other with the output, and the output forms supply voltage through 100K resistance.

8. The method of claim 1, wherein the method comprises: the waterproof connector is integrally of a circular structure and is divided into a connector A and a connector B, and the waterproof connector is integrally of a circular structure.

9. The method of claim 8, wherein the method comprises: the joint A is divided into an outer column A, a rubber pad A, a wiring area A and an inner column A, and external threads are arranged on the outer side of the joint surface of the outer column A and locked with the internal threads of the joint B; the rubber gasket A is a waterproof rubber gasket and is tightly attached to the corresponding structure of the inner column B; the wiring area A is a wiring area of 2 circuits, an outer cover is used for screw fixation, and hot glue is coated for water prevention; the inner column A comprises a female head A and a male head A, the female head A is made of elastic materials and is arranged according to the shape of a reversed gourd and is in effective contact with the male head B corresponding to MBUS +, and the male head A is made of elastic stripe banana and is in effective contact with the female head B corresponding to MBUS-; the joint B is divided into an outer column B, a rubber pad B, a wiring area B and an inner column B, wherein the inner side of the joint surface of the outer column B is provided with an external thread for locking with the external thread of the joint A; the rubber gasket B is a waterproof rubber gasket and is tightly attached to the corresponding structure of the inner column A; the wiring area B is a wiring area of 2 circuits, an outer cover is used for screw fixation, and hot glue is coated for water prevention; the B inner column is internally provided with a B male head and a B female head, the B female head is made of elastic materials and is arranged according to the shape of an inverted gourd and corresponds to the shape of MBUS-, the B male head is effectively contacted with the A male head, the B male head is in the shape of an elastic stripe banana and corresponds to the shape of MBUS +, and the B male head is effectively contacted with the A female head.