CN112332647B - Valley locking circuit, chip and power supply based on quasi-resonance control technology - Google Patents
Valley locking circuit, chip and power supply based on quasi-resonance control technology Download PDFInfo
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
- H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/3353—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having at least two simultaneously operating switches on the input side, e.g. "double forward" or "double (switched) flyback" converter
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The invention provides a valley bottom locking circuit, a chip and a power supply based on a quasi-resonance control technology, wherein in the valley bottom locking circuit, the output end of a FB comparison detection module and the output end of a ZCD comparison detection module are respectively connected to the input end of a logic operation module, and the output end of the logic operation module is connected to a driving module; the FB comparison detection module compares and counts signals output by the isolation optocouplers in the switching power supply and outputs a reference valley value; the ZCD comparison detection module compares and counts signals output by an auxiliary winding of the transformer T1 in each switching period of the switching power supply and outputs real-time valley numbers; the logic operation module generates valley bottom opening pulses according to the reference valley number and the real-time valley number, and transmits the valley bottom opening pulses to the driving module, so that the driving module outputs control signals to be transmitted to a high-voltage switching tube of the switching power supply. The circuit solves the frequency jitter problem that two adjacent valleys are alternately opened in the prior art and the problem that the reference valley number is difficult to acquire.
Description
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to a valley locking circuit, a chip and a power supply based on a quasi-resonance control technology.
Background
The traditional switching power supply adopts a PWM control technology, and the switch of a switching tube is controlled by an internal oscillator of a chip to be opened at a set moment. Since the switching tube has a relatively high operating voltage and a large parasitic capacitance, there is a relatively large switching loss. In order to further improve the conversion efficiency of the switching power supply, a quasi-resonance control technology conducted at the bottom of the resonance valley is developed by referring to the control principle of the resonance power supply. At the bottom of the resonance valley, the voltage at the drain end of the switching tube is the lowest, and the switching loss is correspondingly reduced. Therefore, by detecting the position of the resonance valley bottom, the switching tube is controlled to be opened at the valley bottom, and the switching loss of the switching tube can be reduced to the greatest extent.
But since the valley position will vary with the input voltage and load, there is a problem in that it is difficult to lock the valley and frequency jitter. Under a specific load, the frequency change caused by the alternate opening of two adjacent valleys can occur if the dithering frequency is in the range of the auditory frequency of the human ear, and the situation that the transformer generates audio noise can occur. The prior art has the problem that the reference valley number is difficult to obtain, for example, in the patent of application number 201721068719.4, the resonant voltage potential valley value needs to be counted to obtain the reference valley number.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides a valley locking circuit, a chip and a power supply based on a quasi-resonance control technology, which solve the frequency jitter problem that two adjacent valleys are alternately opened and the problem that the reference valley number is difficult to acquire in the prior art.
In a first aspect, a valley lock circuit based on quasi-resonant control technique,
The system comprises an FB comparison detection module, a ZCD comparison detection module and a logic operation module; the output end of the FB comparison detection module and the output end of the ZCD comparison detection module are respectively connected to the input end of the logic operation module, and the output end of the logic operation module is connected to the driving module;
The FB comparison detection module is used for comparing and counting signals output by the isolation optocouplers in the switching power supply and outputting reference valley numbers; the ZCD comparison detection module is used for comparing and counting signals output by the auxiliary winding of the transformer T1 in each switching period of the switching power supply and outputting real-time valley numbers; the logic operation module is used for generating valley bottom opening pulses according to the reference valley number and the real-time valley number and transmitting the valley bottom opening pulses to the driving module, so that the driving module outputs control signals to be transmitted to a high-voltage switching tube of the switching power supply.
Preferably, the FB comparison detection module includes a reference voltage selection unit, a comparator Cmp1, a comparator Cmp2, an exclusive or gate Xnor, and a first counter;
the high voltage output end of the reference voltage selection unit is connected with the positive input end of the comparator Cmp1, the low voltage output end of the reference voltage selection unit is connected with the positive input end of the comparator Cmp2, and the reverse input end of the comparator Cmp1 and the reverse input end of the comparator Cmp2 are both connected to signals output by the isolation optocoupler of the switching power supply; the output end of the comparator Cmp1 is respectively connected to one input end of the exclusive-or gate Xnor and the Add end of the first counter, the output end of the comparator Cmp2 is respectively connected to the other input end of the exclusive-or gate Xnor and the Sub end of the first counter, the output end of the exclusive-or gate Xnor is connected to the enabling end of the first counter, the clock end of the first counter is connected to the clock signal, and the output end of the first counter is connected to the selection end of the reference voltage selection unit;
The output end of the first counter is used as the output end of the FB comparison detection module.
Preferably, the reference voltage selecting unit is provided with a plurality of reference voltages, and the reference voltage selecting unit is used for selecting corresponding reference voltages according to the input signals of the selecting terminals to be respectively output from the high voltage output terminal and the low voltage output terminal.
Preferably, the reference voltage output by the high voltage output end in the reference voltage selecting unit is larger than the reference voltage output by the low voltage output end.
Preferably, the ZCD comparison detection module comprises a comparator Cmp3 and a second counter;
The reverse input end of the comparator Cmp3 is connected with a signal output by an auxiliary winding of the transformer T1 in the switching power supply, the forward input end of the comparator Cmp3 is connected with a preset voltage comparison threshold value, and the output end of the comparator Cmp3 is connected with a clock end of the second counter;
the reset end of the second counter is connected to the control signal output by the driving module, and the output end of the second counter is used as the output end of the ZCD comparison detection module.
Preferably, the logic operation module is used for outputting high level to be transmitted to the driving module when the reference valley number and the real-time valley number are detected to be equal.
Preferably, the logic operation module comprises a first decoder, a second decoder and a logic unit;
The input end of the first decoder is connected with the output end of the FB comparison detection module, the input end of the second decoder is connected with the output end of the ZCD comparison detection module, the first decoder and the second decoder are connected with the output end of the logic unit, and the output end of the logic unit is used as the output end of the logic operation module.
In a second aspect, a power chip includes a peak current monitoring circuit and a drive module,
The device also comprises a valley locking circuit; the output end of the valley locking circuit and the output end of the peak current monitoring circuit are respectively connected to the input end of the driving module, and the output end of the driving module is connected with a high-voltage switching tube of the switching power supply;
The valley bottom locking circuit comprises an FB comparison detection module, a ZCD comparison detection module and a logic operation module; the output end of the FB comparison detection module and the output end of the ZCD comparison detection module are respectively connected to the input end of the logic operation module, and the output end of the logic operation module is connected to the first input end of the driving module; the FB comparison detection module is used for comparing and counting signals output by the isolation optocouplers in the switching power supply and outputting reference valley numbers; the ZCD comparison detection module is used for comparing and counting signals output by the auxiliary winding of the transformer T1 in each switching period of the switching power supply and outputting real-time valley numbers; the logic operation module is used for outputting a valley bottom opening pulse according to the reference valley number and the real-time valley number;
the input end of the peak current monitoring circuit is also respectively connected with a signal output by the isolation optocoupler in the switching power supply and a high-voltage switching tube of the switching power supply.
In a third aspect, a switching power supply includes a high-voltage switching tube, a transformer T1, an optocoupler, and a power chip according to the second aspect.
According to the technical scheme, the valley locking circuit, the chip and the power supply based on the quasi-resonance control technology solve the frequency jitter problem that two adjacent valleys are alternately opened and the problem that the reference valley number is difficult to acquire in the prior art.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. Like elements or portions are generally identified by like reference numerals throughout the several figures. In the drawings, elements or portions thereof are not necessarily drawn to scale.
Fig. 1 is a block diagram of a valley lock circuit according to an embodiment of the present invention.
Fig. 2 is a circuit diagram of an FB comparison detection module according to an embodiment of the invention.
Fig. 3 is a schematic diagram of a valley bottom reference value generated by an FB signal in accordance with a first embodiment of the present invention.
Fig. 4 is a circuit diagram of a ZCD comparison detection module according to an embodiment of the invention.
Fig. 5 is a schematic diagram of ZCD comparison detection and real-time valley count in accordance with an embodiment of the present invention.
Fig. 6 is a circuit diagram of a logic operation module according to an embodiment of the invention.
Fig. 7 is a block diagram of a power chip according to a second embodiment of the present invention.
Fig. 8 is a circuit schematic diagram of a switching power supply according to a third embodiment of the present invention.
Detailed Description
Embodiments of the technical scheme of the present application will be described in detail below with reference to the accompanying drawings. The following examples are only for more clearly illustrating the technical aspects of the present application, and thus are merely examples, and are not intended to limit the scope of the present application. It is noted that unless otherwise indicated, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which this application belongs.
It should be understood that the terms "comprises" and "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
As used in this specification and the appended claims, the term "if" may be interpreted as "when..once" or "in response to a determination" or "in response to detection" depending on the context. Similarly, the phrase "if a determination" or "if a [ described condition or event ] is detected" may be interpreted in the context of meaning "upon determination" or "in response to determination" or "upon detection of a [ described condition or event ]" or "in response to detection of a [ described condition or event ]".
Embodiment one:
A valley lock circuit based on quasi-resonant control technique, see figure 1,
The system comprises an FB comparison detection module, a ZCD comparison detection module and a logic operation module; the output end of the FB comparison detection module and the output end of the ZCD comparison detection module are respectively connected to the input end of the logic operation module, and the output end of the logic operation module is connected to the driving module;
The FB comparison detection module is used for comparing and counting signals output by the isolation optocouplers in the switching power supply and outputting reference valley numbers; the ZCD comparison detection module is used for comparing and counting signals output by the auxiliary winding of the transformer T1 in each switching period of the switching power supply and outputting real-time valley numbers; the logic operation module is used for generating valley bottom opening pulses according to the reference valley number and the real-time valley number and transmitting the valley bottom opening pulses to the driving module, so that the driving module outputs control signals to be transmitted to a high-voltage switching tube of the switching power supply.
Specifically, the principle of the quasi-resonant control technique is to control the high-voltage switching tube U5 to open at the valley bottom of the Drain oscillation waveform. Since Vds of the high voltage switching tube U5 is the lowest at this time, switching loss can be effectively reduced, so that the efficiency of the switching power supply can be provided or the switching frequency can be further improved.
As can be seen from the Drain oscillation waveform of fig. 5, if the switch controlled high voltage switching transistor U5 is turned on at the valley of the Drain oscillation waveform, the switching frequency will become hopped because the valley position is hopped. If the bottom is opened and jumped to the bottom 2 from the bottom 3, the switching frequency is increased more, the FB signal voltage is reduced under the action of the loop, and if the loop is not controlled, the loop may be opened at the bottom 3 next time. In this way, the power chip has a phenomenon that the high-voltage switch tube U5 is alternately opened between two adjacent valley bottoms (such as the valley bottom 2 and the valley bottom 3) under a specific load.
The valley locking circuit obtains the reference valley number by detecting the signal (namely the FB signal) output by the isolation optocoupler of the switching power supply, and sets a larger hysteresis voltage for the FB signal to realize the valley locking function. And then counting the valley number of a signal (namely ZCD signal) output by an auxiliary winding of the transformer T1 in the switching power supply every switching period to obtain the real-time valley number. When the valley bottom number of the ZCD signal is the same as the reference valley number, the logic operation module outputs a valley bottom opening pulse and transmits the valley bottom opening pulse to the driving module, so that the driving module outputs a DRV signal to a high-voltage switching tube of the switching power supply, and the high-voltage switching tube is opened to realize a quasi-resonance control technology of valley bottom opening. The valley locking circuit has the advantages of simple acquisition of reference valley number, stable valley locking and no audio noise.
Referring to fig. 2, the FB comparison detection module includes a reference voltage selection unit, a comparator Cmp1, a comparator Cmp2, an exclusive or gate Xnor, and a first counter;
the high voltage output end of the reference voltage selection unit is connected with the positive input end of the comparator Cmp1, the low voltage output end of the reference voltage selection unit is connected with the positive input end of the comparator Cmp2, and the reverse input end of the comparator Cmp1 and the reverse input end of the comparator Cmp2 are both connected to signals output by the isolation optocoupler of the switching power supply; the output end of the comparator Cmp1 is respectively connected to one input end of the exclusive-or gate Xnor and the Add end of the first counter, the output end of the comparator Cmp2 is respectively connected to the other input end of the exclusive-or gate Xnor and the Sub end of the first counter, the output end of the exclusive-or gate Xnor is connected to the enabling end of the first counter, the clock end of the first counter is connected to the clock signal, and the output end of the first counter is connected to the selection end of the reference voltage selection unit;
The output end of the first counter is used as the output end of the FB comparison detection module.
Specifically, in the FB comparison detection module, the FB signal is compared with VH (i.e., the high voltage output terminal of the reference voltage selection unit) and VL (i.e., the high voltage output terminal of the reference voltage selection unit) reference voltages by two comparators Cmp1 and Cmp2, respectively. The outputs of comparators Cmp1 and Cmp2 are fed to an exclusive or gate Xnor, the output of exclusive or gate Xnor is connected to the enable terminal of the first counter, while the output of comparator Cmp1 is connected to the Add terminal of the first counter and the output of comparator Cmp2 is connected to the Sub terminal of the first counter. The output reference valley number of the first counter is simultaneously returned to the reference voltage selecting unit. The reference voltage selecting unit selects specific output voltages of VH and VL by referring to the valley number, for example, vl=v1 when vh=v3 in fig. 3, and vl=v2 when vh=v4.
When the voltage of the FB signal is between VH and VL, the voltage of the FB signal is less than VH, the comparator Cmp1 outputs a high level, the voltage of the FB signal is greater than VL, the comparator Cmp2 outputs a high level, and the exclusive-or gate Xnor outputs a low level, so that the first counter is not enabled to count, and the VH and VL reference voltages remain unchanged.
If the FB signal rises in voltage and is higher than VH (vh=v3), the comparator Cmp1 outputs a low level, the comparator Cmp2 outputs a high level, and the output of the exclusive-or gate Xnor is thus high, so that the first counter starts counting, the comparator Cmp1 outputs a low level to the Add end of the first counter, the first counter is set to an addition mode, and when the clock CLK rises, the first counter is increased by 1, and the output reference valley number is also increased by 1. After the reference valley value is added by 1, the feedback is fed back to the reference voltage selecting unit, and the reference voltage selecting unit selects a higher reference voltage output, namely, outputs vh=v1a, vl=v3a, wherein V1a > V1, and V3a > V3. Since the VH and VL reference voltages are increased so that the VH voltage is higher than the voltage of the FB signal, the comparator Cmp1 outputs a high level, the comparator Cmp2 outputs a high level, the first counter stops counting, and the reference valley number is maintained unchanged. If the voltage of the FB signal continues to rise above the VH reference voltage, then the same applies the first counter by 1 and the VH and VL reference voltages again increase.
If the FB signal voltage decreases below VL, the comparator Cmp2 outputs a low level, and the comparator Cmp1 outputs a high level, so that the exclusive-or gate Xnor outputs a high level, thereby enabling the first counter to start counting, the comparator Cmp2 outputs a low level to the Sub-end of the first counter, the first counter is set to a subtraction mode, and when the clock CLK goes up, the first counter is decremented by 1, and the output reference valley number is also decremented by 1. After subtracting 1 from the reference valley number, the feedback is fed back to the reference voltage selecting unit, and the reference voltage selecting unit selects a lower reference voltage output, i.e. outputs vh=v1, vl=v3. Therefore, the first counter is incremented by 1 after the voltage of the FB signal is higher than the voltage V3, and is decremented by 1 after the voltage of the FB signal is lower than the voltage V1 a. Since V1a to V3 have relatively large voltage hysteresis, system noise caused by frequent switching between two reference valley numbers is avoided.
Referring to fig. 3, the reference voltage selecting unit is provided with a plurality of reference voltages, and the reference voltage selecting unit is used for selecting corresponding reference voltages according to the input signals of the selecting terminals to be respectively output from the high voltage output terminal and the low voltage output terminal.
Preferably, the reference voltage output by the high voltage output end in the reference voltage selecting unit is larger than the reference voltage output by the low voltage output end.
Specifically, fig. 3 is a reference valley number obtained by detecting the voltage of the FB signal. Fig. 3 sets 5 high thresholds (not limited to 5), and sets 5 low thresholds (not limited to 5). The FB signal is divided into 6 voltage intervals by 5 high thresholds, corresponding to 6 reference valley numbers, e.g., V3 and V4 are two high threshold values. The same 5 low thresholds divide the FB signal into 6 voltage intervals corresponding to 6 reference valley numbers, e.g., V1 and V2 are the two low threshold values. When the voltage of the FB signal is lower than the V1 voltage, the reference valley number is 6. Only after the voltage of FB signal is greater than V3, the reference valley number is changed from 6 to 5. Similarly, when the reference valley number is 5, the reference valley number is changed from 5 to 6 only after the voltage of the FB signal is smaller than the V3 voltage. The voltage difference between V1 and V3 is hysteresis of 6 to 5 of valley value, so that the reference valley value is kept unchanged in a larger FB voltage interval, and the valley locking function is realized. Similarly, when the voltage of the FB signal is greater than V4, the reference valley number is changed from 2 to 1, and when the voltage of the FB signal is lower than V2, the reference valley number is changed from 1 to 2. When the reference valley number is 1, the voltage of the FB signal is greater than V2, which maintains the state of the reference valley number 1.
Referring to fig. 4 and 5, the ZCD comparison detection module includes a comparator Cmp3 and a second counter;
The reverse input end of the comparator Cmp3 is connected with a signal output by an auxiliary winding of the transformer T1 in the switching power supply, the forward input end of the comparator Cmp3 is connected with a preset voltage comparison threshold value, and the output end of the comparator Cmp3 is connected with a clock end of the second counter;
the reset end of the second counter is connected to the control signal output by the driving module, and the output end of the second counter is used as the output end of the ZCD comparison detection module.
Specifically, the ZCD voltage (i.e. the signal output by the auxiliary winding of the transformer T1 in the switching power supply) is compared with a set voltage comparison threshold Vref (e.g. 60 mV), when the ZCD is lower than the voltage comparison threshold Vref, the comparator outputs a high level, the comparator outputs zcd_cmp to the clock end of the second counter, the zcd_cmp outputs a pulse rising edge, the second counter adds 1, and the count value of the second counter is output in real time as the real-time valley number. And meanwhile, when the control signal output by the driving module outputs a high level, the second counter is reset. So that the second counter counts the valley of the ZCD in real time every cycle.
When the DRV signal is at a high level, the high-voltage switching tube U5 is turned on, the Drain voltage becomes low, the current of the transformer T1 increases, and the switching tube is turned off after the DRV signal becomes low, so that the Drain voltage flyback generates a higher voltage. When the transformer demagnetizes, the Drain terminal voltage starts to oscillate, and the AUX output terminal voltage waveform of the transformer and the Drain terminal voltage waveform form a proportion due to the action of the transformer. The voltage is divided by R1, D5 and R3 and then sent to the ZCD input end, and the low level of the ZCD is clamped at-0.7V because the diode is arranged at the ZCD and GND ends of the power chip input end. The ZCD comparison detection module outputs a high level when detecting that the ZCD voltage is lower than a set threshold (e.g. 0V), as shown in the zcd_cmp waveform of fig. 5. The ZCD comparison detection module resets the second counter when the DRV is opened, and then the valley bottom count at the rising edge of each ZCD is increased by 1.
Preferably, the logic operation module is used for outputting high level to be transmitted to the driving module when the reference valley number and the real-time valley number are detected to be equal.
Referring to fig. 6, the logic operation module includes a first decoder, a second decoder, and a logic unit;
The input end of the first decoder is connected with the output end of the FB comparison detection module, the input end of the second decoder is connected with the output end of the ZCD comparison detection module, the first decoder and the second decoder are connected with the output end of the logic unit, and the output end of the logic unit is used as the output end of the logic operation module.
Specifically, fig. 6 is a logic operation module circuit, where the reference valley number and the real-time valley number are decoded by a decoder (e.g. 3-8 decoder) and then AND-logic is performed by an AND gate, and when the real-time valley number is equal to the reference valley number, a high level is output.
Embodiment two:
Referring to fig. 7, a power chip includes a valley lock circuit, a peak current monitoring circuit and a driving module,
The device also comprises a valley locking circuit; the output end of the valley locking circuit and the output end of the peak current monitoring circuit are respectively connected to the input end of the driving module, and the output end of the driving module is connected with a high-voltage switching tube of the switching power supply;
The valley bottom locking circuit comprises an FB comparison detection module, a ZCD comparison detection module and a logic operation module; the output end of the FB comparison detection module and the output end of the ZCD comparison detection module are respectively connected to the input end of the logic operation module, and the output end of the logic operation module is connected to the first input end of the driving module; the FB comparison detection module is used for comparing and counting signals output by the isolation optocouplers in the switching power supply and outputting reference valley numbers; the ZCD comparison detection module is used for comparing and counting signals output by the auxiliary winding of the transformer T1 in each switching period of the switching power supply and outputting real-time valley numbers; the logic operation module is used for outputting a valley bottom opening pulse according to the reference valley number and the real-time valley number;
the input end of the peak current monitoring circuit is also respectively connected with a signal output by the isolation optocoupler in the switching power supply and a high-voltage switching tube of the switching power supply.
Specifically, the power supply chip U1 includes a valley lock circuit U2, a peak current monitoring circuit U3, and a driving module U4. The output DRV signal (i.e., valley opening pulse) of the power chip U1 is connected to the gate end of the high-voltage switching tube U5, and drives the high-voltage switching tube U5 to be turned on or off.
For a brief description, the switch chip provided in the embodiment of the present invention may refer to the corresponding content in the foregoing embodiment where the embodiment is not mentioned.
Embodiment III:
Referring to fig. 8, the switching power supply comprises a high-voltage switching tube, a transformer T1, an optocoupler, and the power supply chip.
Specifically, in fig. 8, the Drain terminal of the high-voltage switching transistor U5 is connected to the transformer T1. Since fig. 8 is a flyback switching power supply, the transformer T1 is a flyback transformer, and is characterized in that when the high-voltage switching tube U5 is turned on, the main pole of the transformer T1 forms a loop conduction, and since the secondary homonymous terminal is reversely connected, the D7 schottky diode is reversely turned off, so that the secondary is not conducted. When the high-voltage switching tube U5 is closed, the transformer T1 is disconnected, the secondary is conducted, and the energy stored by the transformer is output by the secondary, and the process is called demagnetizing the transformer. When the energy of the transformer is completely output and demagnetizing is completed, the high-voltage switching tube U5 is still not opened, and the main-stage inductor of the transformer T1 and the Cds parasitic capacitance of the high-voltage switching tube U5 form LC oscillation, as shown in the Drain waveform of fig. 5.
For a brief description, reference may be made to the corresponding contents of the foregoing embodiments of the present invention where the description of the embodiment is not mentioned.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention, and are intended to be included within the scope of the appended claims and description.
Claims (7)
1. A valley locking circuit based on quasi-resonance control technology is characterized in that,
The system comprises an FB comparison detection module, a ZCD comparison detection module and a logic operation module; the output end of the FB comparison detection module and the output end of the ZCD comparison detection module are respectively connected to the input end of the logic operation module, and the output end of the logic operation module is connected to the driving module;
The FB comparison detection module is used for comparing and counting signals output by the isolation optocouplers in the switching power supply and outputting reference valley numbers; the ZCD comparison detection module is used for comparing and counting signals output by the auxiliary winding of the transformer T1 in each switching period of the switching power supply and outputting real-time valley numbers; the logic operation module is used for generating valley bottom opening pulses according to the reference valley number and the real-time valley number, and transmitting the valley bottom opening pulses to the driving module, so that the driving module outputs control signals to be transmitted to a high-voltage switching tube of the switching power supply;
the FB comparison detection module comprises a reference voltage selection unit, a comparator Cmp1, a comparator Cmp2, an exclusive-or gate Xnor and a first counter;
The high voltage output end of the reference voltage selection unit is connected with the positive input end of the comparator Cmp1, the low voltage output end of the reference voltage selection unit is connected with the reverse input end of the comparator Cmp2, and the reverse input end of the comparator Cmp1 and the positive input end of the comparator Cmp2 are both connected to signals output by the isolation optocoupler of the switching power supply; the output end of the comparator Cmp1 is respectively connected to one input end of the exclusive-or gate Xnor and the Add end of the first counter, the output end of the comparator Cmp2 is respectively connected to the other input end of the exclusive-or gate Xnor and the Sub end of the first counter, the output end of the exclusive-or gate Xnor is connected to the enabling end of the first counter, the clock end of the first counter is connected to the clock signal, and the output end of the first counter is connected to the selection end of the reference voltage selection unit;
the output end of the first counter is used as the output end of the FB comparison detection module;
and the logic operation module is used for outputting high level to be transmitted to the driving module when the reference valley number is detected to be equal to the real-time valley number.
2. The valley lock circuit of claim 1, wherein,
The reference voltage selection unit is provided with a plurality of reference voltages, and is used for selecting corresponding reference voltages according to the input signals of the selection ends and outputting the reference voltages from the high voltage output end and the low voltage output end respectively.
3. The valley lock circuit of claim 2, wherein,
The reference voltage output by the high voltage output end in the reference voltage selection unit is larger than the reference voltage output by the low voltage output end.
4. The valley lock circuit of claim 1, wherein,
The ZCD comparison detection module comprises a comparator Cmp3 and a second counter;
The reverse input end of the comparator Cmp3 is connected with a signal output by an auxiliary winding of the transformer T1 in the switching power supply, the forward input end of the comparator Cmp3 is connected with a preset voltage comparison threshold value, and the output end of the comparator Cmp3 is connected with a clock end of the second counter;
the reset end of the second counter is connected to the control signal output by the driving module, and the output end of the second counter is used as the output end of the ZCD comparison detection module.
5. The valley lock circuit of claim 1, wherein,
The logic operation module comprises a first decoder, a second decoder and a logic unit;
The input end of the first decoder is connected with the output end of the FB comparison detection module, the input end of the second decoder is connected with the output end of the ZCD comparison detection module, the first decoder and the second decoder are connected with the output end of the logic unit, and the output end of the logic unit is used as the output end of the logic operation module.
6. A power supply chip comprises a peak current monitoring circuit and a driving module, and is characterized in that,
The device also comprises a valley locking circuit; the output end of the valley locking circuit and the output end of the peak current monitoring circuit are respectively connected to the input end of the driving module, and the output end of the driving module is connected with a high-voltage switching tube of the switching power supply;
The valley bottom locking circuit comprises an FB comparison detection module, a ZCD comparison detection module and a logic operation module; the output end of the FB comparison detection module and the output end of the ZCD comparison detection module are respectively connected to the input end of the logic operation module, and the output end of the logic operation module is connected to the first input end of the driving module; the FB comparison detection module is used for comparing and counting signals output by the isolation optocouplers in the switching power supply and outputting reference valley numbers; the ZCD comparison detection module is used for comparing and counting signals output by the auxiliary winding of the transformer T1 in each switching period of the switching power supply and outputting real-time valley numbers; the logic operation module is used for outputting a valley bottom opening pulse according to the reference valley number and the real-time valley number;
the input end of the peak current monitoring circuit is also respectively connected with a signal output by an isolation optocoupler in the switching power supply and a high-voltage switching tube of the switching power supply;
the FB comparison detection module comprises a reference voltage selection unit, a comparator Cmp1, a comparator Cmp2, an exclusive-or gate Xnor and a first counter;
The high voltage output end of the reference voltage selection unit is connected with the positive input end of the comparator Cmp1, the low voltage output end of the reference voltage selection unit is connected with the reverse input end of the comparator Cmp2, and the reverse input end of the comparator Cmp1 and the positive input end of the comparator Cmp2 are both connected to signals output by the isolation optocoupler of the switching power supply; the output end of the comparator Cmp1 is respectively connected to one input end of the exclusive-or gate Xnor and the Add end of the first counter, the output end of the comparator Cmp2 is respectively connected to the other input end of the exclusive-or gate Xnor and the Sub end of the first counter, the output end of the exclusive-or gate Xnor is connected to the enabling end of the first counter, the clock end of the first counter is connected to the clock signal, and the output end of the first counter is connected to the selection end of the reference voltage selection unit;
the output end of the first counter is used as the output end of the FB comparison detection module;
and the logic operation module is used for outputting high level to be transmitted to the driving module when the reference valley number is detected to be equal to the real-time valley number.
7. A switching power supply comprises a high-voltage switching tube, a transformer T1 and an optocoupler, and is characterized in that,
Further comprising the power chip of claim 6.
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| CN115065253B (en) * | 2022-08-19 | 2022-12-20 | 深圳英集芯科技股份有限公司 | Valley bottom locking control method of flyback switching power supply and related device |
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