CN112331646A - Circuit structure for reducing capacitance, electrostatic protection circuit, and electronic apparatus - Google Patents
Circuit structure for reducing capacitance, electrostatic protection circuit, and electronic apparatus Download PDFInfo
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
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Abstract
A circuit structure for reducing capacitance, an electrostatic protection circuit, and an electronic apparatus. The circuit structure includes: a substrate; a first signal transmission carrier including a first body extending in a first direction and at least one first transmission sub-carrier configured to transmit a first signal; a second signal transmission carrier including a second body extending in a second direction and at least one second transmission sub-carrier configured to transmit a second signal; the first edge of the first transmission subcarrier comprises a first intersection point intersected with the first main body, the second edge of the second transmission subcarrier comprises a second intersection point intersected with the second main body, the distance between the first intersection point and the second intersection point in the third direction is a first distance, the third direction is perpendicular to the extending direction of the first transmission subcarrier or the second transmission subcarrier, the minimum distance between the first edge and the second edge is a second distance, and the first distance is smaller than the second distance. The circuit structure can reduce the parasitic capacitance at the staggered opposite positions of the signal lines.
Description
Technical Field
Embodiments of the present disclosure relate to a circuit structure for reducing capacitance, an electrostatic protection circuit, and an electronic apparatus.
Background
The parasitic capacitance means that a capacitor is not designed at that place, but because mutual capacitance always exists between wirings, the mutual capacitance is as if the capacitor is parasitic between the wirings, so the parasitic capacitance is called as stray capacitance.
Disclosure of Invention
At least one embodiment of the present disclosure provides a circuit structure for reducing capacitance, including: the signal transmission device comprises a substrate, a first signal transmission carrier, a second signal transmission carrier and a signal transmission module, wherein the first signal transmission carrier is positioned on the substrate and comprises a first main body extending along a first direction and at least one first transmission sub-carrier extending from the first main body and configured to transmit a first signal; a second signal transmission carrier on the substrate, including a second body extending along the second direction and at least one second transmission sub-carrier extending from the second body, configured to transmit a second signal, the at least one first transmission sub-carrier being located at a side of the first body close to the second body, the at least one second transmission sub-carrier being located at a side of the second body close to the first body, the at least one second transmission sub-carrier and the at least one first transmission sub-carrier being insulated and interleaved with each other; the at least one first transmission subcarrier and the at least one second transmission subcarrier are opposite to form at least part of the capacitor; at the opposite place, a projection of the first transport sub-carrier on the surface of the substrate includes a first edge close to the second transport sub-carrier, a projection of the second transport sub-carrier on the surface of the substrate includes a second edge close to the first transport sub-carrier, the first edge of the first transport sub-carrier includes a first intersection intersecting the first body, the second edge of the second transport sub-carrier includes a second intersection intersecting the second body, a distance between the first intersection and the second intersection in a third direction is a first distance, the third direction is perpendicular to an extending direction of the first transport sub-carrier or the second transport sub-carrier, a minimum distance between the first edge and the second edge is a second distance, and the first distance is smaller than the second distance.
For example, in a circuit structure provided in at least one embodiment of the present disclosure, the first direction and the second direction are parallel or cross.
For example, at least one embodiment of the present disclosure provides a circuit structure in which the first side and the second side are substantially parallel.
For example, in a circuit structure provided by at least one embodiment of the present disclosure, the at least one first transport sub-carrier includes a plurality of side-by-side first transport sub-carriers, the at least one second transport sub-carrier includes a plurality of side-by-side second transport sub-carriers, and a planar shape of a first transport sub-carrier located on two sides among the plurality of side-by-side first transport sub-carriers is substantially a single-sided trapezoid; the planar shape of the second transmission sub-carriers positioned at two sides in the plurality of side-by-side second transmission sub-carriers is approximately a single-side trapezoid; the planar shape of the rest first transmission sub-carriers except the first transmission sub-carriers positioned at two sides in the plurality of side-by-side first transmission sub-carriers is approximately a double-sided trapezoid; the planar shape of the rest of the plurality of second transmission sub-carriers, except the second transmission sub-carriers positioned at two sides, is approximately a double-sided trapezoid.
For example, in a circuit arrangement provided in at least one embodiment of the present disclosure, the first signal transmission carrier is configured to be coupled to a first signal source to receive the first signal, and the second signal transmission carrier is configured to be coupled to a second signal source to receive the second signal.
For example, the circuit structure provided by at least one embodiment of the present disclosure further includes a third signal transmission carrier, located on the substrate and on a side of the first signal transmission carrier away from the second signal transmission carrier, including a third main body extending along a fourth direction and at least one third transmission sub-carrier extending from the third main body, configured to transmit a third signal; the first signal transmission carrier further comprises at least one fourth transmission sub-carrier extending from the first main body and positioned on one side of the first main body close to the third main body; the at least one third transmission sub-carrier is positioned on one side of the third main body close to the first main body, and the at least one third transmission sub-carrier and the at least one fourth transmission sub-carrier are insulated and staggered with each other; the at least one third transmission sub-carrier and the at least one fourth transmission sub-carrier are opposite to each other for forming at least part of the capacitance; at the opposite place, a projection of the third transport sub-carrier on the surface of the substrate includes a third side close to the fourth transport sub-carrier, a projection of the fourth transport sub-carrier on the surface of the substrate includes a fourth side close to the third transport sub-carrier, the third side of the third transport sub-carrier includes a third intersection intersecting with the third body, the fourth side of the fourth transport sub-carrier includes a fourth intersection intersecting with the first body, a distance between the third intersection and the fourth intersection in a fifth direction is a third distance, the fifth direction is perpendicular to an extending direction of the third transport sub-carrier or the fourth transport sub-carrier, a minimum distance between the third side and the fourth side is a fourth distance, and the third distance is smaller than the fourth distance.
For example, in a circuit structure provided in at least one embodiment of the present disclosure, the four directions are parallel to or cross the first direction or the second direction.
For example, in a circuit arrangement provided in at least one embodiment of the present disclosure, the third signal transmission carrier is configured to be coupled to the third signal source to receive the third signal.
For example, in the circuit structure provided by at least one embodiment of the present disclosure, the at least one third transport sub-carrier includes a plurality of side-by-side third transport sub-carriers, the at least one fourth transport sub-carrier includes a plurality of side-by-side fourth transport sub-carriers, and a planar shape of third transport sub-carriers located on two sides among the plurality of side-by-side third transport sub-carriers is substantially a single-sided trapezoid; the planar shape of the fourth transmission sub-carriers positioned at two sides in the plurality of side-by-side fourth transmission sub-carriers is approximately a single-side trapezoid; the planar shapes of the rest of the plurality of third transmission sub-carriers side by side except the third transmission sub-carriers positioned at the two sides are approximately double-sided trapezoids, and the planar shapes of the rest of the plurality of fourth transmission sub-carriers side by side except the fourth transmission sub-carriers positioned at the two sides are approximately double-sided trapezoids.
At least one embodiment of the present disclosure further provides a circuit structure for reducing capacitance, including: a substrate; a first signal transmission carrier on the substrate, including a first body extending in a first direction and at least one first transmission sub-carrier extending from the first body, configured to transmit a first signal; a second signal transmission carrier on the substrate, including a second body extending along the second direction and at least one second transmission sub-carrier extending from the second body, configured to transmit a second signal; the at least one first transmission sub-carrier is positioned at one side of the first body close to the second body, the at least one second transmission sub-carrier is positioned at one side of the second body close to the first body, and the at least one second transmission sub-carrier and the at least one first transmission sub-carrier are insulated and staggered with each other; the at least one first transmission subcarrier and the at least one second transmission subcarrier are opposite to form at least part of the capacitor; the opposite position is that the projection of the first transmission subcarrier on the surface of the substrate comprises a first edge close to the second transmission subcarrier, the projection of the second transmission subcarrier on the surface of the substrate comprises a second edge close to the first transmission subcarrier, a first included angle is formed between a straight line of the first edge along the extending direction of the first edge and a straight line of the first main body along the first direction, a second included angle is formed between a straight line of the second edge along the extending direction of the second edge and a straight line of the second main body along the second direction, the first included angle and the second included angle are arranged oppositely, and at least one of the first included angle and the second included angle is an obtuse angle.
For example, the circuit structure provided by at least one embodiment of the present disclosure further includes a third signal transmission carrier, located on the substrate and on a side of the first signal transmission carrier away from the second signal transmission carrier, including a third main body extending along a fourth direction and at least one third transmission sub-carrier extending from the third main body, configured to transmit a third signal; the first signal transmission carrier further comprises at least one fourth transmission sub-carrier which is positioned on one side of the first main body close to the third main body; the at least one third transmission sub-carrier is positioned on one side of the third main body close to the first main body, and the at least one third transmission sub-carrier and the at least one fourth transmission sub-carrier are insulated and staggered with each other; the at least one third transmission sub-carrier and the at least one fourth transmission sub-carrier are opposite to each other for forming at least part of the capacitance; the opposite position, the projection of third transmission subcarrier is in on the surface of substrate includes being close to the third edge of fourth transmission subcarrier, the projection of fourth transmission subcarrier is in on the surface of substrate includes being close to the fourth side of third transmission subcarrier, the third edge of third transmission subcarrier is followed the sharp at third edge's extending direction place with the third main part is followed be the third contained angle between the sharp at third direction place, the fourth edge of fourth transmission subcarrier is followed the extending direction of fourth edge the sharp with the first main part is followed be the fourth contained angle between the sharp at first direction place, the third contained angle with the fourth contained angle sets up relatively, at least one of third contained angle and fourth contained angle is the obtuse angle.
At least one embodiment of the present disclosure further provides an electrostatic protection circuit including the circuit structure for reducing capacitance provided in any one embodiment of the present disclosure.
For example, an electrostatic protection circuit provided in at least one embodiment of the present disclosure further includes an input terminal, a first electrostatic sub-circuit, and a second electrostatic sub-circuit; the input end is connected with the first signal transmission carrier to transmit the first signal, the first electrostatic sub-circuit is connected with the first signal transmission carrier and the second signal transmission carrier, and the second electrostatic sub-circuit is connected with the first signal transmission carrier and the third signal transmission carrier.
For example, in an electrostatic protection circuit provided in at least one embodiment of the present disclosure, the input terminal is connected to a high-speed input/output interface to receive the first signal.
For example, in an electrostatic protection circuit provided in at least one embodiment of the present disclosure, the first electrostatic sub-circuit includes a first diode, a first pole of the first diode is connected to the first transport sub-carrier, and a second pole of the first diode is connected to the second transport sub-carrier.
For example, in an electrostatic protection circuit provided in at least one embodiment of the present disclosure, the circuit structure further includes a third signal transmission carrier, located on a side of the first signal transmission carrier away from the second signal transmission carrier, including a third main body extending along a third direction and at least one third transmission sub-carrier extending from the third main body, configured to transmit a third signal; the first signal transmission carrier further comprises at least one fourth transmission sub-carrier which is positioned on one side of the first main body close to the third main body; the at least one third transmission subcarrier is located on one side of the third main body close to the first main body, the second electrostatic subcircuit comprises a second diode, a first pole of the second diode is connected with the fourth transmission subcarrier, and a second pole of the second diode is connected with the third transmission subcarrier.
For example, in an electrostatic protection circuit provided in at least one embodiment of the present disclosure, the first electrostatic sub-circuit and the second electrostatic sub-circuit are implemented as transistors.
At least one embodiment of the present disclosure further provides an electronic device including the electrostatic protection circuit provided in any one of the embodiments of the present disclosure.
Drawings
To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure and are not limiting to the present disclosure.
FIG. 1 is a schematic plan view of a circuit configuration;
fig. 2 is a schematic plan view of a circuit structure according to at least one embodiment of the present disclosure;
fig. 3 is a schematic plan view of another circuit structure provided in at least one embodiment of the present disclosure;
fig. 4 is a schematic plan view of a circuit structure according to at least one embodiment of the present disclosure;
fig. 5 is a schematic diagram of an esd protection circuit according to at least one embodiment of the present disclosure;
fig. 6 is a schematic circuit structure diagram of an electrostatic protection circuit according to at least one embodiment of the present disclosure;
fig. 7 is a schematic plan view of an electrostatic protection circuit according to at least one embodiment of the present disclosure; and
fig. 8 is a schematic block diagram of an electronic device according to at least one embodiment of the present disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.
Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
ESD (Electro-Static discharge) technology refers to a technology for protecting devices inside a chip by discharging Static charges inside or outside the chip through some specific devices inside the chip. The Input/Output (I/O) interface refers to a high-speed transmission port, and is an interface for data transmission interaction between a chip and the outside, and the speed and the signal transmission quality of the interface greatly affect the quality of the chip. Signals on the high-speed I/O interface are generally transmitted to an internal circuit of the chip through the electrostatic protection circuit, and parasitic capacitance is generated at the staggered position because signal lines connected with the electrostatic protection circuit and signal lines connected with the high-speed I/O interface can be staggered. For example, as shown in fig. 1, in the conventional layout scheme, the projection shape of each signal line on the substrate is rectangular, the signal line a and the signal line B are laid out in parallel with a certain distance d kept therebetween, and a parasitic capacitance Cp exists. The larger the parasitic capacitance Cp is, the larger the influence on the signal transmission speed and transmission quality on the high-speed I/O interface is, and further, the great influence is exerted on the performance of the chip.
At least one embodiment of the present disclosure provides a circuit structure for reducing capacitance, including: a substrate; a first signal transmission carrier on the substrate, including a first body extending in a first direction and at least one first transmission sub-carrier extending from the first body, configured to transmit a first signal; a second signal transmission carrier located on the substrate, including a second body extending along a second direction and at least one second transmission sub-carrier extending from the second body and configured to transmit a second signal, the at least one first transmission sub-carrier being located at a side of the first body close to the second body, the at least one second transmission sub-carrier being located at a side of the second body close to the first body, the at least one second transmission sub-carrier and the at least one first transmission sub-carrier being insulated and interleaved with each other; at least one first transmission subcarrier and at least one second transmission subcarrier are opposite to form at least part of a capacitor; in the opposite place, the projection of the first transport sub-carrier on the surface of the substrate includes a first edge near the second transport sub-carrier, the projection of the second transport sub-carrier on the surface of the substrate includes a second edge near the first transport sub-carrier, the first edge of the first transport sub-carrier includes a first intersection intersecting the first body, the second edge of the second transport sub-carrier includes a second intersection intersecting the second body, a distance between the first intersection and the second intersection in a third direction is a first distance, the third direction is perpendicular to the extending direction of the first transport sub-carrier or the second transport sub-carrier, a minimum distance between the first edge and the second edge is a second distance, and the first distance is smaller than the second distance.
Some embodiments of the present disclosure also provide an electrostatic protection circuit and an electronic device corresponding to the above circuit structure.
According to the circuit structure for reducing the capacitance, the electrostatic protection circuit and the electronic device, which are provided by at least one embodiment of the disclosure, the characteristics of the parasitic capacitance can be improved, and the parasitic capacitance at the staggered opposite position of the signal line can be reduced, so that the influence of the parasitic capacitance on the signal transmission speed and the transmission quality of the signal line can be reduced, and the influence on the performance of a chip can be reduced.
Embodiments of the present disclosure and examples thereof are described in detail below with reference to the accompanying drawings.
At least one embodiment of the present disclosure provides a circuit structure for reducing capacitance, which may be used, for example, to reduce parasitic capacitance between signal lines in the circuit structure. For example, the circuit structure may be applied to an electrostatic protection circuit of an integrated circuit to avoid a large parasitic capacitance generated between a signal line connected to the electrostatic protection circuit and a signal line connected to a high-speed I/O interface, so as to avoid an influence on a signal transmission speed and a transmission quality on the high-speed I/O interface. Of course, the circuit structure may also be applied to other types of circuits, and the embodiment of the present disclosure is not limited thereto.
Fig. 2 is a schematic plan view of a circuit structure according to at least one embodiment of the present disclosure. As shown in fig. 2, the circuit structure 100 includes a substrate 10, a first signal-transmission carrier, and a second signal-transmission carrier. For example, the first signal transmission carrier and the second signal transmission carrier may be signal lines or carriers such as metal blocks for transmitting signals, which is not limited by the embodiments of the present disclosure.
For example, as shown in fig. 2, a first signal transmission carrier is located on the substrate 10, and includes a first body 11 extending in a first direction and at least one first transmission sub-carrier a extending from the first body 11 and configured to transmit a first signal; the second signal transmission carrier is located on the substrate, and includes a second body 12 extending in a second direction and at least one second transmission sub-carrier B extending from the second body 12 and configured to transmit a second signal. For example, the first direction and the second direction are parallel or cross. For example, in the circuit structure shown in fig. 2, the first direction and the second direction are parallel, for example, X direction, and the embodiment of the present disclosure is not limited thereto.
For example, the first signal and the second signal are different. For example, a first signal transport carrier is configured to couple to a first signal source (not shown) to receive a first signal, and a second signal transport carrier is configured to couple to a second signal source (not shown) to receive a second signal. For example, when the circuit structure is applied to an electrostatic protection circuit, the first signal source is an I/O interface, and the second signal source is a high-level voltage source, which is not limited in this embodiment of the disclosure.
For example, as shown in fig. 2, at least one first transport sub-carrier a is located at a side of the first body 11 close to the second body 12, and at least one second transport sub-carrier B is located at a side of the second body 12 close to the first body 11, that is, at least one first transport sub-carrier a and at least one second transport sub-carrier B are located between the first body 11 and the second body 12. For example, the at least one second transmission sub-carrier B and the at least one first transmission sub-carrier a are insulated and interleaved with each other; at least one first transmission sub-carrier a and at least one second transmission sub-carrier B are opposed to each other for forming at least a part of the capacitance Cp.
For example, in the opposite, the projection of the first transporting sub-carrier a on the surface of the substrate 10 includes a first side L1 near the second transporting sub-carrier B, the projection of the second transporting sub-carrier B on the surface of the substrate 10 includes a second side L2 near the first transporting sub-carrier a, the first side L1 of the first transporting sub-carrier a includes a first intersection point a intersecting the first body 11, the second side L2 of the second transporting sub-carrier B includes a second intersection point B intersecting the second body 12, the distance between the first intersection point a and the second intersection point B in the third direction is a first distance d1, and the third direction is perpendicular to the extending direction of the first transporting sub-carrier a or the second transporting sub-carrier B. For example, the extending direction of the first transport sub-carrier a or the second transport sub-carrier B shown in fig. 2 is a Y direction, and correspondingly, the third direction is an X direction, but the embodiment of the present disclosure is not limited thereto. For example, the extending direction of the first transporting sub-carrier a or the second transporting sub-carrier B may be any direction, for example, a direction inclined with respect to the Y direction, etc., and accordingly, the third direction is also changed as the extending direction of the first transporting sub-carrier a or the second transporting sub-carrier B is changed.
For example, the minimum distance between the first side L1 and the second side L2 is the second distance d2, and the first distance d1 is less than the second distance d 2. For example, the first distance d1 is the distance d in the conventional scheme shown in fig. 1. In the embodiment of the present disclosure, by setting the first distance d1 to be smaller than the second distance d2, the magnitude of the parasitic capacitance Cp between the first transmission sub-carrier a and the second transmission sub-carrier B can be reduced, thereby reducing the influence of the parasitic capacitance on the signals transmitted on the first transmission carrier and the second transmission carrier.
For example, the parasitic capacitance Cp is calculated as:
Cp＝εS/(4πkd)，
wherein epsilon is the dielectric constant of the medium between the polar plates, S is the opposite area of the capacitor polar plate, d is the distance of the capacitor polar plate, and k is the constant of the electrostatic force.
Based on the above formula, it can be seen that since the distance d of the capacitor plates is applied to the whole plate, the magnitude of the distance d plays a decisive role in the parasitic capacitance. Therefore, if the first interval d1< the second interval d2, then the parasitic capacitance Cp1> Cp 2.
For example, the width of the first transport sub-carrier a in the first direction is gradually reduced in a direction away from the first body 11 and close to the second body 12, and the width of the second transport sub-carrier B in the first direction is gradually reduced in a direction away from the second body 12 and close to the first body 11, that is, the first transport sub-carrier a or the second transport sub-carrier B is gradually tapered in a direction extending, so that the distance between the first transport sub-carrier a and the second transport sub-carrier B may be increased, that is, the second distance d2 may be reached.
For example, as shown in fig. 2, the at least one first transport sub-carrier a includes a plurality of side-by-side first transport sub-carriers a, and the at least one second transport sub-carrier B includes a plurality of side-by-side second transport sub-carriers B.
For example, the planar shape of the first transporting sub-carriers a located on both sides among the plurality of first transporting sub-carriers a side by side is substantially a one-sided trapezoid; the planar shape of the second transmission sub-carriers B positioned at two sides among the plurality of second transmission sub-carriers B arranged side by side is approximately a single-side trapezoid; the plane shapes of the rest first transmission sub-carriers B except the first transmission sub-carriers A positioned at two sides in the plurality of first transmission sub-carriers A which are arranged side by side are approximately double-sided trapezoids; the planar shape of the remaining second transport sub-carriers except the second transport sub-carriers B located at both sides among the plurality of side-by-side second transport sub-carriers B is substantially a double-sided trapezoid.
For example, the first transmission sub-carrier or the second transmission sub-carrier is tapered along the extending direction, that is, the top end is wider, and the end is narrower, so that not only can the magnitude of the parasitic capacitance between the first transmission sub-carrier and the second transmission sub-carrier be reduced, but also the requirement of signal transmission on resistance can be met, and because there are fewer elements connected in series at the end, the requirement on resistance is not high, and therefore the width can be narrower than the top end.
For example, the first side L1 and the second side L2 are inclined with respect to the extending direction of the first transporting sub-carrier a and the second transporting sub-carrier B, respectively, and the first side L1 and the second side L2 may be straight lines, zigzag as shown in fig. 4, arc, etc., as long as the straight lines along the extending direction of the first side L1 and the second side L2 are inclined with respect to the extending direction of the first transporting sub-carrier a and the second transporting sub-carrier B to increase the distance between the first transporting sub-carrier a and the second transporting sub-carrier B, which is not limited by the embodiment of the present disclosure. The following examples are the same and will not be described in detail.
Fig. 3 is a schematic plan view of another circuit structure provided in at least one embodiment of the present disclosure. For example, as shown in fig. 3, the circuit structure further includes a third signal transmission carrier on the substrate 10 and on a side of the first signal transmission carrier away from the second signal transmission carrier, and a third main body 13 extending along a fourth direction (e.g., X direction) and at least one third transmission sub-carrier C extending from the third main body 13 and configured to transmit a third signal. For example, the third signal is different from the first signal, and may be the same as or different from the second signal, which may be determined according to the actual situation, and the embodiment of the present disclosure is not limited thereto. For example, the third signal transport carrier is configured to be coupled to a third signal source (not shown) to receive a third signal. For example, when the circuit structure is applied to an electrostatic protection circuit, the third signal source may be a low-level voltage source, which is not limited by the embodiment of the disclosure.
For example, the fourth direction is parallel to or intersects with the first direction or the second direction. For example, in the circuit structure shown in fig. 3, the fourth direction is parallel to the first direction and the second direction, for example, the X direction, and the embodiment of the disclosure is not limited thereto.
For example, the first signal transmission carrier further includes at least one fourth transmission sub-carrier D extending from the first body 11. For example, at least one fourth transport sub-carrier D is located at a side of the first body 11 close to the third body 13, and at least one third transport sub-carrier C is located at a side of the third body 13 close to the first body 11, that is, at least one third transport sub-carrier C and at least one fourth transport sub-carrier D are located between the first body 11 and the third body 13. For example, at least one third transmission sub-carrier C and at least one fourth transmission sub-carrier D are insulated and interleaved with each other; at least one third transmission sub-carrier C and at least one fourth transmission sub-carrier D are opposed to form at least part of the capacitance Cp.
For example, in the opposite, the projection of the third transporting sub-carrier C on the surface of the substrate 10 includes a third side L3 adjacent to the fourth transporting sub-carrier C, the projection of the fourth transporting sub-carrier D on the surface of the substrate 10 includes a fourth side L4 adjacent to the third transporting sub-carrier C, the third side L3 of the third transporting sub-carrier C includes a third intersection C intersecting the third body 13, the fourth side L4 of the fourth transporting sub-carrier D includes a fourth intersection D intersecting the first body 11, a distance between the third intersection C and the fourth intersection D in the fifth direction is a third distance D3, and the fifth direction is perpendicular to the extending direction of the third transporting sub-carrier C or the fourth transporting sub-carrier D. For example, the extending direction of the third transport sub-carrier C or the fourth transport sub-carrier D shown in fig. 3 is a Y direction, and correspondingly, the fifth direction is an X direction, but the embodiment of the present disclosure is not limited thereto. For example, the extending direction of the third transporting sub-carrier C or the fourth transporting sub-carrier D may be any direction, for example, a direction inclined with respect to the Y direction, etc., and accordingly, the fifth direction is also changed as the extending direction of the third transporting sub-carrier C or the fourth transporting sub-carrier D is changed.
For example, the minimum distance between the third side L3 and the fourth side L4 is a fourth distance d4, and the third distance d3 is less than the fourth distance d 4. For example, the third distance d3 is the distance d in the conventional scheme shown in fig. 1. In the embodiment of the present disclosure, by setting the third distance D3 to be smaller than the fourth distance D4, the magnitude of the parasitic capacitance Cp between the third transmission sub-carrier C and the fourth transmission sub-carrier D can be reduced, thereby reducing the influence of the parasitic capacitance on the signals transmitted on the third transmission sub-carrier C and the fourth transmission sub-carrier D.
For example, the width of the third transporting sub-carrier C in the fourth direction is gradually reduced in a direction away from the third body 13 and close to the first body 11 (i.e., the Y direction), and the width of the fourth transporting sub-carrier D in the first direction is gradually reduced in a direction away from the first body 11 and close to the third body 13, i.e., the third transporting sub-carrier C or the fourth transporting sub-carrier D is gradually tapered in a direction extending, so that the distance between the third transporting sub-carrier C and the fourth transporting sub-carrier D can be increased, i.e., up to the fourth distance D4.
For example, as shown in fig. 3, the at least one third transport sub-carrier C includes a plurality of side-by-side third transport sub-carriers C, the at least one fourth transport sub-carrier D includes a plurality of side-by-side fourth transport sub-carriers D, and the planar shape of the third transport sub-carriers C located at both sides among the plurality of side-by-side third transport sub-carriers C is substantially a one-sided trapezoid; the planar shape of the fourth transmission sub-carriers D positioned at both sides among the plurality of side-by-side fourth transmission sub-carriers D is substantially a single-sided trapezoid; the planar shapes of the third transporting sub-carriers C except the third transporting sub-carriers C located on both sides among the plurality of third transporting sub-carriers C arranged side by side are substantially double-sided trapezoids, and the planar shapes of the remaining fourth transporting sub-carriers D except the fourth transporting sub-carriers D located on both sides among the plurality of fourth transporting sub-carriers D arranged side by side are substantially double-sided trapezoids.
For example, the third transmission sub-carrier C or the fourth transmission sub-carrier D is tapered in the extending direction, that is, the top end is wider and the end is narrower, so that not only can the parasitic capacitance between the third transmission sub-carrier C and the fourth transmission sub-carrier D be reduced, but also the requirement of signal transmission on resistance can be met, and the requirement of signal transmission on resistance can be made narrower than the top because of less elements connected in series at the end and less requirement on resistance.
For example, the third side L3 and the fourth side L4 are inclined with respect to the extending direction of the third transporting sub-carrier C and the fourth transporting sub-carrier D, respectively, and the third side L3 and the fourth side L4 may be straight lines, zigzag as shown in fig. 4, arc, etc., as long as the straight lines along the extending direction of the third side L3 and the fourth side L4 are inclined with respect to the extending direction of the third transporting sub-carrier C and the fourth transporting sub-carrier D to increase the distance between the first transporting sub-carrier C and the second transporting sub-carrier D, which is not limited by the embodiment of the present disclosure. The following examples are the same and will not be described in detail.
For example, at least one embodiment of the present disclosure further provides a circuit structure for reducing capacitance, including: including a substrate 10, a first signal transmission carrier and a second signal transmission carrier.
For example, as shown in fig. 3, a first signal transmission carrier is located on the substrate 10, and includes a first body 11 extending in a first direction and at least one first transmission sub-carrier a extending from the first body 11 and configured to transmit a first signal; the second signal transmission carrier is located on the substrate, and includes a second body 12 extending in a second direction and at least one second transmission sub-carrier B extending from the second body 12 and configured to transmit a second signal. For example, the first direction and the second direction are parallel or cross. For example, in the circuit structure shown in fig. 2, the first direction and the second direction are parallel, for example, X direction, and the embodiment of the present disclosure is not limited thereto.
For example, as shown in fig. 3, at least one first transport sub-carrier a is located at a side of the first body 11 close to the second body 12, and at least one second transport sub-carrier B is located at a side of the second body 12 close to the first body 11, that is, at least one first transport sub-carrier a and at least one second transport sub-carrier B are located between the first body 11 and the second body 12. For example, the at least one second transmission sub-carrier B and the at least one first transmission sub-carrier a are insulated and interleaved with each other; at least one first transmission sub-carrier a and at least one second transmission sub-carrier B are opposed to each other for forming at least a part of the capacitance Cp.
For example, in the opposite, the projection of the first transport sub-carrier a on the surface of the substrate 10 includes a first side L1 near the second transport sub-carrier B, and the projection of the second transport sub-carrier B on the surface of the substrate 10 includes a second side L2 near the first transport sub-carrier a.
For example, a first included angle t1 is formed between a straight line of the first edge L1 of the first transporting sub-carrier a along the extending direction of the first edge L1 and a straight line L11 of the first main body 11 along the first direction, namely, an included angle between the outer side of the first transporting sub-carrier a and the first main body 11; for example, a second included angle t2 is formed between a straight line of the second side L2 of the second transmission sub-carrier B along the extending direction of the second side L2 and a straight line L12 of the second main body 12 along the second direction, that is, an included angle between the outer side of the second transmission sub-carrier B and the second main body 12, that is, the first included angle t1 is opposite to the second included angle t 2. For example, at least one of the first and second included angles t1 and t2 is an obtuse angle, so that the distance between the first and second transport sub-carriers a and B can be increased.
For example, as shown in fig. 3, the circuit structure further includes a third signal transmission carrier, located on the substrate 10 and located on a side of the first signal transmission carrier away from the second signal transmission carrier, including a third body 13 extending along a fourth direction and at least one third transmission sub-carrier C extending from the third body 13, configured to transmit a third signal; the first signal transmission carrier further comprises at least one fourth transmission subcarrier D located on one side of the first body 11 close to the third body 13; at least one third transmission sub-carrier C is positioned on one side of the third body 13 close to the first body 11, and the at least one third transmission sub-carrier C and the at least one fourth transmission sub-carrier D are insulated and staggered with each other; at least one third transmission sub-carrier C and the at least one fourth transmission sub-carrier D are opposite for forming at least part of a capacitance.
For example, as shown in fig. 3, in the opposite, the projection of the third transporting sub-carrier C on the surface of the substrate 10 includes a third side L3 close to the fourth transporting sub-carrier D, and the projection of the fourth transporting sub-carrier D on the surface of the substrate 10 includes a fourth side L4 close to the third transporting sub-carrier C.
For example, a third included angle t3 is formed between a straight line of the third side L3 of the third transporting sub-carrier C along the extending direction of the third side L3 and a straight line of the third main body 13 along the third direction, that is, an included angle between the outer side of the third transporting sub-carrier C and the third main body 13; for example, a fourth included angle t4 is formed between a straight line of the fourth side L4 of the fourth transporting sub-carrier D along the extending direction of the fourth side L4 and a straight line of the first main body 11 along the first direction, that is, an included angle between the outer side of the fourth transporting sub-carrier D and the first main body 11, that is, the third included angle t3 and the fourth included angle t4 are oppositely arranged. For example, at least one of the third and fourth angles t3 and t4 is an obtuse angle, so that the distance between the third and fourth transporting sub-carriers C and D may be increased.
The circuit structure for reducing the capacitance provided by each of the above embodiments of the present disclosure can improve the characteristics of the parasitic capacitance, and reduce the parasitic capacitance at the staggered and opposite positions of the signal lines, thereby reducing the influence of the parasitic capacitance on the signal transmission speed and transmission quality on the signal lines, and further reducing the influence on the performance of the chip.
At least one embodiment of the present disclosure further provides an electrostatic protection circuit. Fig. 5 is a schematic diagram of an electrostatic protection circuit according to at least one embodiment of the present disclosure. Fig. 6 is a schematic circuit structure diagram of an electrostatic protection circuit according to at least one embodiment of the present disclosure. Fig. 7 is a schematic plan view of an electrostatic protection circuit according to at least one embodiment of the present disclosure. As shown in fig. 5, the esd protection circuit 200 includes the circuit structure 100 for reducing capacitance according to any embodiment of the present disclosure.
For example, as shown in fig. 6, the electrostatic protection circuit further includes an input terminal (e.g., the input terminal is connected to the high-speed input/output interface to receive the first signal), a first electrostatic sub-circuit 201, and a second electrostatic sub-circuit 202. For example, the input terminal I/O is connected to a first signal transmission carrier (e.g., a signal line connected to an I/O interface) to transmit a first signal, the first electrostatic sub-circuit 201 is connected to the first signal transmission carrier and a second signal transmission carrier (e.g., a signal line connected to a first voltage terminal VDD (high level voltage source)) to receive a second signal, and the second electrostatic sub-circuit 202 is connected to the first signal transmission carrier and a third signal transmission carrier (e.g., a signal line connected to a second voltage terminal VSS (low level voltage source)) to receive a third signal.
For example, as shown in fig. 6 and 7, the first electrostatic sub-circuit 201 includes a first diode LED1, a first pole of the first diode LED1 is connected to the first transport sub-carrier a, and a second pole of the first diode LED1 is connected to the second transport sub-carrier B.
For example, as shown in fig. 6 and 7, the second electrostatic sub-circuit 202 includes a second diode LED2, a first pole of the second diode LED2 is connected to the fourth transport sub-carrier D, and a second pole of the second diode LED2 is connected to the third transport sub-carrier C.
For example, the first electrostatic sub-circuit 201 and the second electrostatic sub-circuit 202 may also be implemented as transistors, which is not limited by the embodiments of the present disclosure. For example, the transistors may be thin film transistors or field effect transistors or other switching devices with the same characteristics, and the thin film transistors are described herein as examples, for example, the active layer (channel region) of the transistor is made of a semiconductor material, such as polysilicon (e.g., low temperature polysilicon or high temperature polysilicon), amorphous silicon, indium gallium tin oxide (IGZO), and the like, and the gate, the source, and the drain are made of a metal material, such as aluminum or an aluminum alloy.
For example, the electrostatic protection circuit 200 is connected to the chip internal circuit 300, so that on-chip (internal circuit) or off-chip static charges (static charges carried in signals transmitted from the high-speed I/O port to the internal circuit 300) can be discharged to protect the chip internal device (e.g., the internal circuit 300). The main technical effects are that the parasitic capacitance parameter of the port end of the high-speed I/O port is reduced, and the quality and the speed of the I/O signal are improved.
For a detailed description of the electrostatic protection circuit, reference may be made to the description of the circuit structure described above, and details are not repeated here. Regarding the technical effects of the electrostatic protection circuit provided in the above embodiments, reference may be made to the technical effects of the circuit structure provided in the embodiments of the present disclosure, which are not described herein again.
At least one embodiment of the present disclosure further provides an electronic device including the electrostatic protection circuit provided in any one of the embodiments of the present disclosure. Fig. 8 is a schematic view of an electronic device according to at least one embodiment of the present disclosure. As shown in fig. 8, the electronic apparatus 1000 includes, for example, the electrostatic protection circuit 200 shown in fig. 6.
For example, the electronic device may be any device such as a mobile phone, a tablet computer, a notebook computer, an electronic book, a game machine, a television, a digital photo frame, and a navigator, and may also be any combination of electronic devices and hardware, which is not limited in this respect in the embodiments of the disclosure.
It should be noted that in the embodiments of the present disclosure, the electronic device may include more or less circuits or units, and the connection relationship between the respective circuits or units is not limited and may be determined according to actual needs. The specific configuration of each circuit is not limited, and may be configured by an analog device, a digital chip, or other suitable configurations according to the circuit principle.
Regarding the technical effects of the electronic device provided by the above embodiments, reference may be made to the technical effects of the circuit structure provided in the embodiments of the present disclosure, and details are not described here.
The following points need to be explained:
(1) the drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to the common design.
(2) Without conflict, embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments.
The above description is intended to be exemplary of the present disclosure, and not to limit the scope of the present disclosure, which is defined by the claims appended hereto.
Claims (18)
1. A circuit structure for reducing capacitance, comprising:
a substrate;
a first signal transmission carrier on the substrate, including a first body extending in a first direction and at least one first transmission sub-carrier extending from the first body, configured to transmit a first signal;
a second signal transmission carrier on the substrate, including a second body extending in the second direction and at least one second transmission sub-carrier extending from the second body, configured to transmit a second signal,
wherein the at least one first transmission sub-carrier is located at a side of the first body close to the second body, and the at least one second transmission sub-carrier is located at a side of the second body close to the first body,
the at least one second transmission sub-carrier and the at least one first transmission sub-carrier are insulated and staggered from each other;
the at least one first transmission subcarrier and the at least one second transmission subcarrier are opposite to form at least part of the capacitor;
at the opposite, a projection of the first transport sub-carrier on the surface of the substrate includes a first edge near the second transport sub-carrier, a projection of the second transport sub-carrier on the surface of the substrate includes a second edge near the first transport sub-carrier,
the first edge of the first transport sub-carrier includes a first intersection point intersecting the first body, the second edge of the second transport sub-carrier includes a second intersection point intersecting the second body,
the distance between the first intersection point and the second intersection point in a third direction is a first distance, the third direction is perpendicular to the extending direction of the first transmission sub-carrier or the second transmission sub-carrier, the minimum distance between the first edge and the second edge is a second distance,
the first distance is less than the second distance.
2. The circuit structure of claim 1, wherein the first direction and the second direction are parallel or cross.
3. The circuit structure of claim 1 or 2, wherein the first side and the second side are substantially parallel.
4. Circuit arrangement according to claim 1 or 2, wherein the at least one first transport sub-carrier comprises a plurality of side by side first transport sub-carriers and the at least one second transport sub-carrier comprises a plurality of side by side second transport sub-carriers,
the planar shape of the first transmission sub-carriers positioned at two sides in the plurality of side-by-side first transmission sub-carriers is approximately a single-side trapezoid;
the planar shape of the second transmission sub-carriers positioned at two sides in the plurality of side-by-side second transmission sub-carriers is approximately a single-side trapezoid;
the planar shape of the rest first transmission sub-carriers except the first transmission sub-carriers positioned at two sides in the plurality of side-by-side first transmission sub-carriers is approximately a double-sided trapezoid;
the planar shape of the rest of the plurality of second transmission sub-carriers, except the second transmission sub-carriers positioned at two sides, is approximately a double-sided trapezoid.
5. The circuit arrangement of claim 1 or 2, wherein the first signal transport carrier is configured to be coupled to a first signal source to receive the first signal and the second signal transport carrier is configured to be coupled to a second signal source to receive the second signal.
6. The circuit structure of claim 1 or 2, further comprising a third signal transport carrier on the substrate and on a side of the first signal transport carrier remote from the second signal transport carrier, comprising a third body extending in a fourth direction and at least one third transport sub-carrier extending from the third body, configured to transport a third signal;
the first signal transmission carrier further comprises at least one fourth transmission sub-carrier extending out of the first main body and positioned on one side of the first main body close to the third main body;
the at least one third transmission sub-carrier is positioned on one side of the third body close to the first body,
the at least one third transmission sub-carrier and the at least one fourth transmission sub-carrier are insulated from each other and staggered;
the at least one third transmission sub-carrier and the at least one fourth transmission sub-carrier are opposite to each other for forming at least part of the capacitance;
at the opposite, a projection of the third transport sub-carrier onto the surface of the substrate includes a third side proximate to the fourth transport sub-carrier, a projection of the fourth transport sub-carrier onto the surface of the substrate includes a fourth side proximate to the third transport sub-carrier,
a third side of the third transport sub-carrier includes a third intersection point intersecting the third body, a fourth side of the fourth transport sub-carrier includes a fourth intersection point intersecting the first body,
a distance between the third intersection point and the fourth intersection point in a fifth direction is a third distance, the fifth direction is perpendicular to an extending direction of the third transport sub-carrier or the fourth transport sub-carrier, and a minimum distance between the third side and the fourth side is a fourth distance,
the third distance is less than the fourth distance.
7. The circuit structure of claim 6, wherein the four directions are parallel to or cross the first direction or the second direction.
8. The circuit arrangement of claim 6, wherein the third signal transport carrier is configured to be coupled to the third signal source to receive the third signal.
9. The circuit arrangement according to any of claims 6-8, wherein said at least one third transport sub-carrier comprises a plurality of side-by-side third transport sub-carriers, and said at least one fourth transport sub-carrier comprises a plurality of side-by-side fourth transport sub-carriers,
the planar shape of the third transmission sub-carriers positioned at two sides in the plurality of side-by-side third transmission sub-carriers is approximately a single-side trapezoid;
the planar shape of the fourth transmission sub-carriers positioned at two sides in the plurality of side-by-side fourth transmission sub-carriers is approximately a single-side trapezoid;
the planar shape of the rest of the plurality of side-by-side third transporting sub-carriers except the third transporting sub-carriers positioned at the two sides is approximately a double-sided trapezoid,
the planar shape of the rest of the plurality of side-by-side fourth transmission sub-carriers except the fourth transmission sub-carriers positioned at the two sides is approximately a double-sided trapezoid.
10. A circuit structure for reducing capacitance, comprising:
a substrate;
a first signal transmission carrier on the substrate, including a first body extending in a first direction and at least one first transmission sub-carrier extending from the first body, configured to transmit a first signal;
a second signal transmission carrier on the substrate, including a second body extending in the second direction and at least one second transmission sub-carrier extending from the second body, configured to transmit a second signal,
wherein the at least one first transmission sub-carrier is located at a side of the first body close to the second body, and the at least one second transmission sub-carrier is located at a side of the second body close to the first body,
the at least one second transmission sub-carrier and the at least one first transmission sub-carrier are insulated and staggered from each other;
the at least one first transmission subcarrier and the at least one second transmission subcarrier are opposite to form at least part of the capacitor;
at the opposite, a projection of the first transport sub-carrier on the surface of the substrate includes a first edge near the second transport sub-carrier, a projection of the second transport sub-carrier on the surface of the substrate includes a second edge near the first transport sub-carrier,
a first included angle is formed between a straight line of the first edge of the first transmission sub-carrier along the extension direction of the first edge and a straight line of the first main body along the first direction,
a second included angle is formed between a straight line of a second edge of the second transmission sub-carrier along the extension direction of the second edge and a straight line of the second main body along the second direction,
the first included angle and the second included angle are arranged oppositely, and at least one of the first included angle and the second included angle is an obtuse angle.
11. The circuit structure of claim 10, further comprising a third signal transport carrier on the substrate and on a side of the first signal transport carrier remote from the second signal transport carrier, comprising a third body extending in a fourth direction and at least one third transport sub-carrier extending from the third body configured to transport a third signal;
the first signal transmission carrier further comprises at least one fourth transmission subcarrier and is positioned on one side, close to the third body, of the first body;
the at least one third transmission sub-carrier is positioned on one side of the third body close to the first body,
the at least one third transmission sub-carrier and the at least one fourth transmission sub-carrier are insulated from each other and staggered;
the at least one third transmission sub-carrier and the at least one fourth transmission sub-carrier are opposite to each other for forming at least part of the capacitance;
at the opposite, a projection of the third transport sub-carrier onto the surface of the substrate includes a third side proximate to the fourth transport sub-carrier, a projection of the fourth transport sub-carrier onto the surface of the substrate includes a fourth side proximate to the third transport sub-carrier,
a third included angle is formed between a straight line of a third edge of the third transmission sub-carrier along the extending direction of the third edge and a straight line of the third main body along the third direction,
a fourth included angle is formed between the straight line of the fourth edge of the fourth transmission sub-carrier along the extension direction of the fourth edge and the straight line of the first main body along the first direction,
the third included angle and the fourth included angle are arranged oppositely, and at least one of the third included angle and the fourth included angle is an obtuse angle.
12. An electrostatic protection circuit comprising the reduced capacitance circuit arrangement of any of claims 1-11.
13. The electrostatic protection circuit of claim 12, further comprising an input, a first electrostatic sub-circuit and a second electrostatic sub-circuit; wherein the content of the first and second substances,
the input terminal is connected with the first signal transmission carrier to transmit the first signal,
the first electrostatic sub-circuit is connected to the first signal transmitting carrier and the second signal transmitting carrier,
the second electrostatic sub-circuit is connected with the first signal transmission carrier and the third signal transmission carrier.
14. The electrostatic protection circuit of claim 13, wherein the input is connected with a high speed input/output interface to receive the first signal.
15. The electrostatic protection circuit of claim 13, wherein the first electrostatic sub-circuit comprises a first diode, a first pole of the first diode and the first transport sub-carrier are connected, and a second pole of the first diode and the second transport sub-carrier are connected.
16. The electrostatic protection circuit of claim 13, wherein the circuit structure further comprises a third signal transmission carrier located on a side of the first signal transmission carrier away from the second signal transmission carrier, comprising a third body extending in a third direction and at least one third transmission sub-carrier extending from the third body, configured to transmit a third signal;
the first signal transmission carrier further comprises at least one fourth transmission subcarrier and is positioned on one side, close to the third body, of the first body;
the at least one third transmission sub-carrier is positioned on one side of the third body close to the first body,
the second electrostatic sub-circuit comprises a second diode, a first pole of the second diode is connected with the fourth transmission sub-carrier, and a second pole of the second diode is connected with the third transmission sub-carrier.
17. An electrostatic protection circuit according to claim 13 or 14, wherein the first and second electrostatic sub-circuits are implemented as transistors.
18. An electronic device comprising the electrostatic protection circuit of any of claims 12-17.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011116691.3A CN112331646A (en) | 2020-10-19 | 2020-10-19 | Circuit structure for reducing capacitance, electrostatic protection circuit, and electronic apparatus |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011116691.3A CN112331646A (en) | 2020-10-19 | 2020-10-19 | Circuit structure for reducing capacitance, electrostatic protection circuit, and electronic apparatus |
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| CN112331646A true CN112331646A (en) | 2021-02-05 |
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000261269A (en) * | 1999-03-05 | 2000-09-22 | Nec Corp | Surface acoustic wave filter and characteristic adjustment method for surface acoustic wave |
| JP2005006015A (en) * | 2003-06-11 | 2005-01-06 | Seiko Epson Corp | Surface acoustic wave filter |
| US20050139885A1 (en) * | 2003-12-31 | 2005-06-30 | Via Technologies, Inc. | Capacitor pair structure for increasing the match thereof |
| JP2005191052A (en) * | 2003-12-24 | 2005-07-14 | Sumitomo Electric Ind Ltd | Semiconductor device and its manufacturing method |
| US20070215948A1 (en) * | 2006-03-17 | 2007-09-20 | Samsung Electronics Co., Ltd. | Semiconductor device having function of improved electrostatic discharge protection |
| US20070228424A1 (en) * | 2006-03-31 | 2007-10-04 | Eudyna Devices Inc. | Semiconductor device and method of manufacturing the same |
| US20080111193A1 (en) * | 2006-11-10 | 2008-05-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Serpentine ballasting resistors for multi-finger ESD protection device |
| CN102842576A (en) * | 2011-06-22 | 2012-12-26 | 半导体元件工业有限责任公司 | Semiconductor device |
-
2020
- 2020-10-19 CN CN202011116691.3A patent/CN112331646A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000261269A (en) * | 1999-03-05 | 2000-09-22 | Nec Corp | Surface acoustic wave filter and characteristic adjustment method for surface acoustic wave |
| JP2005006015A (en) * | 2003-06-11 | 2005-01-06 | Seiko Epson Corp | Surface acoustic wave filter |
| JP2005191052A (en) * | 2003-12-24 | 2005-07-14 | Sumitomo Electric Ind Ltd | Semiconductor device and its manufacturing method |
| US20050139885A1 (en) * | 2003-12-31 | 2005-06-30 | Via Technologies, Inc. | Capacitor pair structure for increasing the match thereof |
| US20070215948A1 (en) * | 2006-03-17 | 2007-09-20 | Samsung Electronics Co., Ltd. | Semiconductor device having function of improved electrostatic discharge protection |
| US20070228424A1 (en) * | 2006-03-31 | 2007-10-04 | Eudyna Devices Inc. | Semiconductor device and method of manufacturing the same |
| US20080111193A1 (en) * | 2006-11-10 | 2008-05-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Serpentine ballasting resistors for multi-finger ESD protection device |
| CN102842576A (en) * | 2011-06-22 | 2012-12-26 | 半导体元件工业有限责任公司 | Semiconductor device |
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Application publication date: 20210205 |
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