CN112331155A - Signal driving board - Google Patents
Signal driving board Download PDFInfo
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- CN112331155A CN112331155A CN202011186097.1A CN202011186097A CN112331155A CN 112331155 A CN112331155 A CN 112331155A CN 202011186097 A CN202011186097 A CN 202011186097A CN 112331155 A CN112331155 A CN 112331155A
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- module
- pcie
- signal
- electrically connected
- processing module
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
Abstract
The embodiment of the invention provides a signal driving board, which comprises an interface module, a processing module, a PCIE module, an PCIE SWICH module, a plurality of slots and a plurality of FPGA daughter boards; the processing module is electrically connected with the interface module and is used for receiving the image signal through the interface module; the PCIE module is electrically connected with the processing module and used for receiving the image signals sent by the processing module and dividing the image signals into n paths of sub-image signals according to the number n of the FPGA daughter boards; the PCIE SWICH module is electrically connected with the PCIE module and is used for receiving n paths of sub-image signals transmitted by the PCIE module; the PCIE SWICH module comprises a plurality of PCIE SWICH units, the number of PCIE SWICH units is the same as that of slots, each PCIE SWICH unit is electrically connected with one slot, and one FPGA daughter board is detachably and electrically connected with one slot; the FPGA daughter board is electrically connected with the display panel and used for transmitting the sub-image signals to the display panel. The signal driving board provided by the embodiment of the invention can drive the display panels with different resolutions without manufacturing a new signal driving board again.
Description
Technical Field
The invention relates to the field of display driving, in particular to a signal driving board.
Background
With the development of scientific technology, the display technology is more advanced, and the resolution of the display panel is higher and higher. From the traditional CRT television, to the plasma television, and then to the liquid crystal television, the display screen of the television displays more and more clear pictures, and the resolution also rises linearly from 480P to 720P, 1080P to 4K, and then to the current 8K.
Display technology is continuously developed, 8K liquid crystal display screens exist at present, and 10K, 16K or 20K liquid crystal display screens may exist in the future. Therefore, along with the fact that the resolution ratio of liquid crystal display screen production of manufacturers is higher and higher, the requirement on the driving capability of the graphic signal of downstream detection equipment is higher and higher.
The signal driving board of the existing liquid crystal television is basically molded in one version, so long as the signal driving board of the liquid crystal television is within the specification of a client, the signal driving board of the liquid crystal television only has so many specifications, if the client is upgraded subsequently, the signal driving board of the liquid crystal television can only be replaced, the signal driving board of the downstream liquid crystal television can only be designed and produced again continuously, and each design needs a certain debugging period and a certain production period.
Disclosure of Invention
The signal driving board provided by the embodiment of the invention can drive the display panels with different resolutions to display high-definition images without manufacturing a new signal driving board again.
The embodiment of the invention provides a signal driving board, which comprises an interface module, a processing module, a PCIE module, an PCIE SWICH module, a plurality of slots and a plurality of FPGA daughter boards;
the processing module is electrically connected with the interface module and is used for receiving image signals or control instruction signals through the interface module or sending set signals to external equipment through the interface module;
the PCIE module is electrically connected with the processing module and is used for receiving the image signals sent by the processing module and dividing the image signals into n paths of sub-image signals according to the number n of the FPGA daughter boards;
the PCIE SWICH module is electrically connected with the PCIE module and configured to receive n paths of sub-image signals transmitted by the PCIE module; the PCIE SWICH module comprises a plurality of PCIE SWICH units, the number of the PCIE SWICH units is the same as that of the slots, each PCIE SWICH unit is electrically connected with one slot, and one FPGA daughter board is detachably and electrically connected with one slot; each path of sub-image signal is transmitted to one FPGA daughter board through one PCIE SWICH unit;
the FPGA daughter board is electrically connected with the display panel and used for transmitting the sub-image signals to the display panel.
Optionally, the FPGA daughter board sends the sub-image signal to the display panel in a V-BY-ONE signal form, an EDP signal form, or an LVDS signal form.
Optionally, the processing module is electrically connected to the FPGA daughter board through a bus, and the FPGA daughter board is configured to send an insertion signal to the processing module through the bus when being electrically connected to the socket.
Optionally, the PCIE SWICH unit includes a switch; the switch is electrically connected with the slot correspondingly, and the processing module is used for conducting the switch when receiving an insertion signal.
Optionally, the slot supports displayport2.0 protocol and PCIE4.0 protocol.
Optionally, the interface module includes a network port, the network port is electrically connected to the processing module, and the processing module is configured to receive the image signal and the control instruction signal through the network port.
Optionally, the interface module includes an asynchronous serial communication port, the asynchronous serial communication port is electrically connected to the processing module, the asynchronous serial communication port is used for connecting an external device, and the processing module is used for controlling the external device through the asynchronous serial communication port to implement device testing.
Optionally, the interface module includes a USB interface, the USB interface is electrically connected to the processing module, the USB interface is used for externally connecting a USB device, and the processing module is used for exporting data of the signal driving board to the USB device through the USB interface, or importing an image signal through the USB device, or performing error checking through the USB device.
Optionally, the signal driving board further includes a power supply module, and the power supply module is configured to supply power to the processing module, the PCIE module, and the FPGA daughter board.
Optionally, the driving capability of a plurality of the FPGA daughter boards is different.
The processing module in the signal driving board provided by the embodiment of the invention is used for receiving the image signals transmitted by the interface module and transmitting the image signals to the PCIE module, the PCIE module divides the image signals into the same number of paths as the number of the FPGA daughter boards according to the number of the FPGA daughter boards inserted into the slots, and the image signals are transmitted to the display panel through the FPGA daughter boards. The signal drive board that this embodiment provided can be according to the nimble number and the driving capability of adjusting the FPGA daughter board of image signal's size, need not to make new signal drive board again and just can drive different resolution ratio display panels and show high definition image, and this signal drive board can reduce manufacturing cost in the in-service use, improves the definition of display panel display image.
Drawings
Fig. 1 is a schematic structural diagram of a signal driving board according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of an FPGA daughter board supporting V-BY-ONE signal output according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of an FPGA daughter board supporting EDP signal output according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of an FPGA daughter board supporting LVDS signal output according to an embodiment of the present disclosure;
fig. 5 is a schematic structural diagram of another signal driving board according to an embodiment of the present invention.
Detailed Description
The embodiments of the present invention will be described in further detail with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of and not restrictive on the broad invention. It should be further noted that, for convenience of description, only some structures, not all structures, relating to the embodiments of the present invention are shown in the drawings.
The embodiment of the invention provides a signal driving board, which comprises an interface module 110, a processing module 120, a PCIE module 130, an PCIE SWICH module 140, a plurality of slots 150 and a plurality of FPGA daughter boards 160; the processing module 120 is electrically connected to the interface module 110, and is configured to receive an image signal or a control instruction signal through the interface module 110, or send a setting signal to an external device through the interface module 110; the PCIE module 130 is electrically connected to the processing module 120, and is configured to receive the image signal sent by the processing module 120, and divide the image signal into n paths of sub-image signals according to the number n of the FPGA daughter boards 160; PCIE SWICH module 140 is electrically connected to PCIE module 130, and is configured to receive n paths of sub-image signals transmitted by PCIE module 130; PCIE SWICH module 140 includes a plurality of PCIE SWICH units 141, PCIE SWICH units 141 are the same number as slots 150, each PCIE SWICH unit 141 is electrically connected to a slot 150, and an FPGA daughter board 160 is removably electrically connected to a slot 150; each path of sub-image signals are transmitted to an FPGA daughter board 160 through an PCIE SWICH unit 141; the FPGA daughter board 160 is electrically connected to the display panel for transmitting the sub-image signal to the display panel.
For example, the display panel may be a liquid crystal display panel, but is not limited to a liquid crystal display panel, and may also be an OLED display panel, and the like, and is not limited specifically.
Specifically, the setting signal may be a control command signal, a data signal, or the like. One slot 150 is correspondingly and electrically connected with one FPGA daughter board 160, and the FPGA daughter board 160 and the slot 150 are detachable, so that the FPGA daughter board 160 can be conveniently replaced. The PCIE module 130 divides the image signals into corresponding paths according to the number of the FPGA sub-board 160, for example, eight slots 150 are provided, if only two slots 150 are inserted into the FPGA sub-board 160, the PCIE module 130 divides the image signals into two paths, and transmits the image signals to the FPGA sub-board 160 through two PCIE SWICH units 141. Further, the processing module 120 may be an ARM.
The processing module 120 in the signal driving board provided in the embodiment of the present invention is configured to receive the image signal transmitted by the interface module 110, and transmit the image signal to the PCIE module 130, the PCIE module 130 divides the image signal into the same number of paths as the number of the FPGA daughter boards 160 according to the number of the FPGA daughter boards 160 inserted into the slot 150, and the image signal is transmitted to the display panel through the FPGA daughter board 160. In practical applications, the number of the FPGA daughter boards 160 can be selected according to the size of the image signal, for example: the higher the resolution of the display panel, the larger the size of the image signal, the more FPGA daughter boards 160 may be inserted. In addition, the driving capability of the FPGA sub-board 160 may be adjusted according to the size of the image signal to drive the display panels with different resolutions by the driving board. For example, the socket 150 may be inserted with an FPGA daughter board 160 supporting 16lane V-BY-ONE output signals, and four pieces of FPGA daughter boards 160 may be inserted to meet the driving requirements of the existing commercially available 8K 120HZ display panel, or two pieces of FPGA daughter boards 160 of 32lane V-BY-ONE may meet the driving requirements of the 8K 120HZ display panel.
The signal drive board provided by the embodiment can flexibly adjust the number and the driving capability of the FPGA daughter board 160 according to the size of the image signal, and can drive the display panels with different resolutions to display high-definition images without manufacturing a new signal drive board again.
Optionally, the FPGA daughter board sends the sub-image signal to the display panel in a V-BY-ONE signal form, an EDP signal form, or an LVDS signal form.
For example, fig. 2 is a schematic structural diagram of an FPGA daughter board supporting V-BY-ONE signal output according to an embodiment of the present invention, when the FPGA daughter board supporting V-BY-ONE signal output is inserted into a slot, an image signal is converted into a V-BY-ONE signal through the FPGA daughter board and is input to a liquid crystal display panel, and a DDR (Double Data Rate) in fig. 2 has a cache function. Fig. 3 is a schematic structural diagram of an FPGA daughter board supporting EDP signal output according to an embodiment of the present invention, where when the FPGA daughter board supporting EDP signal output is inserted into a slot, an image signal is converted into an EDP signal through the FPGA daughter board and is input to a liquid crystal display panel. Fig. 4 is a schematic structural diagram of an FPGA daughter board supporting LVDS signal output according to an embodiment of the present invention, where when the FPGA daughter board supporting LVDS signal output is inserted into a slot, an image signal is converted into an LVDS signal through the FPGA daughter board and is input to a liquid crystal display panel. The FPGA daughter board supports the output of various signals and can be suitable for a liquid crystal display panel with multiple signal types. Optionally, with continued reference to fig. 1, the processing module 120 is electrically connected to the FPGA daughter board 160 through a bus, and the FPGA daughter board 160 is configured to send an insertion signal to the processing module 120 through the bus when electrically connected to the socket 150.
Specifically, when the FPGA daughter board 160 is electrically connected to the socket 150, the FPGA daughter board 160 sends an insertion signal to the processing module 120 through the bus, and the processing module 120 receives the insertion signal to determine the number and the type of the FPGA daughter boards 160 inserted into the socket 150. In addition, the processing module 120 can also send the information of the upgrade software to the FPGA sub-board 160 through the bus. Illustratively, the FPGA daughter board 160 supporting the V-BY-ONE signal output is inserted into the slot 150, and when the V-BY-ONE protocol is upgraded, the processing module 120 may send an upgrade signal to the FPGA daughter board 160 supporting the V-BY-ONE signal output through the bus, so that the FPGA daughter board 160 with stronger driving capability may be upgraded without replacing hardware.
Optionally, unit PCIE SWICH includes a switch; the switch is electrically connected with the slot correspondingly, and the processing module is used for conducting the switch when receiving the insertion signal.
Illustratively, one PCIE SWICH unit includes a switch, one switch is electrically connected to one socket, and one socket can only be electrically connected to one FPGA daughter board, and when one socket is electrically connected to the FPGA daughter board, the FPGA daughter board sends an insertion signal to the processing module through the bus, and the processing module sends a signal for opening the switch to the corresponding PCIE SWICH unit, and when the switch in the PCIE SWICH unit is opened, the image signal can be transmitted to the FPGA daughter board through the PCIE SWICH unit.
Optionally, the slot supports Display Port2.0 protocol and PCIE4.0 protocol.
For example, the PCIE protocol already has a PCIE4.0 protocol at present, and a higher PCIE protocol version is provided later. The slot is used as a channel for transmitting images between the processing module and the FPGA daughter board, a PCIE 3.0 protocol is commonly used at present, and the slot in the signal driving board provided by the embodiment supports the PCIE4.0 protocol, which means that the slot in the signal driving board can be kept unchanged for a long period of time later, and if necessary, software in the FPGA daughter board can be directly upgraded, so that the frequency of replacing the signal driving board is reduced, and the production cost is reduced. With the distribution of the DisplayPort2.0 protocol, the EDP signal can also easily realize the driving of 8K and 16K high-definition images, and the FPGA daughter board is not only limited to supporting the output of the V-BY-ONE signal, but also can support the output of the EDP signal.
Optionally, fig. 5 is a schematic structural diagram of another signal driving board according to an embodiment of the present invention, referring to fig. 5, the interface module 110 includes a network port 111, the network port 111 is electrically connected to the processing module 120, and the processing module 120 is configured to receive an image signal and a control instruction signal through the network port 111.
Illustratively, the network port 111 in the interface module 110 is used to electrically connect to a network cable, the network cable is electrically connected to the network port 111, and the image signal can be transmitted to the processing module 120 through the network cable.
Optionally, with continued reference to fig. 5, the interface module 110 includes an asynchronous serial communication port 112, the asynchronous serial communication port 112 is electrically connected to the processing module 120, the asynchronous serial communication port 112 is used for connecting an external device, and the processing module 120 is used for controlling the external device through the asynchronous serial communication port 112 to implement device testing.
Illustratively, the CA310 color analyzer was optically tested. In addition, the external device may be a camera in an optical instrument, the camera may capture a picture displayed on the liquid crystal display panel, and send the captured picture to the processing module 120, and the processing module 120 analyzes the image quality such as the definition and the gray scale of the picture. The asynchronous serial communication port 112 may also receive video information and pass image information from the video information to the processing module.
Optionally, with reference to fig. 5, the interface module 110 includes a USB interface 113, the USB interface 113 is electrically connected to the processing module 120, the USB interface 113 is used for externally connecting a USB device, and the processing module 120 is used for exporting data of the signal driver board to the USB device through the USB interface 113, or importing an image signal through the USB device, or performing error checking through the USB device.
For example, the USB interface 113 may be electrically connected to a USB device, the USB device may be a mobile hard disk, an image signal in the mobile hard disk may also be transmitted to the processing module 120 through the USB interface 113, and the processing module 120 transmits the image signal to the display panel.
Optionally, with continuing reference to fig. 5, the signal driver board according to the embodiment of the present invention further includes a power module 170, where the power module 170 is configured to supply power to the processing module 120, the PCIE module 130, and the FPGA daughter board 160.
For example, the power module may include a battery, and may also supply power to the processing module, the PCIE module, and the FPGA daughter board by being connected to the mains supply.
Optionally, the driving capability of the plurality of FPGA daughter boards is different.
For example, an FPGA daughter board supporting V-BY-ONE signal output may be inserted into ONE slot, and an FPGA daughter board supporting EDP signal output may be inserted into the other slot, so that the image signal transmitted from the processing module is correspondingly converted into a V-BY-ONE signal or an EDP signal when passing through the two slots. For example, the slot may be inserted into an FPGA daughter board supporting 16lane V-BY-ONE signal output or an FPGA daughter board supporting 32lane V-BY-ONE signal output, and in practical application, the driving capability of the FPGA daughter board and the number of the FPGA daughter boards may be selected according to the size of the image signal.
It should be noted that the foregoing is only a preferred embodiment of the present invention and the technical principles applied. Those skilled in the art will appreciate that the embodiments of the present invention are not limited to the specific embodiments described herein, and that various obvious changes, adaptations, and substitutions are possible, without departing from the scope of the embodiments of the present invention. Therefore, although the embodiments of the present invention have been described in more detail through the above embodiments, the embodiments of the present invention are not limited to the above embodiments, and many other equivalent embodiments may be included without departing from the concept of the embodiments of the present invention, and the scope of the embodiments of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A signal driving board is characterized by comprising an interface module, a processing module, a PCIE module, an PCIE SWICH module, a plurality of slots and a plurality of FPGA daughter boards;
the processing module is electrically connected with the interface module and is used for receiving image signals or control instruction signals through the interface module or sending set signals to external equipment through the interface module;
the PCIE module is electrically connected with the processing module and is used for receiving the image signals sent by the processing module and dividing the image signals into n paths of sub-image signals according to the number n of the FPGA daughter boards;
the PCIE SWICH module is electrically connected with the PCIE module and configured to receive n paths of sub-image signals transmitted by the PCIE module; the PCIE SWICH module comprises a plurality of PCIE SWICH units, the number of the PCIE SWICH units is the same as that of the slots, each PCIE SWICH unit is electrically connected with one slot, and one FPGA daughter board is detachably and electrically connected with one slot; each path of sub-image signal is transmitted to one FPGA daughter board through one PCIE SWICH unit;
the FPGA daughter board is electrically connected with the display panel and used for transmitting the sub-image signals to the display panel.
2. The signal driving board according to claim 1, wherein the FPGA daughter board transmits the sub-image signals to the display panel in a V-BY-ONE signal form, an EDP signal form, or an LVDS signal form.
3. The signal driving board according to claim 1, wherein the processing module is electrically connected to the FPGA daughter board through a bus, and the FPGA daughter board is configured to send an insertion signal to the processing module through the bus when electrically connected to the socket.
4. The signal driving board according to claim 3, wherein the PCIE SWICH unit comprises a switch; the switch is electrically connected with the slot correspondingly, and the processing module is used for conducting the switch when receiving an insertion signal.
5. The signal driving board of claim 1, wherein the socket supports displayport2.0 protocol and PCIE4.0 protocol.
6. The signal driving board according to claim 1, wherein the interface module comprises a network port, the network port is electrically connected to the processing module, and the processing module is configured to receive the image signal and the control command signal through the network port.
7. The signal driving board according to claim 1, wherein the interface module comprises an asynchronous serial communication port, the asynchronous serial communication port is electrically connected to the processing module, the asynchronous serial communication port is used for connecting an external device, and the processing module is used for controlling the external device to realize device testing through the asynchronous serial communication port.
8. The signal driver board according to claim 1, wherein the interface module includes a USB interface, the USB interface is electrically connected to the processing module, the USB interface is used for externally connecting a USB device, and the processing module is used for exporting data of the signal driver board to the USB device through the USB interface, or importing an image signal through the USB device, or performing error checking through the USB device.
9. The signal driving board according to claim 1, further comprising a power module configured to supply power to the processing module, the PCIE module, and the FPGA daughter board.
10. The signal driving board according to claim 1, wherein the plurality of FPGA daughter boards differ in driving capability.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011186097.1A CN112331155A (en) | 2020-10-29 | 2020-10-29 | Signal driving board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011186097.1A CN112331155A (en) | 2020-10-29 | 2020-10-29 | Signal driving board |
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| CN112331155A true CN112331155A (en) | 2021-02-05 |
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| CN202011186097.1A Pending CN112331155A (en) | 2020-10-29 | 2020-10-29 | Signal driving board |
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|---|---|---|---|---|
| US20090140976A1 (en) * | 2007-11-29 | 2009-06-04 | Bae Jae-Sung | Display apparatus and method of driving the same |
| US20110321115A1 (en) * | 2009-01-03 | 2011-12-29 | Haier Group Co. | Tv function expansion component using gold finger connector |
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