CN112327676A - ENDAT data acquisition device, equipment and method - Google Patents
ENDAT data acquisition device, equipment and method Download PDFInfo
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- CN112327676A CN112327676A CN202010978172.1A CN202010978172A CN112327676A CN 112327676 A CN112327676 A CN 112327676A CN 202010978172 A CN202010978172 A CN 202010978172A CN 112327676 A CN112327676 A CN 112327676A
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- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
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Abstract
One embodiment of the invention discloses an ENDAT data acquisition device, equipment and a method, wherein the device comprises: a first MAX3485 transceiver chip and a second MAX3485 transceiver chip; an RO pin of the first MAX3485 transceiver chip is connected with a MISO signal wire of an embedded SPI interface of the microprocessor; the DI pin of the first MAX3485 transceiver chip is connected with the MOSI signal line of the embedded SPI interface; a pin B of the first MAX3485 transceiver chip is connected with a DATA-signal line of the ENDAT encoder, and a pin A is connected with a DATA + signal line of the ENDAT encoder; the/RE end and the DE end of the first MAX3485 transceiver chip are connected with an enable level signal; the DI pin of the second MAX3485 transceiver chip is connected with the CLK signal line of the embedded SPI interface; a pin B of the second MAX3485 transceiver chip is connected with a CLK-signal line of the ENDAT encoder, and a pin A is connected with a CLK + signal line of the ENDAT encoder; the/RE end and DE end of the second MAX3485 transceiver chip are connected with the anode of the power supply.
Description
Technical Field
The invention relates to the field of computers, in particular to an ENDAT data acquisition device, equipment and a method.
Background
The application of the ENDAT in the control industry can be very wide, as long as a system for measuring angles by using a grating is used, most systems need the grating to realize angle acquisition, and especially, most of the very wide grating manufacturers including large manufacturers such as Renysha, Heidenhain and the like adopt the ENDAT protocol to realize angle data acquisition, so how to realize the acquisition of the ENDAT protocol data is the important factor in the control industry.
In a modern control system, one method for obtaining ENDAT data is to adopt a board card provided by a manufacturer, and the other method is to design the board card by the manufacturer to realize data acquisition. The price of the former method is too expensive, which increases the cost of the whole control system; the second method is a mode selected by most control system developers, and has the advantages of flexible development, independent controllability and low development cost.
In a system for realizing data acquisition by designing a board card by self, almost all data acquisition of ENDAT is realized by FPGA or CPLD, the data acquisition is realized by writing a complex verilog time sequence logic module in FGPA or CPLD, after the data acquisition is realized by the FPGA or CPLD, the data is transmitted to a board card controller, a general DSP, ARM or singlechip through a high-speed parallel bus, and the great disadvantage of the design is that in order to read the data of the ENDAT, a piece of FPGA is required to be specially expanded on the board card to realize the data acquisition, and the data acquired by the FPGA is transmitted to an embedded controller.
Disclosure of Invention
Based on the background, the invention provides the ENDAT data acquisition device, the equipment and the method, which have the advantages of simple operation and strong portability, greatly simplifies the design of a system and reduces the cost of the system.
In order to achieve the purpose, the invention adopts the following technical scheme:
one aspect of the present invention provides an indat data acquisition apparatus, the apparatus comprising: a first MAX3485 transceiver chip and a second MAX3485 transceiver chip, wherein,
an RO pin of the first MAX3485 transceiver chip is connected with a MISO signal wire of an embedded SPI interface of the microprocessor;
the DI pin of the first MAX3485 transceiver chip is connected with the MOSI signal line of the embedded SPI interface;
a pin B of the first MAX3485 transceiver chip is connected with a DATA-signal line of the ENDAT encoder, and a pin A is connected with a DATA + signal line of the ENDAT encoder;
the/RE end and the DE end of the first MAX3485 transceiver chip are connected with an enable level signal;
the DI pin of the second MAX3485 transceiver chip is connected with the CLK signal line of the embedded SPI interface;
a pin B of the second MAX3485 transceiver chip is connected with a CLK-signal line of the ENDAT encoder, and a pin A is connected with a CLK + signal line of the ENDAT encoder;
the/RE end and DE end of the second MAX3485 transceiver chip are connected with the anode of the power supply.
In a specific embodiment, the above apparatus further comprises
A first end of the first capacitor is connected with a pin A of the first MAX3485 transceiver chip, and a second end of the first capacitor is connected with a negative electrode of a power supply;
a first resistor having a first end connected to a first end of the first capacitor and a second end connected to a DATA + signal line of the ENDAT encoder;
a second capacitor having a first terminal connected to a second terminal of the first resistor and a DATA-signal line of the ENDAT encoder, and a second terminal connected to a negative terminal of the power supply.
In a specific embodiment, the above apparatus further comprises
And the first end of the third capacitor is connected with the GND end and the power supply cathode of the first MAX3485 transceiver chip, and the second end of the third capacitor is connected with the VCC end and the power supply anode of the first MAX3485 transceiver chip.
In a specific embodiment, the apparatus further includes:
a first end of the fourth capacitor is connected with a pin A of the second MAX3485 transceiver chip, and a second end of the fourth capacitor is connected with a negative electrode of a power supply;
a second resistor having a first end connected to a first end of the fourth capacitor and a second end connected to a CLK + signal line of the ENDAT encoder;
a fifth capacitor, a first end of the fifth capacitor being connected to the second end of the second resistor and the CLK-signal line of the ENDAT encoder, a second end of the fifth capacitor being connected to the negative pole of the power supply.
In a specific embodiment, the above apparatus further comprises
And the first end of the sixth capacitor is connected with the GND end and the power supply cathode of the second MAX3485 transceiver chip, and the second end of the sixth capacitor is connected with the VCC end and the power supply anode of the second MAX3485 transceiver chip.
In one embodiment, the first and second capacitors have a capacitance of 370 pF.
In one embodiment, the capacitance values of the fourth capacitor and the fifth capacitor are 370 pF.
Another aspect of the present invention provides an indat data acquisition apparatus, including:
the above-described device;
a microprocessor; and
an ENDAT encoder.
In another aspect, the present invention provides a method for acquiring data by utilizing the above apparatus, where the method includes the following steps:
s101, configuring the SPI to be 8 bits;
s102: setting a/RE end and a DE end of a first MAX3485 transceiver chip to be a low level and a high level respectively;
s103, the microprocessor sends two idle bits and a 6-bit mode word 000111 to the ENDAT encoder through the MISO signal line or the MOSI signal line;
s104, delaying preset time to wait for the completion of transmission;
s105, continuously sending invalid data bits with preset length after the sending is finished;
s106, setting the RE end and the DE end of a first MAX3485 transceiver chip to be a high level and a low level respectively, and receiving ENDAT data from the ENDAT encoder by the microprocessor through the MISO signal line or the MOSI signal line;
s107, the microprocessor judges a start bit from the first bit in the received data of the preset length, and takes out effective data after finding the start bit;
s108, performing CRC check;
and S109, obtaining valid data.
The invention has the following beneficial effects:
the invention makes full use of the communication characteristics of the SPI, carries out time sequence programming through a simple peripheral circuit, has strong universality, strong transportability and accurate transmission, omits the FPGA, reduces the complexity of the system and reduces the cost.
Drawings
In order to more clearly illustrate the embodiments of the present application or the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are one embodiment of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 illustrates a conventional ENDAT data protocol diagram of one embodiment of the present invention.
FIG. 2 shows a hardware interface diagram of one embodiment of the invention.
FIG. 3 shows a flowchart of a method for the SPI to read ENDAT data according to one embodiment of the present invention.
Detailed Description
In order to make the technical solution of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and examples. The present invention will be described in detail with reference to specific examples, but the present invention is not limited to these examples. Variations and modifications may be made by those skilled in the art without departing from the principles of the invention and should be considered within the scope of the invention.
FIG. 1 illustrates a conventional ENDAT data protocol diagram of one embodiment of the present invention;
it can be seen from the figure that to achieve data reading, it is first necessary to keep the first two clock data lines free, then send the pattern word 000111 in the next timing sequence, representing the read angle information, then wait for the arrival of the start signal, then judge the error status, read the angle information and the CRC check code.
The embedded processor adopted by the embodiment has the advantages that the SPI is of a four-wire system and comprises MOSI, MISO, CLK and SPISTE, ENDAT does not need to use a chip selection signal SPISTE, and only needs three signals in the front.
Since ENDAT requires two pairs of differential signals, CLK +, CLK-, DATA + and DATA-, and DATA is bidirectional, but signals of embedded SPI are all unidirectional, conversion is required, the transceiver chip adopted in the embodiment is MAX3485 produced by Maxim corporation, and bidirectional DATA transmission can be realized by controlling the enabling end of MAX 3485.
As shown in FIG. 2, FIG. 2 shows a hardware interface diagram of one embodiment of the invention;
as can be seen from the figure, the specific connection manner of the devices and apparatuses in this embodiment is as follows:
the apparatus and arrangement comprises a first MAX3485 transceiver chip D20, a second MAX3485 transceiver chip D21, a microprocessor and an ENDAT encoder;
an RO pin of the first MAX3485 transceiver chip is connected with a MISO signal wire of an embedded SPI interface of the microprocessor;
the DI pin of the first MAX3485 transceiver chip is connected with the MOSI signal line of the embedded SPI interface;
a pin B of the first MAX3485 transceiver chip is connected with a DATA-signal line of the ENDAT encoder, and a pin A is connected with a DATA + signal line of the ENDAT encoder;
the/RE end and the DE end of the first MAX3485 transceiver chip are connected with an enable level signal;
the DI pin of the second MAX3485 transceiver chip is connected with the CLK signal line of the embedded SPI interface;
a pin B of the second MAX3485 transceiver chip is connected with a CLK-signal line of the ENDAT encoder, and a pin A is connected with a CLK + signal line of the ENDAT encoder;
the/RE end and the DE end of the second MAX3485 transceiver chip are connected with the anode of a power supply;
in addition, the apparatus further comprises:
a capacitor C95 with a capacitance value of 370pF, a first end of the capacitor C95 is connected with the A pin of the first MAX3485 transceiver chip, and a second end of the capacitor C95 is connected with the negative Power of the Power supply;
a resistor R93, a first end of the resistor R93 being connected to a first end of the capacitor C95, a second end of the resistor C95 being connected to the DATA + signal line of the ENDAT encoder;
a capacitor C96 having a capacitance of 370pF, a first terminal of the capacitor C96 being connected to the second terminal of the resistor R93 and the DATA-signal line of the ENDAT encoder, a second terminal of the capacitor C96 being connected to the negative Power of the Power supply;
a first end of the capacitor C100 is connected to the GND end of the first MAX3485 transceiver chip and the Power supply negative Power-, and a second end of the capacitor C100 is connected to the VCC end of the first MAX3485 transceiver chip D20 and the Power supply positive electrode VDD 3.3;
a capacitor C97 with a capacitance value of 370pF, a first end of the capacitor C97 is connected with the A pin of the second MAX3485 transceiver chip, and a second end of the capacitor C97 is connected with the negative Power of the Power supply;
a resistor R94, a first end of the resistor R94 being connected to a first end of the capacitor C97, a second end of the resistor R94 being connected to the CLK + signal line of the ENDAT encoder;
a capacitor C98 with a capacitance value of 370pF, a first end of the capacitor C98 is connected with a second end of the resistor R94 and the CLK-signal line of the ENDAT encoder, and a second end of the capacitor C98 is connected with the negative Power of the Power supply;
a capacitor C99, wherein a first end of the capacitor C99 is connected with the GND terminal and the Power negative pole Power of the second MAX3485 transceiver chip D21, and a second end of the capacitor C99 is connected with the VCC terminal and the Power positive pole VDD3.3 of the second MAX3485 transceiver chip D21;
in the present embodiment, the resistance values of the resistors R93 and R94 are 120 ohms; the capacitance values of the capacitors C99 and C100 were 0.1 uF.
With the above devices and apparatuses, this embodiment further provides an indat data acquisition method, as shown in fig. 3, fig. 3 shows a flowchart of a method for reading indat data by an SPI according to an embodiment of the present invention;
in order to adapt to all microprocessors, including DSP, ARM, and single chip, the present embodiment uses 8-bit SPI.
As can be seen from fig. 3, the method steps of the method are as follows:
s101, configuring the SPI to be 8 bits;
s102: setting a/RE end and a DE end of a first MAX3485 transceiver chip to be a low level and a high level respectively;
s103, the microprocessor sends two idle bits and a 6-bit mode word 000111 to the ENDAT encoder through the MISO signal line or the MOSI signal line;
s104, delaying preset time to wait for the completion of transmission;
s105, continuously sending invalid data bits with preset length after the sending is finished;
s106, setting the RE end and the DE end of a first MAX3485 transceiver chip to be a high level and a low level respectively, and receiving ENDAT data from the ENDAT encoder by the microprocessor through the MISO signal line or the MOSI signal line;
s107, the microprocessor judges a start bit from the first bit in the received data of the preset length, and takes out effective data after finding the start bit;
s108, performing CRC check;
s109, obtaining valid data
In this embodiment, the delay time of step S104 is 1us, and in step S105, 40 invalid data bits are selected to be transmitted.
In addition, those skilled in the art can appreciate that the object of the present invention can be achieved by changing the value of the delay time or the transmitted invalid data bits and then adjusting the parameters of each device specifically.
It should be understood that the above-mentioned embodiments of the present invention are only examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention, and it will be obvious to those skilled in the art that other variations or modifications may be made on the basis of the above description, and all embodiments may not be exhaustive, and all obvious variations or modifications may be included within the scope of the present invention.
Claims (9)
1. An apparatus for data acquisition with ENDAT, the apparatus comprising: a first MAX3485 transceiver chip and a second MAX3485 transceiver chip, wherein,
an RO pin of the first MAX3485 transceiver chip is connected with a MISO signal wire of an embedded SPI interface of the microprocessor;
the DI pin of the first MAX3485 transceiver chip is connected with the MOSI signal line of the embedded SPI interface;
a pin B of the first MAX3485 transceiver chip is connected with a DATA-signal line of the ENDAT encoder, and a pin A is connected with a DATA + signal line of the ENDAT encoder;
the/RE end and the DE end of the first MAX3485 transceiver chip are connected with an enable level signal;
the DI pin of the second MAX3485 transceiver chip is connected with the CLK signal line of the embedded SPI interface;
a pin B of the second MAX3485 transceiver chip is connected with a CLK-signal line of the ENDAT encoder, and a pin A is connected with a CLK + signal line of the ENDAT encoder;
the/RE end and DE end of the second MAX3485 transceiver chip are connected with the anode of the power supply.
2. The apparatus of claim 1, further comprising
A first end of the first capacitor is connected with a pin A of the first MAX3485 transceiver chip, and a second end of the first capacitor is connected with a negative electrode of a power supply;
a first resistor having a first end connected to a first end of the first capacitor and a second end connected to a DATA + signal line of the ENDAT encoder;
a second capacitor having a first terminal connected to a second terminal of the first resistor and a DATA-signal line of the ENDAT encoder, and a second terminal connected to a negative terminal of the power supply.
3. The apparatus of claim 1, further comprising
And the first end of the third capacitor is connected with the GND end and the power supply cathode of the first MAX3485 transceiver chip, and the second end of the third capacitor is connected with the VCC end and the power supply anode of the first MAX3485 transceiver chip.
4. The apparatus of claim 1, further comprising:
a first end of the fourth capacitor is connected with a pin A of the second MAX3485 transceiver chip, and a second end of the fourth capacitor is connected with a negative electrode of a power supply;
a second resistor having a first end connected to a first end of the fourth capacitor and a second end connected to a CLK + signal line of the ENDAT encoder;
a fifth capacitor, a first end of the fifth capacitor being connected to the second end of the second resistor and the CLK-signal line of the ENDAT encoder, a second end of the fifth capacitor being connected to the negative pole of the power supply.
5. The apparatus of claim 1, further comprising
And the first end of the sixth capacitor is connected with the GND end and the power supply cathode of the second MAX3485 transceiver chip, and the second end of the sixth capacitor is connected with the VCC end and the power supply anode of the second MAX3485 transceiver chip.
6. The apparatus of claim 2, wherein the first and second capacitors have a capacitance value of 370 pF.
7. The apparatus of claim 4, wherein the capacitance values of the fourth and fifth capacitors are 370 pF.
8. An ENDAT data acquisition device, comprising:
the device of any one of claims 1-7;
a microprocessor; and
an ENDAT encoder.
9. Method for data acquisition with an apparatus according to any of claims 1-7, characterized in that the method comprises the following steps:
s101, configuring the SPI to be 8 bits;
s102: setting a/RE end and a DE end of a first MAX3485 transceiver chip to be a low level and a high level respectively;
s103, the microprocessor sends two idle bits and a 6-bit mode word 000111 to the ENDAT encoder through the MISO signal line or the MOSI signal line;
s104, delaying preset time to wait for the completion of transmission;
s105, continuously sending invalid data bits with preset length after the sending is finished;
s106, setting the RE end and the DE end of a first MAX3485 transceiver chip to be a high level and a low level respectively, and receiving ENDAT data from the ENDAT encoder by the microprocessor through the MISO signal line or the MOSI signal line;
s107, the microprocessor judges a start bit from the first bit in the received data of the preset length, and takes out effective data after finding the start bit;
s108, performing CRC check;
and S109, obtaining valid data.
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