CN112309890A - System and method for analyzing semiconductor devices - Google Patents

System and method for analyzing semiconductor devices Download PDF

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Publication number
CN112309890A
CN112309890A CN201911094467.6A CN201911094467A CN112309890A CN 112309890 A CN112309890 A CN 112309890A CN 201911094467 A CN201911094467 A CN 201911094467A CN 112309890 A CN112309890 A CN 112309890A
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wafer
dimensional
etching
etch
module
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CN201911094467.6A
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Inventor
韩振熙
李秉镐
李昌奂
李廷民
马圣民
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SK Hynix Inc
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SK Hynix Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H01L21/67063—Apparatus for fluid treatment for etching
    • H01L21/67069—Apparatus for fluid treatment for etching for drying etching
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67288—Monitoring of warpage, curvature, damage, defects or the like
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
    • G01B11/00—Measuring arrangements characterised by the use of optical techniques
    • G01B11/002—Measuring arrangements characterised by the use of optical techniques for measuring two or more coordinates
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
    • G01B11/00—Measuring arrangements characterised by the use of optical techniques
    • G01B11/24—Measuring arrangements characterised by the use of optical techniques for measuring contours or curvatures
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
    • G01B15/00—Measuring arrangements characterised by the use of electromagnetic waves or particle radiation, e.g. by the use of microwaves, X-rays, gamma rays or electrons
    • G01B15/04—Measuring arrangements characterised by the use of electromagnetic waves or particle radiation, e.g. by the use of microwaves, X-rays, gamma rays or electrons for measuring contours or curvatures
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
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    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H01L21/67028—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
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    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67161—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers
    • H01L21/67167—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers surrounding a central transfer chamber
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    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67207—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
    • H01L21/67213—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process comprising at least one ion or electron beam chamber
    • H—ELECTRICITY
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    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H—ELECTRICITY
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    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H—ELECTRICITY
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    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions

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  • Engineering & Computer Science (AREA)
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  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Analysing Materials By The Use Of Radiation (AREA)

Abstract

Systems and methods for analyzing semiconductor devices are disclosed. A system for analyzing a semiconductor device includes an etch module, an analysis module, and a calculation module. The etching module may repeatedly etch the entire surface of the wafer at the same etch rate in order to expose a next surface of the wafer at a next depth where there is an object to be analyzed. The analysis module may obtain two-dimensional structural information from each repeatedly etched surface of the wafer. The computing device is configured to continuously stack the repeatedly obtained two-dimensional structure information to generate a three-dimensional image.

Description

System and method for analyzing semiconductor devices
Cross Reference to Related Applications
This application claims priority from korean application No. 10-2019-0088824 filed on 23.7.2019 with the korean intellectual property office, the disclosure of which is incorporated herein by reference in its entirety.
Technical Field
Various embodiments may relate generally to systems and methods for analyzing semiconductor devices, and more particularly, to systems and methods for analyzing structures of semiconductor devices.
Background
Current technologies used in the fabrication of semiconductor devices can produce highly integrated three-dimensional structures having dimensions on the order of tens of nanometers. A pattern having such a three-dimensional structure may have various defects in a deep portion of the pattern. These defects at deep portions of the pattern may not be found using current semiconductor inspection equipment to obtain two-dimensional information.
Disclosure of Invention
In an example embodiment of the present disclosure, a system for analyzing a semiconductor device includes an etching module for repeatedly etching an entire surface of a wafer at a same etching rate so as to expose a next surface of the wafer at a next depth where an object to be analyzed exists. The system also includes an analysis module for iteratively obtaining two-dimensional structural information from each iteratively etched surface of the wafer. The system further includes a computing device for successively stacking the repeatedly obtained two-dimensional structure information to generate a three-dimensional image.
In an example embodiment, the etching module includes at least one of a milling device for irradiating an entire surface of the wafer with an ion beam, a Chemical Mechanical Polishing (CMP) device, a dry etching device, and a wet etching device.
The analysis module may include an analysis device configured to obtain two-dimensional information using light, an electron beam, and X-rays, an inspection device, and a calibration device. For example, the analysis module may include at least one of a Scanning Electron Microscope (SEM), a photoelectron emission microscope (PEEM), an X-ray photoelectron spectrometer (XPS), an energy dispersive X-ray analyzer (EDX), and an optical metrology/inspection tool.
Wherein the repeatedly obtained two-dimensional structure information comprises two-dimensional images, the computing device may comprise a controller for classifying the two-dimensional images according to etch depth and two-dimensional coordinates (X, Y) for successively stacking the two-dimensional images based on the etch depth and the two-dimensional coordinates to generate a three-dimensional image. The computing device may also include a memory for storing the classified two-dimensional image.
In an example embodiment of the present disclosure, a method of analyzing a semiconductor device includes: the entire surface of the wafer is repeatedly etched to a target depth at the same etch rate to expose the next surface of the wafer. The method also includes iteratively obtaining two-dimensional structural information from each iteratively etched surface of the wafer. The method further includes successively stacking the two-dimensional structure information repeatedly obtained to generate a three-dimensional image.
In an example embodiment, obtaining the two-dimensional structure information includes obtaining two-dimensional physical information of the wafer and obtaining two-dimensional electrical information of the wafer.
Drawings
The foregoing and other aspects, features and advantages of the disclosed subject matter will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:
fig. 1 is a block diagram illustrating a system for analyzing a semiconductor device according to an example embodiment;
FIG. 2 is a cross-sectional view illustrating an etch module according to an example embodiment;
FIG. 3 is a block diagram illustrating a computing module according to an example embodiment;
FIG. 4 is a flowchart illustrating operation of a system for analyzing semiconductor devices according to an example embodiment;
FIG. 5 is a cross-sectional view illustrating an etched surface of a wafer according to an example embodiment;
FIG. 6 is a view showing a two-dimensional image of the etched surface of the wafer in FIG. 5;
fig. 7 is a view showing a three-dimensional image generated from the two-dimensional image in fig. 6;
FIG. 8 is a block diagram illustrating an analysis module according to an example embodiment;
fig. 9 and 10 are views illustrating a method of analyzing a semiconductor device using the analysis module in fig. 8; and
fig. 11 is a block diagram illustrating a system for analyzing a semiconductor device according to an example embodiment.
Detailed Description
Various embodiments of the present invention will be described in more detail with reference to the accompanying drawings. The figures are schematic diagrams of various embodiments (and intermediate structures). As such, variations from the configurations and shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Accordingly, the described embodiments should not be construed as limited to the particular configurations and shapes shown herein but are to include deviations in configurations and shapes that do not depart from the spirit and scope of the invention as defined by the appended claims.
The present invention is described herein with reference to cross-sectional and/or plan view illustrations of idealized embodiments of the present invention. However, the embodiments of the invention should not be construed as limiting the inventive concept. Although a few embodiments of the present invention will be shown and described, it would be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the principles and spirit of the invention.
Fig. 1 is a block diagram illustrating a system 100 for analyzing semiconductor devices according to an example embodiment.
Referring to fig. 1, a system 100 for analyzing a semiconductor device may include a two-dimensional information inspection apparatus 110, a calculation apparatus 150, and a cleaning module 180. The two-dimensional information inspection apparatus 110 may include an etching module 120 and an analysis module 130.
The etching module 120 may etch the entire surface of the wafer to a uniform thickness (depth), i.e., an etching target thickness (etching target depth), at the same etching rate. The same etch rate means that different areas of the wafer surface are etched substantially the same distance during the same duration. For example, the etching module 120 may include an ion beam milling apparatus using ion beam etching, a Chemical Mechanical Polishing (CMP) apparatus, a dry etching apparatus, or a wet etching apparatus configured to etch the entire surface of a wafer having a size of about 300 mm. The ion beam milling apparatus may remove a layer on the entire surface of the wafer by ion beam irradiation in a sputtering manner. The ion beam milling apparatus may uniformly irradiate the entire surface of the wafer with the ion beam to remove the entire surface of the wafer with a uniform thickness. The CMP apparatus may remove the entire surface of the wafer with a uniform thickness using the polishing pad.
The etching target thickness (etching target depth) can be set according to the inspection position of the wafer. For example, the etch target thickness may be no greater than about 10nm, taking into account etch depth resolution.
In an example embodiment, the etch module 120 may etch the various layers on the wafer to a uniform target depth (thickness) at the same etch rate. For example, the etch rate of the various layers on the wafer may be about 1. When the etching module 120 includes an ion beam milling device, the milling device may include at least one ion beam source to remove layers on the wafer at the same etching rate.
The analysis module 130 may obtain two-dimensional structural information of the etching surface of the wafer etched by the etching module 120. For example, the analysis module 130 can obtain a two-dimensional image of the etched surface of the wafer w from the ions and electrons emitted from the wafer w. The analysis module 130 may include an analysis device, an inspection device, and a calibration device configured to obtain two-dimensional information using light, an electron beam, and X-rays. For example, the analysis module 130 may include at least one of a Scanning Electron Microscope (SEM) device, a photoelectron emission microscope (PEEM) device, an X-ray photoelectron spectrometer (XPS) device, an energy dispersive X-ray analysis (EDX) device, and an optical metrology/inspection tool. In addition, the analysis module 130 may include a mass spectrometer and/or Optical Emission Spectroscopy (OES) device. The mass spectrometer and/or OES device can measure the amount of by-products generated during etching of the wafer w. The mass spectrometer and/or OES device can provide the amount of by-product to the computing device 150. The computing device 150 can control the target depth of the etch module 120. Computing device 150 may analyze the properties of the byproducts.
Fig. 2 is a cross-sectional view illustrating the etch module 120 of fig. 1 according to an example embodiment.
Referring to fig. 2, for one embodiment, the etch module 120 may include a milling device utilizing an ion beam. In the following, such embodiments are described and reference numeral 120 of the etching module refers to the milling device.
The milling device 120 may include a stage (stage)111 configured to support the wafer w. Wafer w may include a semiconductor substrate 101 and a circuit layer 102, the circuit layer 102 including a plurality of materials on the semiconductor substrate 101.
The milling device 120 may include an ion irradiator 115 (also referred to as an ion accelerator) configured to accelerate ions to irradiate the entire surface of the wafer w with the ion BEAM. The ion radiator 115 may be disposed above the stage 111. The diameter of the ion radiator 115 may be larger than the diameter of the wafer W. The ion radiator 115 may be irradiated with an ion BEAM to uniformly etch the entire surface of the wafer w (i.e., the surface of the circuit layer 102) to a uniform thickness in a direction substantially perpendicular to the surface of the semiconductor substrate 101. The ion BEAM may be incident on the surface of the wafer w in various directions.
In example embodiments, the milling device 120 may concentrate a Focused Ion Beam (FIB) on the surface of the wafer w using a FIB apparatus or radiate a Cluster Ion Beam (CIB) on the surface of the wafer w using a CIB apparatus. The ion beam generated by the FIB method or the CIB method may be irradiated to the entire surface of the wafer w to etch the entire surface of the circuit layer 102 to a uniform thickness.
For example, the milling device 120 may use Ar ions as etching ions.
When the milling device 120 uses FIB or CIB, the etching ions may include a metal source having a low melting point and low reactivity. The metal source may include Al, As, Au, Be, Bi, Cs, Cu, Ga, Ge, Fe, In, Li, Ni, Pb, Pd, Pr, Pt, Zn, and the like. For example, milling device 120 may heat a solid Ga source to generate Ga+Ions. The milling device 120 may comprise an ion gun configured to accelerate Ga with an acceleration voltage+Ion acceleration and irradiation of Ga+Ions. For example, the ion gun can produce an ion beam having an acceleration voltage of about 30keV or higher. When generated by the milling device 120When the ion beam of (2) irradiates the surface of the wafer w, ions and electrons may be emitted from the surface of the wafer w. The milling speed of the ion beam and the depth resolution of the ion beam can be controlled by the current of the ion beam and the incident angle of the ion beam to the surface of the wafer w.
When the etching module 120 includes a FIB device or a CIB device, the analysis module 130 may be disposed in the etching module 120. The analysis module 130 may be positioned above the wafer w to detect ions and electrons emitted from the wafer w. The SEM device 130 may obtain a two-dimensional image of the wafer w from ions and electrons emitted from the wafer w.
Referring to fig. 1, the computing device 150 may successively stack two-dimensional (image) information obtained from the analysis module 130 to obtain a three-dimensional image.
Fig. 3 is a block diagram illustrating computing device 150 of fig. 1, according to an example embodiment.
Referring to fig. 3, computing device 150 may include a controller 152, a memory 154, an input/output unit 156, and an interface unit 158.
The controller 152 may calculate various process monitoring data based on the two-dimensional image I obtained from the analysis module 130. The calculations of the controller 152 may be driven according to algorithms designed to calculate process monitoring data. The controller 152 may continuously stack the two-dimensional images obtained from the analysis module 130 to generate a three-dimensional image.
Memory 154 may include non-volatile storage media. For example, the memory 154 may include a hard disk and/or a memory of a nonvolatile semiconductor device, such as a flash memory, a phase change memory, a magnetic memory, or the like. The memory 154 may store two-dimensional images obtained from the analysis module 130 and image data (such as parameters and three-dimensional images) processed by the computing device 150.
The input/output unit 156 may include a keyboard, keypad, and/or display device.
The image data obtained from the two-dimensional information inspection apparatus 110 may be transmitted to the computing apparatus 150 through the interface unit 158. Data processed by the computing device 150 may be transmitted to the inspection device 110 or other external devices, such as a data server or an Agent Policy Center (APC) server, through the interface unit 158. The interface unit 158 may include a wired communication device, a wireless communication device, and/or a Universal Serial Bus (USB) port. The controller 152, the memory 154, the input/output unit 156, and the interface unit 158 may be coupled to each other via a data bus.
Referring to fig. 1, the cleaning module 180 may clean the etched surface of the wafer w etched to a uniform depth. The cleaning module 180 may include a wet cleaning device or a dry cleaning device.
Fig. 4 is a flowchart illustrating an operation of a system for analyzing a semiconductor device according to example embodiments, fig. 5 is a sectional view illustrating an etched surface of a wafer according to example embodiments, fig. 6 is a view illustrating a two-dimensional image of the etched surface of the wafer in fig. 5, and fig. 7 is a view illustrating a three-dimensional image generated from the two-dimensional image in fig. 6. In an example embodiment, the etching module 120 may include a milling device. The wafer w may include a plurality of contact plugs (plugs) CT1, CT2, and CT3(CT1 to CT 3).
Referring to fig. 4 and 5, a wafer w may be loaded into the two-dimensional information inspection apparatus 110. In operation S1, the etching module 120 may uniformly irradiate the entire surface of the wafer w using the ion beam and etch the entire surface of the wafer w to a target depth. For example, the ion beam may be initially irradiated to the surface a-a' of the wafer w in fig. 5 at an initial target depth. Therefore, the surface of the wafer w can be sputtered and etched to a uniform depth by the ion beam. A mass spectrometer or OES in the analysis module 130 can measure the amount of by-products while the wafer w is being etched by the ion beam. The etch depth of the wafer w can be determined and thus controlled based on the amount of by-products.
In operation S2, the analysis module 130 may measure electrons emitted from the surface of the wafer w to obtain a two-dimensional image of the etched surface of the wafer w. After ion beam milling, an analysis module 130, such as an SEM, EDX, or PEEM, may generate a two-dimensional image of the etched surface of wafer w.
The etching of the wafer w down to the next surface B-B 'in fig. 5 as a target depth is repeated using ions to obtain a two-dimensional image of the etched surface B-B' of the wafer w, and then the etching of the wafer w down to the next surface C-C 'in fig. 5 as a target depth is repeated using an ion beam to obtain a two-dimensional image of the etched surface C-C' of the wafer w. This cycle of etching the target depth and then obtaining a two-dimensional image may be performed iteratively. The difference (gap) between the target depths A-A ', B-B ', and C-C ' in FIG. 5 may be varied. In addition, the surface of the wafer w may be cleaned to obtain a two-dimensional image, and then the surface of the wafer w is etched again.
Under ideal conditions, the two-dimensional image of surface A-A ', the two-dimensional image of surface B-B ', and the two-dimensional image of surface C-C ' may be substantially identical to each other. In practice, however, in the highly integrated three-dimensional device, the sizes and shapes of the contact plugs CT1 to CT3 may be uneven and/or voids v may be generated in the contact plugs CT1 to CT 3. The void v and/or the shape error may be detected in the two-dimensional image from the detection point. Further, the shape of the three-dimensional pattern of the highly integrated semiconductor device may not be predictable.
In an example embodiment, referring to fig. 6, in operation S3, the controller 152 of the computing device 150 may continuously laminate two-dimensional information (such as two-dimensional images obtained by the analysis module 130) to obtain three-dimensional image data. The controller 152 may sort the two-dimensional information measured by the analysis module 130 along the X-Y direction according to the etch depth. The controller 152 may provide the sorted two-dimensional information to the memory 154. In particular, the controller 152 may classify a two-dimensional image of the entire surface of the wafer w into two-dimensional coordinates (X, Y). The controller 152 may provide the two-dimensional coordinates (X, Y) to the memory 154. In addition, the controller 152 may classify the two-dimensional information according to the etching depth order. The controller 152 may provide the sorted two-dimensional information to the memory 154 according to the etch depth order. Although not shown in fig. 3, an additional noise filter for filtering noise in the two-dimensional image may also be disposed in the controller 152.
The controller 152 may align the X-Y coordinates of the two-dimensional images and order them by the target depth to stack the two-dimensional images to obtain a three-dimensional image. The detailed shape of the three-dimensional structure on the wafer w can be predicted based on a tomographic image (fault image) of the wafer w.
For example, the size of the image of the third contact plug CT3 on the surface B-B 'in fig. 6 may be smaller than the size of the image of the third contact plug CT3 on the surface a-a' or C-C ', and the image of the third contact plug CT3 on the surface B-B' in fig. 6 may be deviated from the image of the third contact plug CT3 on the surface a-a 'or C-C'. In the three-dimensional image of the third contact plug CT3 in fig. 7, the third contact plug CT3 is shown to have a different diameter. Therefore, the computing apparatus 150 may detect shape failure (failure), i.e., a physical defect in the third contact plug CT 3. The calculation device 150 may calculate the size of the third contact plug CT3, the distance between the contact plugs CT1 to CT3, the resistance of the contact plugs CT1 to CT3, and expected process parameters.
For example, as shown in fig. 6, when a sectional image of the second contact plug CT2 on the surface C-C 'may have a ring shape, it may be noted that a void may be generated at the surface C-C' of the second contact plug CT 2. Further, portions of the three-dimensional image corresponding to the voids may have a different color or transparency than other portions of the three-dimensional image. The controller 152 of the computing device 150 may rotate and deform (expand and contract) the contours of the three-dimensional image. Therefore, the shape destruction and the internal destruction of the three-dimensional image can be easily detected.
The controller 152 of the computing device 150 may store a two-dimensional image of the wafer w in terms of etch depth and two-dimensional coordinates (X, Y). Accordingly, when the etch depth and the two-dimensional coordinates (X, Y) of the region of interest (ROI) are input by the input/output unit 156, the controller 152 may rotate and/or deform the image of the ROI. The controller 152 may output an image of the ROI to provide the output image to the user.
Fig. 8 is a block diagram illustrating an analysis module 130 according to an example embodiment, and fig. 9 and 10 are views illustrating a method of analyzing a semiconductor device using the analysis module 130 in fig. 8.
Referring to fig. 8, the analysis module 130 may include a first analysis unit 135a and a second analysis unit 135 b. For example, the first analysis unit 135a may comprise an SEM device configured to detect a physical image of the etched surface. The second analysis unit 135b may include an EDX apparatus or a PEEM apparatus configured to display electrical characteristics of the etched surface. The second analysis unit 135b, such as a PEEM device, may graphically represent an electrical property, such as a concentration distribution of particles.
Hereinafter, a method of inspecting a semiconductor device using the analysis module in fig. 8 is described and explained in detail with reference to fig. 9 and 10.
The composite wafer < w0> can be prepared. The composite wafer < w0> may include a semiconductor substrate 10 having MOS transistors. The MOS transistor may include a gate structure, a source 20s and a drain 20d on the semiconductor substrate 10. The gate structure may include a gate insulating layer 12, a gate electrode 15, and a hard mask layer 17, which are sequentially stacked. The gate structure may further include spacers 19 on sidewalls of the gate insulation layer 12, the gate 15 and the hard mask layer 17. The source electrode 20s and the drain electrode 20d may be formed in the semiconductor substrate 10 at both sides of the gate structure. The composite wafer < w0> may further include an insulating interlayer 22, the insulating interlayer 22 being configured to cover the MOS transistor and the contacts 25a, 25b, and 25 c. The contacts 25a, 25b, and 25c may be formed in the insulating interlayer 22. The contacts 25a, 25b, and 25c may contact the gate 15, the source 20s, and the drain 20d, respectively.
The first analysis unit 135a may measure an image I0 of the upper surface of the composite wafer < w0 >. Since the first analysis unit 135a can detect the physical image, the image I0 can show the insulating interlayer 22 and the contacts 25a, 25b, and 25 c. Physical information such as the shapes and positions of the contacts 25a, 25b, and 25c can be identified from the image I0.
The etching module 120 may etch the wafer w to a first target depth da to expose a first surface a-a' of the wafer w. For example, the first target depth da may be the distance from the surface of the composite wafer < w0> to the surface of the hard mask layer 17. The first analysis unit 135a may measure a physical image Ia of the exposed first surface a-a' of the wafer w. The physical image Ia of the first surface a-a' of the wafer w may show the shape and position of the hard mask layer 17, the contacts 25a, 25b and 25c and the insulating interlayer 22 having different properties.
The etch module 120 may then etch the wafer w to a second target depth db to expose a second surface b-b' of the wafer w. For example, the second target depth db may allow the gate 15 to be exposed. The first analysis unit 135a may measure a physical image Ib of the exposed second surface b-b' of the wafer w. The physical image Ib of the second surface b-b' of the wafer w may show the shape and location of the spacers 19, the gate 15, the insulating interlayer 22, and the contacts 25a, 25b, and 25c having different properties.
The etch module 120 may then etch the wafer w to a third target depth dc to expose a third surface c-c' of the wafer w. For example, the third target depth dc may allow the surface of the semiconductor substrate 10 to be exposed. The first and second analyzing units 135a and 135b may measure the two-dimensional physical image Ic and the electrical image IEc of the exposed third surface c-c' of the wafer w. The two-dimensional physical image Ic measured by the first analyzing unit 135a may show the shape and the position of the semiconductor substrate 10, the source electrode 20s, and the drain electrode 20d having different properties. The two-dimensional electrical image IEc measured by the second analysis unit 135b can show the positions of the source and drain electrodes 20s and 20d and the concentration distribution of impurities. As shown in the two-dimensional electrical image IEc, it can be noted that the impurity concentration in the source electrode 20s and the drain electrode 20d can be reduced toward the edge portion according to the gaussian distribution.
The etch module 120 may then etch the wafer w to a fourth target depth dd to expose a fourth surface d-d' of the wafer w. For example, the fourth target depth dd may allow the bottom surface of the source 20s and the bottom surface of the drain 20d to be exposed. The first and second analysis units 135a and 135b may measure the two-dimensional physical image Id and the electrical image IEd of the exposed fourth surface d-d' of the wafer w. The two-dimensional physical image Id measured by the first analysis unit 135a may show the shapes and positions of the drain electrode 20d, the semiconductor substrate 10, and the source electrode 20s having different properties. Since the source and drain electrodes 20s and 20d may be impurity regions, the doping concentration of the source and drain electrodes 20s and 20d may be gradually decreased toward the lower portions of the source and drain electrodes 20s and 20d according to a gaussian distribution. Further, the width of the source and drain electrodes 20s and 20d may also be gradually reduced toward the lower portions of the source and drain electrodes 20s and 20 d. Accordingly, the width of the source and drain electrodes 20s and 20d exposed through the fourth surface d-d 'of the wafer w may be narrower than the width of the source and drain electrodes 20s and 20d exposed through the third surface c-c' of the wafer w. The two-dimensional electrical image IEd measured by the second analysis unit 135b can show the concentration distribution of the source electrode 20s and the drain electrode 20 ds. As shown in the two-dimensional electrical image IEd, it may be noted that the impurity concentration in the source electrode 20s and the drain electrode 20d at the fourth surface d-d 'of the wafer w may be lower than the impurity concentration in the source electrode 20s and the drain electrode 20d at the third surface c-c' of the wafer w.
The controller 152 of the computing device 150 may collect the two-dimensional images I0, Ia, Ib, Ic, Id, IEc, and IEd obtained from the analysis module 130. As shown in fig. 10, the controller 152 may successively stack two-dimensional images to generate a three-dimensional image b corresponding to the actual structure a. Further, the two-dimensional physical images I0, Ia, Ib, Ic, and Id obtained by the first analysis unit 135a and the two-dimensional electrical images IEc and IEd are synthesized with each other to obtain the shapes, positions, and electrical characteristic distributions of the elements in the actual structures in the three-dimensional image. Therefore, the shape damage and the internal damage of the three-dimensional semiconductor device can be easily detected from the three-dimensional image.
Fig. 11 is a block diagram illustrating a system 100a for analyzing semiconductor devices according to an example embodiment.
Referring to fig. 11, the etch module 120, the analysis module 130, the computing device 150, and the cleaning module 180 in the system 100a may be configured in clusters. The wafer w may be on standby at a load lock.
Thus, the cluster of etch modules 120, analysis modules 130, computing device 150, and cleaning modules may be systematized to improve inspection efficiency.
According to example embodiments, a system for inspecting a semiconductor device may etch the entire surface of a wafer to a uniform depth at the same etch rate. A two-dimensional image of the etched surface can be acquired. The system may continuously stack two-dimensional images to generate a three-dimensional image. Therefore, the system can easily detect three-dimensional damage in a highly integrated three-dimensional device from a three-dimensional image of the device obtained by collecting two-dimensional images.
The above-described embodiments of the present teachings are intended to be illustrative, but not limiting, of the present teachings. Various alternatives and equivalents are possible. The present teachings are not limited to the embodiments described herein. Nor is the present teachings limited to any particular type of semiconductor device. Other additions, subtractions or modifications are possible in light of the present disclosure and are intended to fall within the scope of the appended claims.

Claims (19)

1. A system for analyzing semiconductor devices, the system comprising:
an etching module for repeatedly etching an entire surface of a wafer at a same etching rate to expose a next surface of the wafer at a next depth where an object to be analyzed exists;
an analysis module for obtaining two-dimensional structural information from each repeatedly etched surface of the wafer; and
a computing device for successively stacking the two-dimensional structure information obtained repeatedly to generate a three-dimensional image.
2. The system of claim 1, wherein the etch module comprises at least one of:
a milling device for irradiating the entire surface of the wafer with an ion beam;
a chemical mechanical polishing CMP apparatus;
a dry etching device; and
provided is a wet etching device.
3. The system of claim 2, wherein the milling device comprises an ion accelerator for accelerating ions into the entire surface of the wafer to remove material.
4. The system of claim 1, wherein the analysis module comprises at least one of:
a Scanning Electron Microscope (SEM) device;
a photoemission microscope PEEM device;
an energy dispersive X-ray analysis EDX apparatus;
an X-ray photoelectron spectrometer XPS device; and
an optical metrology/inspection tool.
5. The system of claim 1, wherein the analysis module comprises:
a first analysis unit for obtaining a physical image of an etched surface of the wafer; and
a second analysis unit for obtaining an electrical image of the etched surface of the wafer.
6. The system of claim 5, wherein the first analysis unit comprises a Scanning Electron Microscope (SEM) device.
7. The system of claim 5, wherein the second analysis unit comprises at least one of a photoemission microscope (PEEM) device and an energy dispersive X-ray analysis (EDX) device.
8. The system of claim 1, wherein the etch module comprises:
a stage for supporting the wafer; and
an ion accelerator for accelerating ions into an entire surface of the wafer to etch a circuit layer on the wafer.
9. The system of claim 8, wherein the width of the ion accelerator is greater than the width of the wafer such that the accelerated ions are incident normally on the entire surface of the wafer.
10. The system of claim 1, wherein the two-dimensional structure information obtained iteratively comprises two-dimensional images, and wherein the computing device comprises:
a controller for classifying the two-dimensional images according to an etching depth and two-dimensional coordinates (X, Y) to successively stack the two-dimensional images based on the etching depth and the two-dimensional coordinates to generate the three-dimensional image; and
a memory for storing the classified two-dimensional image.
11. The system of claim 1, further comprising a cleaning module for cleaning an etch surface of the wafer.
12. The system of claim 11, further comprising a load lock at which the wafer is on standby, wherein the etch module, the analysis module, and the cleaning module are each coupled to and interconnected with one another by the load lock.
13. The system of claim 1, wherein the analysis module comprises at least one of:
a mass spectrometer; and
an optical emission spectrometer OES device for analyzing byproducts generated during etching of the wafer.
14. A method of analyzing a semiconductor device, the method comprising:
repeatedly etching the entire surface of the wafer to a target depth at the same etch rate to expose a next surface of the wafer;
repeatedly obtaining two-dimensional structural information from each repeatedly etched surface of the wafer; and
the two-dimensional structure information obtained repeatedly is successively stacked to generate a three-dimensional image.
15. The method of claim 14, wherein obtaining the two-dimensional structure information comprises:
obtaining two-dimensional physical information of the wafer; and
two-dimensional electrical information of the wafer is obtained.
16. The method of claim 14:
wherein the two-dimensional structure information obtained repeatedly comprises a two-dimensional image;
wherein repeatedly obtaining the two-dimensional structure information comprises: classifying the two-dimensional image according to a target depth and two-dimensional coordinates (X, Y); and
wherein successively laminating the two-dimensional structure information obtained repeatedly includes: continuously stacking the two-dimensional images based on the target depth and the two-dimensional coordinates.
17. The method of claim 14, further comprising analyzing byproducts generated during the etching of the wafer.
18. The method of claim 17, wherein the amount of the byproduct is analyzed to control the target depth.
19. The method of claim 14, further comprising: cleaning an etched surface of the wafer between repeated etches of the surface of the wafer, and obtaining the two-dimensional structural information.
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