CN112309865A - Lateral diffusion metal oxide semiconductor device and manufacturing method thereof - Google Patents

Lateral diffusion metal oxide semiconductor device and manufacturing method thereof Download PDF

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Publication number
CN112309865A
CN112309865A CN201910706598.9A CN201910706598A CN112309865A CN 112309865 A CN112309865 A CN 112309865A CN 201910706598 A CN201910706598 A CN 201910706598A CN 112309865 A CN112309865 A CN 112309865A
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groove
field plate
substrate
plate dielectric
trench
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CN112309865B (en
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马春霞
林峰
许超奇
孙贵鹏
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CSMC Technologies Fab2 Co Ltd
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CSMC Technologies Fab2 Co Ltd
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Priority to PCT/CN2020/092889 priority patent/WO2021017601A1/en
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Abstract

The invention relates to a lateral diffusion metal oxide semiconductor device and a manufacturing method thereof. The method comprises the following steps: obtaining a substrate with a first groove on the surface; forming an isolation structure; forming field plate dielectric structures on two sides of the first groove, forming a drain region in the substrate, wherein at least part of the drain region is covered by the field plate dielectric structures; forming a source region in the substrate at the middle position of the first trench; and forming a grid on the surface of the field plate dielectric structure, wherein the grid extends downwards to the surface of the substrate at the bottom of the second groove along the field plate dielectric structure. The field plate dielectric structure is formed by etching the isolation structure in the first groove, is compatible with the traditional shallow groove isolation process, does not increase extra field plate forming steps, and has the advantages that a source-drain current path is close to a straight line along the bottom of the first groove when the device is conducted, so that the current path between a source electrode region and a drain electrode region is effectively shortened when the device is conducted, the current crowding problem does not exist, and the on-resistance of the device is reduced.

Description

Lateral diffusion metal oxide semiconductor device and manufacturing method thereof
Technical Field
The present invention relates to the field of semiconductor devices, and in particular, to a method for manufacturing a lateral diffusion metal oxide semiconductor device.
Background
Two key evaluation parameters of LDMOS (laterally diffused metal oxide semiconductor) are breakdown voltage and on-resistance of the device. The traditional LDMOS device adopts LOCOS (local oxidation of silicon isolation) technology or STI (shallow trench isolation) technology to manufacture field oxide on a drift region, a polysilicon gate is expanded to the upper part of the field oxide of the drift region and serves as a field plate, the field oxide manufactured on the drift region and the polysilicon gate field plate jointly play a role of RESURF (reduction of surface electric field), and the breakdown voltage of the device is increased. The LOCOS process is limited by the size of a bird's beak, the length of a drift region of a device is more than or equal to 0.6 micrometer, a source-drain current path is longer when the device is conducted, and the on-resistance of the device is larger; the size of the device of the STI shallow groove structure can be continuously reduced, but when the device is conducted, source-drain current flows along the STI edge under the silicon substrate, the current path is longer, the current crowding problem can occur at the junction of the STI and the silicon substrate and the STI corner, and the on-resistance of the device is larger.
Disclosure of Invention
Therefore, it is necessary to provide a new method for manufacturing a laterally diffused metal oxide semiconductor device and a new laterally diffused metal oxide semiconductor device, which are directed to the problem of the large device size of the field oxide in the LOCOS process and the problems of the long current path, the current crowding and the large on-resistance of the device in the STI shallow trench process.
A method for manufacturing a laterally diffused metal oxide semiconductor device comprises the following steps:
the method comprises the steps of obtaining a substrate, wherein a first groove is formed in the surface of the substrate.
An isolation structure is formed in the first trench.
And removing the isolation structure in the central area of the first groove by etching so as to expose the second groove in the middle area of the first groove, wherein the rest isolation structures comprise isolation structures covering two sides of the first groove and used as field plate dielectric structures.
And forming a drain region in the substrate, wherein one end of the drain region is arranged at a position of the substrate close to the top edge of the first groove and extends obliquely downwards to the substrate structure at the bottom of the first groove, and the drain region is at least partially covered by the field plate dielectric structure.
And forming a source region in the substrate at the middle position of the second trench.
And forming a grid on the surface of the field plate dielectric structure, wherein the grid extends downwards to the surface of the substrate at the bottom of the second groove along the field plate dielectric structure.
In one embodiment, the field plate dielectric structure has a sloped inclined surface.
In one embodiment, the included angle between the inclined surface of the field plate dielectric structure and the horizontal plane is greater than or equal to 30 degrees and less than or equal to 40 degrees, and the thickness of the field plate dielectric structure is less than or equal to 420 nanometers.
In one embodiment, the step of opening the first trench on the surface of the substrate includes:
forming an isolation oxide layer;
depositing to form a nitride protective layer;
photoetching and etching to form a first groove;
wherein, the bottom edge to the top edge of the first groove are of a slope structure.
In one embodiment, the step of forming the isolation structure in the first trench includes:
depositing to form a trench oxide;
etching to remove the nitride protective layer;
and etching to remove the isolation oxide layer.
In one embodiment, the trench oxide is formed by a high density plasma chemical vapor deposition process.
In one embodiment, the gate is 2000 angstroms thick.
The manufacturing method of the transverse diffusion metal oxide semiconductor device removes the isolation structure in the central area of the first groove by etching, exposes the second groove in the middle area of the first groove, and forms the isolation structures covering the two sides of the first groove as a field plate medium structure; one end of the drain electrode region is arranged at a position, close to the top edge of the first groove, of the substrate and extends downwards obliquely to the substrate structure at the bottom of the first groove, a source electrode region is formed in the substrate at the middle position of the second groove, a grid electrode is formed on the surface of the field plate dielectric structure, the grid electrode extends downwards to the substrate surface at the bottom of the second groove along the field plate dielectric structure, the field plate dielectric structure is formed by etching an isolation structure in the first groove, the method is compatible with the traditional shallow groove isolation process, extra field plate forming steps are not added, a source drain current path is close to a straight line along the bottom of the first groove when the device is conducted, the current path between the source electrode region and the drain electrode region is effectively shortened when the device is conducted, the current crowding problem does not exist, and the conduction resistance of the device.
A laterally diffused metal oxide semiconductor device, comprising:
the surface of the substrate is provided with a groove;
and one end of the drain region is arranged at the position of the substrate close to the top edge of the groove and extends downwards obliquely to the substrate structure at the bottom of the groove.
And the field plate dielectric structure covers two sides of the groove and at least part of the drain region at the bottom of the groove.
And the source region is arranged in the substrate at the middle position of the bottom of the groove.
And the grid electrode is arranged on the surface of the field plate dielectric structure and extends out of the field plate dielectric structure downwards to the surface of the substrate at the bottom of the groove.
In one embodiment, the bottom edge to the top edge of the trench is a ramp structure.
In one embodiment, the field plate dielectric structure has a sloped inclined surface.
In one embodiment, the included angle between the inclined surface of the field plate dielectric structure and the horizontal plane is greater than or equal to 30 degrees and less than or equal to 40 degrees, and the thickness of the field plate dielectric structure is less than or equal to 420 nanometers.
The transverse diffusion metal oxide semiconductor device comprises a substrate, wherein a groove is formed in the surface of the substrate; one end of the drain region is arranged at the position of the substrate close to the top edge of the groove and extends downwards obliquely to the substrate structure at the bottom of the groove; the field plate dielectric structure covers two sides of the groove and at least part of the drain region at the bottom of the groove; the source electrode region is arranged in the substrate at the middle position of the bottom of the groove; and the grid electrode is arranged on the surface of the field plate dielectric structure and extends out of the field plate dielectric structure to the surface of the substrate at the bottom of the groove. The grid electrode, the field plate medium structure and the source electrode region are arranged in the groove, the drain electrode region is arranged in the substrate, the device is compatible with the traditional shallow groove isolation process, extra field plate forming steps are not added, a source-drain current path is close to a straight line along the bottom of the groove when the device is conducted, the current path between the source electrode region and the drain electrode region is effectively shortened when the device is conducted, the current crowding problem does not exist, and meanwhile the on-resistance of the device is reduced.
Drawings
FIG. 1 is a flow chart of a method of fabricating a LDMOS device according to an embodiment;
FIG. 2 is a flow chart of forming a first trench in one embodiment;
FIG. 3a is a cross-sectional view of an embodiment of a LDMOS device before a first trench is formed;
FIG. 3b is a cross-sectional view of an LDMOS device after forming a first trench in accordance with an embodiment;
FIG. 4 is a cross-sectional view of an embodiment of a LDMOS device after forming isolation structures;
fig. 5 is a cross-sectional view of a ldmos device after forming a gate in accordance with an embodiment of the present invention.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
As used herein, the term semiconductor is used in the art to distinguish between P-type and N-type impurities, and for example, P + type represents P-type with heavy doping concentration, P-type represents P-type with medium doping concentration, P-type represents P-type with light doping concentration, N + type represents N-type with heavy doping concentration, N-type represents N-type with medium doping concentration, and N-type represents N-type with light doping concentration.
As shown in fig. 1 and 5, the present invention provides a method for manufacturing a laterally diffused metal oxide semiconductor device, comprising:
s102, a substrate is obtained.
The surface of the substrate is provided with a first groove, as shown in fig. 2, and in one embodiment, the step of providing the first groove on the surface of the substrate 100 includes:
s202, forming an isolation oxide layer.
And S204, forming a nitride protective layer.
As shown in fig. 3a, a nitride protection layer 104 is deposited on the isolation oxide layer 102, and then a photoresist coating and an exposure development are performed to form a photoresist layer 106.
And S206, forming a first groove.
As shown in fig. 3a and fig. 3b, the exposed and developed portions without the protection of the photoresist layer are etched to remove the nitride, the oxide and a portion of the substrate, thereby forming a first trench 108, and removing the photoresist layer 106.
Wherein, the bottom edge to the top edge of the first trench 108 is a slope structure with a slope 109.
And S104, forming an isolation structure.
Forming an isolation structure in the first trench; as shown in fig. 4, in one embodiment, the step of forming an isolation structure in the first trench includes:
s302, depositing to form a trench oxide.
First, a trench oxide, such as silicon dioxide, is deposited to fill the first trench. The trench oxide is then planarized, for example by chemical mechanical polishing. In one embodiment, the trench oxide is formed by a high density plasma chemical vapor deposition process.
And S304, etching to remove the nitride protective layer.
And stripping to remove the nitride protection layer on the surface of the substrate.
S306, etching to remove the isolation oxide layer.
And stripping and removing the isolation oxide layer on the surface of the substrate to form an isolation structure.
And S106, forming a field plate dielectric structure.
As shown in fig. 5, the isolation structure in the central region of the first trench is removed by photolithography and etching, so as to expose the second trench in the middle region of the first trench, and the remaining isolation structures include isolation structures covering both sides of the first trench as field plate dielectric structures 110.
The upper surface of the field plate dielectric structure 110 is on the same plane as the substrate 100, and in an actual process, the upper surfaces of the field plate dielectric structures 110 with different widths are reserved according to different requirements on breakdown voltage.
The invention obtains the field plate dielectric structure by etching the original isolation structure in the first groove, thereby reducing the complexity of process integration.
As shown in fig. 5, in one embodiment, the field plate dielectric structure 110 has a sloped inclined surface 111.
In one embodiment, the included angle between the inclined surface of the field plate dielectric structure and the horizontal plane is greater than or equal to 30 degrees and less than or equal to 40 degrees, so that the potential lines at two ends of the drift region are distributed more uniformly, the smoothness degree of the grid electrode is improved, the concentration degree of current under the field plate dielectric structure is reduced, the current characteristic of the device is further improved, and the thickness of the field plate dielectric structure is less than or equal to 420 nanometers.
In one embodiment, the thickness of the field plate dielectric structure is greater than or equal to 380 nm and less than or equal to 420 nm, and the breakdown voltage of the device is greater than 100 volts.
And S108, forming a drain region.
And forming a drain region 112 of the device in the substrate 100 through a photolithography and implantation process, wherein one end of the drain region 112 is arranged at a position of the substrate 100 close to the top edge of the first trench and extends obliquely downward into the substrate structure at the bottom of the first trench, and the drain region is at least partially covered by the field plate dielectric structure 110.
In a practical process, the length of the drain region 112 in the first trench is set according to different requirements for the breakdown voltage of the device. In one embodiment, the drain region is implanted with N-type impurities, and the concentration and depth of the implanted impurities are set according to the specific characteristic requirements of the interval.
And S110, forming a source region.
A source region 114 is formed in the substrate 100 at a central position of the second trench by a photolithography and implantation process. When the device is turned on, current flows from the source region 114 to the drain region 112, and the current path is nearly linear, so that the on-resistance of the device is greatly reduced.
And S112, forming a grid electrode.
Forming a gate 116 on the surface of the field plate dielectric structure 110, wherein the gate 116 extends downwards along the field plate dielectric structure 110 to the surface of the substrate at the bottom of the second trench to reduce the surface electric field of the device, the size of the gate covering the field plate dielectric structure and the drain region affects the on-resistance and breakdown voltage of the device, and different sizes of the gate covering the field plate dielectric structure and the drain region are selected to obtain different device parameters; in one embodiment the gate is a polysilicon gate.
In one embodiment, the gate is 2000 angstroms thick.
In one embodiment, the step of forming the gate further comprises forming a gate oxide layer extending down the field plate dielectric structure to the substrate surface at the bottom of the second trench, wherein in one embodiment, the thickness of the gate oxide layer is 13 nm, and the gate voltage of the device is 5 v.
In one embodiment, the step of forming contact holes, through holes, metal plugs and metal interconnects is further included after the step of forming the gates.
The manufacturing method of the transverse diffusion metal oxide semiconductor device removes the isolation structure in the central area of the first groove by etching, exposes the second groove in the middle area of the first groove, and forms the isolation structures covering the two sides of the first groove as a field plate medium structure; one end of the drain electrode region is arranged at a position, close to the top edge of the first groove, of the substrate and extends downwards obliquely to the substrate structure at the bottom of the first groove, a source electrode region is formed in the substrate at the middle position of the second groove, a grid electrode is formed on the surface of the field plate dielectric structure, the grid electrode extends downwards to the substrate surface at the bottom of the second groove along the field plate dielectric structure, the field plate dielectric structure is formed by etching an isolation structure in the first groove, the method is compatible with the traditional shallow groove isolation process, extra field plate forming steps are not added, a source drain current path is close to a straight line along the bottom of the first groove when the device is conducted, the current path between the source electrode region and the drain electrode region is effectively shortened when the device is conducted, the current crowding problem does not exist, and the conduction resistance of the device.
As shown in fig. 5, the present invention also provides a lateral diffused metal oxide semiconductor device, comprising:
the substrate 100, the substrate 100 surface has a trench.
One end of the drain region 112 is disposed on the substrate 100 near the top edge of the trench, and extends obliquely downward into the substrate structure at the bottom of the trench.
The field plate dielectric structure 110 covers both sides of the trench and at least a portion of the drain region 112 at the bottom of the trench.
And a source region 114 disposed in the substrate 100 at a middle position of the bottom of the trench.
And the grid electrode 116 is arranged on the surface of the field plate dielectric structure 110 and extends out of the field plate dielectric structure 116 to the substrate surface at the bottom of the groove.
In one embodiment, the bottom edge to the top edge of the trench is a ramp structure with a ramp 109.
As shown in fig. 5, in one embodiment, the field plate dielectric structure 110 has a sloped inclined surface 111.
In one embodiment, the included angle between the inclined surface of the field plate dielectric structure and the horizontal plane is greater than or equal to 30 degrees and less than or equal to 40 degrees, so that the potential lines at two ends of the drift region are distributed more uniformly, the smoothness degree of the grid electrode is improved, the concentration degree of current under the field plate dielectric structure is reduced, and the current characteristic of the device is further improved, wherein the thickness of the field plate dielectric structure is less than or equal to 420 nanometers.
In one embodiment, the thickness of the field plate dielectric structure is greater than or equal to 380 nm and less than or equal to 420 nm, and the breakdown voltage of the device is greater than 100 volts.
In one embodiment, the laterally diffused metal oxide semiconductor device further comprises a gate oxide extending down the field plate dielectric structure to the substrate surface at the bottom of the second trench.
In one embodiment, the laterally diffused metal oxide semiconductor device further comprises a contact hole, a through hole, a metal plug and a metal interconnection layer.
The transverse diffusion metal oxide semiconductor device comprises a substrate, wherein a groove is formed in the surface of the substrate; one end of the drain region is arranged at the position of the substrate close to the top edge of the groove and extends downwards obliquely to the substrate structure at the bottom of the groove; the field plate dielectric structure covers two sides of the groove and at least part of the drain region at the bottom of the groove; the source electrode region is arranged in the substrate at the middle position of the bottom of the groove; and the grid electrode is arranged on the surface of the field plate dielectric structure and extends out of the field plate dielectric structure to the surface of the substrate at the bottom of the groove. The grid electrode, the field plate medium structure and the source electrode region are arranged in the groove, the drain electrode region is arranged in the substrate, the device is compatible with the traditional shallow groove isolation process, extra field plate forming steps are not added, a source-drain current path is close to a straight line along the bottom of the groove when the device is conducted, the current path between the source electrode region and the drain electrode region is effectively shortened when the device is conducted, the current crowding problem does not exist, and meanwhile the on-resistance of the device is reduced.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (10)

1. A method for manufacturing a laterally diffused metal oxide semiconductor device comprises the following steps:
obtaining a substrate, wherein a first groove is formed in the surface of the substrate;
forming an isolation structure in the first trench;
removing the isolation structure in the central area of the first groove by etching, thereby exposing the second groove in the middle area of the first groove, wherein the rest isolation structures comprise isolation structures covering two sides of the first groove and used as field plate dielectric structures;
forming a drain region in the substrate, wherein one end of the drain region is arranged at a position of the substrate close to the top edge of the first trench and extends obliquely downwards to the substrate structure at the bottom of the first trench, and the drain region is at least partially covered by the field plate dielectric structure;
forming a source region in the substrate at the middle position of the second trench;
and forming a grid on the surface of the field plate dielectric structure, wherein the grid extends downwards to the surface of the substrate at the bottom of the second groove along the field plate dielectric structure.
2. The method of manufacturing of claim 1, wherein the field plate dielectric structure has a sloped inclined surface.
3. The manufacturing method of claim 2, wherein an included angle between the inclined surface of the field plate dielectric structure and a horizontal plane is greater than or equal to 30 degrees and less than or equal to 40 degrees, and the thickness of the field plate dielectric structure is less than or equal to 420 nanometers.
4. The method of manufacturing according to claim 1, wherein the step of opening the first trench in the surface of the substrate comprises:
forming an isolation oxide layer;
depositing to form a nitride protective layer;
photoetching and etching to form the first groove;
wherein, the bottom edge to the top edge of the first groove are of a slope structure.
5. The method of manufacturing of claim 4, wherein the step of forming an isolation structure in the first trench comprises:
depositing to form a trench oxide;
etching to remove the nitride protective layer;
and etching to remove the isolation oxide layer.
6. The method of manufacturing of claim 5, wherein the trench oxide is formed by a high density plasma chemical vapor deposition process.
7. A laterally diffused metal oxide semiconductor device, comprising:
the surface of the substrate is provided with a groove;
one end of the drain electrode region is arranged at the position, close to the top edge of the groove, of the substrate, and extends downwards obliquely to the substrate structure at the bottom of the groove;
the field plate dielectric structure covers two sides of the groove and at least part of the drain region at the bottom of the groove;
the source electrode region is arranged in the substrate at the middle position of the bottom of the groove;
and the grid electrode is arranged on the surface of the field plate dielectric structure and extends downwards to the surface of the substrate at the bottom of the groove.
8. The device of claim 7, wherein a bottom edge to a top edge of the trench is a sloped structure.
9. The device of claim 7, wherein the field plate dielectric structure has a sloped inclined surface.
10. The device of claim 9, wherein the angle between the inclined surface of the field plate dielectric structure and the horizontal plane is greater than or equal to 30 degrees and less than or equal to 40 degrees, and the thickness of the field plate dielectric structure is less than or equal to 420 nanometers.
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