CN112307710B - Direct current voltage drop analysis method and system of system-level integrated circuit - Google Patents
Direct current voltage drop analysis method and system of system-level integrated circuit Download PDFInfo
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Abstract
The invention discloses a direct current voltage drop analysis method and a direct current voltage drop analysis system of a system-level integrated circuit, wherein the method comprises the steps of firstly dividing the system-level integrated circuit into a plurality of subsystems, and when the mth subsystem is analyzed, regarding all the subsystems except the mth subsystem as a system to be processed; performing mesh division on a field of each subsystem, adding points, connected with the field, of through holes of external circuits of the subsystems and other subsystems into mesh division nodes, and uniformly numbering the mesh division nodes to form a uniform finite element sparse matrix; the method adopts a star-triangle transformation method to eliminate the internal nodes of the system to be processed in the finite element sparse matrix, obtains a sparse matrix for analyzing the m subsystem field, and solves the sparse matrix of the m subsystem field rather than the whole system field, thereby greatly simplifying the solving process, improving the solving speed on the basis of ensuring the solving precision and realizing the rapid and accurate analysis of the direct current voltage drop of the system-level super-large scale integrated circuit.
Description
Technical Field
The invention relates to the technical field of system-level integrated circuit analysis, in particular to a direct current voltage drop analysis method and system of a system-level integrated circuit.
Background
The direct current voltage drop analysis of the system-level ultra-large scale integrated circuit is an important work for verifying the back end of the integrated circuit. In the design process of the current system-level ultra-large scale integrated circuit, the core supply voltage of devices in the integrated circuit is continuously reduced, the tolerance of the allowed voltage is smaller and smaller, but the working current and the wiring density of the integrated circuit are larger and larger, so that the problem of direct current voltage drop is more and more prominent. If the problem of direct current voltage drop is not considered in the design process of a system-level very large scale integrated circuit, the noise margin of the system is likely to be reduced due to the problem of direct current voltage drop, and the system cannot work normally due to small disturbance. In addition, excessive current density in a local area can cause the temperature in the area to continuously rise, and finally cause the whole system to be damaged. Therefore, during the design process of the system-level vlsi, the dc drop analysis should be performed on the power distribution network of the whole system to ensure that the dc drop and the current density distribution of the whole system are within the preset tolerance range.
At present, a common analysis method for the direct current voltage drop of an integrated circuit adopts an electromagnetic field numerical calculation method such as a finite element method for analysis, and the basic idea is to disperse an area where a whole system-level super-large-scale integrated circuit is located to form a discrete grid unit, approximate a Maxwell equation describing an electromagnetic field in the grid unit to form an equation set aiming at the discrete grid unit, and solve the equation set to obtain a discrete solution of the field quantity to be analyzed. However, in the development process of a system-level very large scale integrated circuit, the integration level of components in the integrated circuit is higher and higher, and the scale range of the components is larger and larger, that is, the multi-scale structure features are more and more obvious, the overall size reaches the centimeter level, and the sizes of dense routing, gaps and via holes reach the nanometer level. Aiming at the system-level super-large scale integrated circuit with the multi-scale structure, high-quality mesh subdivision is carried out on the region where the whole system-level super-large scale integrated circuit is located, the number of generated mesh subdivision nodes can reach the magnitude of tens of millions or even hundreds of millions, the problem of directly solving a finite element sparse matrix with unknown quantity of tens of millions or even hundreds of millions formed by the mesh is difficult, even if the finite element sparse matrix can be solved, huge memory and CPU time are needed, and for the design of the system-level super-large scale integrated circuit, the time cost is too large, so how to provide a solving method with high precision and high speed is to rapidly and accurately analyze the direct current voltage drop of the system-level super-large scale integrated circuit becomes a technical problem to be solved urgently.
Disclosure of Invention
The invention aims to provide a direct current voltage drop analysis method and a direct current voltage drop analysis system for a system-level integrated circuit, so as to realize rapid and accurate analysis of the direct current voltage drop of the system-level super-large-scale integrated circuit.
In order to achieve the purpose, the invention provides the following scheme:
a method for analyzing dc drop of a system-in-a-line integrated circuit, the method comprising the steps of:
acquiring a multilayer integrated circuit layout of a system-level integrated circuit;
performing mesh generation on each layer of integrated circuit layout in the multilayer integrated circuit layout, and inserting a connection point of an external circuit and each layer of integrated circuit layout and a connection point of a via hole between different layers of integrated circuit layout and each layer of integrated circuit layout into a mesh to form a mesh generation node;
dividing the system level integrated circuit into a plurality of subsystems in units of layers;
sequentially numbering the mesh division nodes of each subsystem, and writing a finite element equation set for direct-current voltage drop analysis according to the information columns of each mesh division node to obtain a finite element sparse matrix;
when the direct current pressure drop of the mth subsystem is analyzed, all subsystems except the mth subsystem in the multiple subsystems are synthesized into a system to be processed;
eliminating internal nodes of a system to be processed in the finite element sparse matrix by adopting a star-triangle transformation method to obtain a sparse matrix for analyzing the mth subsystem field;
and solving and analyzing the sparse matrix of the mth subsystem field to obtain the direct current voltage drop and the current density distribution on the mth subsystem field.
Optionally, the eliminating, by using a star-triangle transformation method, internal nodes of the system to be processed in the finite element sparse matrix to obtain a sparse matrix for analyzing the mth subsystem field includes:
the finite element sparse matrix is equivalent to a sparse matrix of an admittance network which takes a finite element grid as association;
and repeatedly carrying out star-triangle transformation on the sparse matrix of the admittance network to eliminate the internal nodes of the system to be processed, and obtaining a sparse matrix for analyzing the mth subsystem field.
Optionally, the equivalent of the finite element sparse matrix to a sparse matrix of an admittance network using a finite element mesh as a correlation specifically includes:
using formulas
The finite element sparse matrix is equivalent to a sparse matrix of an admittance network which takes a finite element grid as association;
wherein u is the node voltage, b is the right end term, and is essentially current source excitation, and A is the admittance matrix of the finite element mesh subdivision node.
Optionally, the repeatedly performing star-triangle transformation on the sparse matrix of the admittance network to eliminate the internal nodes of the system to be processed specifically includes:
formula for recycling sparse matrix of admittance network
Performing a star-triangle transformation to eliminate internal nodes of the system to be processed;
wherein the content of the first and second substances,
for the second associated with admittance network node to be cancelled in admittance networkiThe mutual admittance of the individual admittance network nodes and the admittance network node to be cancelled,
for the second associated with admittance network node to be cancelled in admittance networkjThe mutual admittance of the individual admittance network nodes and the admittance network node to be cancelled,
for association with admittance network nodes to be cancellediAn admittance network node and a second associated with the admittance network node to be cancelledjMutual admittance of individual admittance network nodes, corresponding to sparse matrix non-diagonal elementsiLine and firstjThe elements of the column are,
for the kth admittance network associated with admittance network nodes to be cancelled in the admittance networkThe mutual admittance of the network node and the admittance network node to be cancelled,pis the number of admittance network nodes associated with the admittance network node to be cancelled.
A system-in-a-system integrated circuit dc-drop analysis system, the analysis system comprising:
the multilayer integrated circuit layout acquisition module is used for acquiring a multilayer integrated circuit layout of the system-level integrated circuit;
the grid subdivision module is used for carrying out grid subdivision on each layer of integrated circuit layout in the multilayer integrated circuit layout, inserting a connection point of an external circuit and each layer of integrated circuit layout and a connection point of a via hole between different layers of integrated circuit layout and each layer of integrated circuit layout into a grid to form a grid subdivision node;
a subsystem division module for dividing the system-level integrated circuit into a plurality of subsystems in units of layers;
the finite element sparse matrix establishing module is used for numbering the grid division nodes of each subsystem in sequence, writing a finite element equation set for direct current voltage drop analysis according to the information column of each grid division node, and obtaining a finite element sparse matrix;
the system to be processed synthesis module is used for synthesizing all subsystems except the mth subsystem into a system to be processed when analyzing the direct current voltage drop of the mth subsystem;
the star-triangle transformation module is used for eliminating internal nodes of the system to be processed in the finite element sparse matrix by adopting a star-triangle transformation method to obtain a sparse matrix for analyzing the mth subsystem field;
and the solving module is used for solving and analyzing the sparse matrix of the mth subsystem field to obtain the direct current voltage drop and the current density distribution on the mth subsystem field.
Optionally, the star-triangle transformation module specifically includes:
the admittance network equivalent submodule is used for equivalent the finite element sparse matrix into a sparse matrix of an admittance network which takes a finite element grid as association;
and the internal node elimination submodule is used for repeatedly carrying out star-triangle transformation on the sparse matrix of the admittance network to eliminate the internal nodes of the system to be processed.
Optionally, the admittance matrix equivalent sub-module specifically includes:
admittance network equivalent unit for using formula
The finite element sparse matrix is equivalent to a sparse matrix of an admittance network which takes a finite element grid as association;
wherein u is the node voltage, b is the right end term, and is essentially current source excitation, and A is the admittance matrix of the finite element mesh subdivision node.
Optionally, the internal node elimination submodule specifically includes:
an internal node elimination unit for reusing the sparse matrix of the admittance network
Performing a star-triangle transformation to eliminate internal nodes of the system to be processed;
wherein the content of the first and second substances,
for the second associated with admittance network node to be cancelled in admittance networkiThe mutual admittance of the individual admittance network nodes and the admittance network node to be cancelled,
for the second associated with admittance network node to be cancelled in admittance networkjThe mutual admittance of the individual admittance network nodes and the admittance network node to be cancelled,
for association with admittance network nodes to be cancellediAn admittance network node and a second associated with the admittance network node to be cancelledjMutual admittance of individual admittance network nodes, corresponding to sparse matrix non-diagonal elementsiLine and firstjThe elements of the column are,
for the mutual admittance of the kth admittance network node associated with the admittance network node to be cancelled and the admittance network node to be cancelled in the admittance network,pis the number of admittance network nodes associated with the admittance network node to be cancelled.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
the invention discloses a direct current voltage drop analysis method of a system-level integrated circuit, which comprises the following steps: acquiring a multilayer integrated circuit layout of a system-level integrated circuit; performing mesh generation on each layer of integrated circuit layout in the multilayer integrated circuit layout, and inserting a connection point of an external circuit and each layer of integrated circuit layout and a connection point of a via hole between different layers of integrated circuit layout and each layer of integrated circuit layout into a mesh to form a mesh generation node; dividing the system level integrated circuit into a plurality of subsystems in units of layers; sequentially numbering the mesh division nodes of each subsystem, and writing a finite element equation set for direct-current voltage drop analysis according to the information columns of each mesh division node to obtain a finite element sparse matrix; when the direct current pressure drop of the mth subsystem is analyzed, all subsystems except the mth subsystem in the multiple subsystems are synthesized into a system to be processed; eliminating internal nodes of a system to be processed in the finite element sparse matrix by adopting a star-triangle transformation method to obtain a sparse matrix for analyzing the mth subsystem field; and solving and analyzing the sparse matrix of the mth subsystem field to obtain the direct current voltage drop and the current density distribution on the mth subsystem field. The system level integrated circuit is divided into a plurality of subsystems, when the mth subsystem is analyzed, all subsystems except the mth subsystem are regarded as a system to be processed, internal nodes of the system to be processed in a finite element sparse matrix are eliminated by adopting a star-triangle transformation method, a sparse matrix for analyzing the mth subsystem field is obtained, only the sparse matrix of the mth subsystem but not the whole system field is solved, the solving process is greatly simplified, the solving speed is improved on the basis of ensuring the solving precision, and the direct current voltage drop of the system level super large scale integrated circuit is quickly and accurately analyzed.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without inventive exercise.
FIG. 1 is a flow chart of a DC drop analysis method for a system-on-a-chip integrated circuit according to the present invention;
FIG. 2 is a schematic diagram of a split subsystem provided in the present invention;
FIG. 3 is a schematic diagram of a system-level integrated circuit two-dimensional layout triangle mesh subdivision and its port definition provided by the embodiment of the present invention;
FIG. 4 is a schematic diagram of an equivalent admittance network of a finite element stiffness matrix according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a star-to-triangle transformation provided by an embodiment of the present invention;
fig. 6 is a schematic diagram of an internal node elimination process of a finite element sparse matrix according to an embodiment of the present invention.
Detailed Description
The invention aims to provide a direct current voltage drop analysis method and a direct current voltage drop analysis system for a system-level integrated circuit, so as to realize rapid and accurate analysis of the direct current voltage drop of the system-level super-large-scale integrated circuit.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
In order to solve the problems, the invention provides a direct current voltage drop analysis method of a system-level super-large scale integrated circuit, which is a method for rapidly and accurately analyzing the direct current voltage drop of the system-level super-large scale integrated circuit by combining star-triangle transformation, the method also carries out mesh subdivision aiming at a complex integrated circuit layout of a multi-scale structure with the scale range of centimeter to nanometer, a finite element rigidity matrix is listed and written by adopting a finite element method based on the field problem, but after a finite element sparse matrix is formed, the unknown sparse finite element matrix is not directly solved, but a plurality of PCB boards and a plurality of packages of the system-level super-large scale integrated circuit, and each PCB board and package are provided with a plurality of power supply layers and signal layers, the whole system-level super-large scale integrated circuit is divided into a plurality of subsystems by taking the PCB boards or the package layers as units, all subsystems are connected through ports such as via holes, external circuits and the like, then, each subsystem is solved in sequence, when a certain subsystem is solved, a finite element grid outside the subsystem and a sparse matrix corresponding to the external circuits repeatedly utilize star-delta transformation of the admittance network to eliminate internal nodes except the port connected with the subsystem, other subsystems except the currently solved subsystem are equivalent to the admittance matrix formed by the port connected with the subsystem to replace the part corresponding to each subsystem in the overall sparse matrix, finally, the original sparse matrix is equivalent to the finite element sparse matrix part of the currently solved subsystem and the port admittance matrices of other subsystems, the unknown quantity of the unknown quantity can be reduced to hundreds of thousands of magnitude order, the sparse matrix is directly solved, and the unknown quantity values of the currently solved subsystem can be obtained, the solved unknown quantity is applied to the currently solved subsystem, so that the field distribution, such as the potential field distribution, of the currently solved subsystem can be obtained, and the direct current voltage drop and the current density distribution of the currently solved subsystem can be further analyzed. Since this star-to-triangle transformation is a strict equivalence, this equivalence does not affect the accuracy of the dc-drop and current density analysis. And repeatedly operating all the rest subsystems according to the method, namely analyzing the direct current voltage drop and the current density of all the subsystems one by one.
Referring to fig. 1, the present invention provides a method for analyzing dc voltage drop of a system-on-a-chip integrated circuit, the method comprising the following steps:
102, performing mesh subdivision on each layer of integrated circuit layout in the multilayer integrated circuit layout, and inserting a connection point of an external circuit and each layer of integrated circuit layout and a connection point of a via hole between different layers of integrated circuit layout and each layer of integrated circuit layout into a mesh to form a mesh subdivision node;
Because the system-level very large scale integrated circuit comprises a plurality of PCBs, a plurality of packages, and each PCB and each package are provided with a plurality of power supply layers and signal layers, the whole system-level very large scale integrated circuit can be split into a plurality of subsystems by taking the layer as a unit, and each subsystem is electrically connected with other subsystems through external circuits, through holes and the like to form the whole system-level very large scale integrated circuit. As shown in fig. 2, the whole system-level vlsi is divided into M subsystems in units of layers, each subsystem includes a region (referred to as a field region) to be analyzed for dc voltage drop and current density, an external circuit, and a via hole connecting the calculation region to other calculation regions. And carrying out mesh division on the corresponding field in each subsystem, wherein external circuits and points of the field, which are connected with the field, of the through holes between the field and other fields form mesh division nodes, and the mesh division nodes which are connected with the external circuits and the through holes between the field and other fields form external connection ports of the field of the subsystem.
And step 104, sequentially numbering the mesh division nodes of each subsystem, writing a finite element equation set for direct current voltage drop analysis according to the information column of each mesh division node, and obtaining a finite element sparse matrix.
For the direct current field model, the three-dimensional model of the multilayer integrated circuit refers to the conductivity in the direct current field model
Potential of the electrode
The distribution of (a) is a function of the three-dimensional spatial coordinates (x, y, z), i.e.:
，
which satisfies the following equation (1):
and boundary condition (2):
in the formula (2), the reaction mixture is,
is a boundary of the first type and is,nis normal to the boundary of the second type,
is an electric potential
At the first kind boundary
Value of above, using
It is shown that,
is the bulk current density of the external circuit.
The dimension of an actual PCB or a chip packaged board in the multilayer ultra-large scale integrated circuit is far larger than the thickness of the metal layer, and the three-dimensional direct current field problem of the multilayer integrated circuit is simplified into a two-dimensional direct current field problem.
The field solving equation set established by the finite element method for the direct current electric field two-dimensional model of each layer of integrated circuit is an equation set (3):
in the formula (I), theI(u)In order to be a functional function,his the thickness of the metal layer or layers,
is the conductivity of grid cell e;
a potential vector of a node which is a grid cell e;
is the face of the grid cell e and,
as the density of the surface current, the current density,
representing the edges of grid cell e. And (4) taking an extreme value of the equation set (3), namely forming a finite element sparse matrix for solving the potential field.
Step 104 specifically includes: and uniformly numbering the grid split nodes and external circuit nodes of the whole system-level super-large scale integrated circuit, and writing a finite element equation set of the whole system-level super-large scale integrated circuit in a row mode to form a uniform finite element sparse matrix.
Assume uniform numbering rules of grid split nodes and external circuit nodes of the whole system-level VLSI are as follows:
numbering according to the sequence of the subsystems, namely, the total number of the subsystem in the sequence is before, and the total number of the subsystem in the sequence is after;
the same subsystem firstly numbers the ports interconnected with other subsystems in the external connection ports, and if the ports are numbered by the small subsystems, the ports directly reference the numbers; numbering external circuit node numbers in the external connection ports; and finally numbering mesh subdivision node numbers.
As shown in fig. 2, it is assumed that this system is split into 3 subsystems, that is, M in fig. 2 has a value of 3, and a subsystem 1 includes 100 nodes, where 10 external connection ports are provided, and there are 4 ports of the 10 ports connected to the subsystem 2 and 6 ports connected to the subsystem 3; the subsystem 2 comprises 200 nodes, wherein 20 external connection ports are provided, 4 ports of the 20 ports are connected with the subsystem 1, 5 ports are connected with the subsystem 3, and the remaining 11 ports are external circuit ports; the subsystem 3 comprises 300 nodes, wherein 16 external connection ports are provided, 6 ports of the 16 ports are connected with the subsystem 1, 5 ports are connected with the subsystem 2, and the remaining 5 ports are external circuit ports. The number of nodes corresponding to the finite element sparse matrix of the entire system is 100+200+300-4 ( ports connecting subsystems 1 and 2 are counted 2 times) -6 ( ports connecting subsystems 1 and 3 are counted 2 times) -5 ( ports connecting subsystems 2 and 3 are counted 2 times) = 585.
According to the unified numbering rule, the unified numbering of the grid split nodes and the external circuit nodes of the whole system-level ultra-large scale integrated circuit is as follows:
subsystem 1:
1-4 (serial numbers of interconnection ports of the subsystem 1 and the subsystem 2);
5-10 (serial numbers of interconnection ports of the subsystem 1 and the subsystem 3);
11-100 (subsystem 1 mesh division node number).
And (3) subsystem 2:
1-4 (serial numbers of the interconnection ports of the subsystem 2 and the subsystem 1);
101-105 (serial numbers of interconnection ports of the subsystem 2 and the subsystem 3);
106-116 (number of circuit nodes outside the subsystem 2);
117-196 (subsystem 2 mesh division node number).
Subsystem 3:
5-10 (serial numbers of the interconnection ports of the subsystem 3 and the subsystem 1);
101-105 (serial numbers of interconnection ports of the subsystem 3 and the subsystem 2);
197-201 (subsystem 3 external circuit node number);
202-585 (subsystem 3 mesh division node number).
And splitting the whole system-level super-large-scale integrated circuit into a plurality of subsystems by taking the layer as a unit, and marking the subsystems to which the nodes corresponding to the finite element sparse matrix unified by the whole system-level super-large-scale integrated circuit belong. If a node is an external connection port of a subsystem field, the node belongs to at least 2 subsystems simultaneously.
The subsystem to which the node corresponding to the finite element sparse matrix unified by the whole system-level very large scale integrated circuit belongs is as follows:
1-4: belongs to a subsystem 1 and a subsystem 2;
5-10: belongs to a subsystem 1 and a subsystem 3;
11-100: belongs to the subsystem 1;
101-105: belongs to a subsystem 2 and a subsystem 3;
106 to 116: belongs to the subsystem 2;
117-196: belongs to the subsystem 2;
197 to 201: belongs to the subsystem 3;
202-585: belongs to the subsystem 3;
106, eliminating internal nodes of a system to be processed in the finite element sparse matrix by adopting a star-triangle transformation method to obtain a sparse matrix for analyzing the mth subsystem field;
106, eliminating internal nodes of the system to be processed in the finite element sparse matrix by adopting a star-triangle transformation method to obtain a sparse matrix for analyzing the mth subsystem field, specifically comprising: the finite element sparse matrix is equivalent to a sparse matrix of an admittance network which takes a finite element grid as association; and repeatedly carrying out star-triangle transformation on the sparse matrix of the admittance network to eliminate the internal nodes of the system to be processed, and obtaining a sparse matrix for analyzing the mth subsystem field.
Wherein, the equivalence of the finite element sparse matrix into a sparse matrix of an admittance network using a finite element mesh as a correlation specifically includes: using formulas
The finite element sparse matrix is equivalent to a sparse matrix of an admittance network which takes a finite element grid as association; wherein u is the node voltage, b is the right end term, and is essentially current source excitation, and A is the admittance matrix of the finite element mesh subdivision node.
Wherein, repeatedly performing star-triangle transformation on the sparse matrix of the admittance network to eliminate the internal nodes of the system to be processed specifically comprises: formula for recycling sparse matrix of admittance network
Performing a star-triangle transformation to eliminate internal nodes of the system to be processed; wherein the content of the first and second substances,
for the second associated with admittance network node to be cancelled in admittance networkiThe mutual admittance of the individual admittance network nodes and the admittance network node to be cancelled,
for the second associated with admittance network node to be cancelled in admittance networkjMutual admittance of individual admittance network nodes and admittance network nodes to be cancelled，
For association with admittance network nodes to be cancellediAn admittance network node and a second associated with the admittance network node to be cancelledjMutual admittance of individual admittance network nodes, corresponding to sparse matrix non-diagonal elementsiLine and firstjThe elements of the column are,
for the mutual admittance of the kth admittance network node associated with the admittance network node to be cancelled and the admittance network node to be cancelled in the admittance network,pis the number of admittance network nodes associated with the admittance network node to be cancelled.
As a specific embodiment, as shown in fig. 3, a schematic diagram of a triangular mesh subdivision of a two-dimensional layout of a system to be processed is shown. As shown in fig. 3, the whole layout is divided into 8 triangular meshes and 9 mesh division nodes, where the nodes 1, 3, and 8 are port network nodes connected to the subsystem to be analyzed.
For the mesh subdivision shown in FIG. 3, the sparse matrix corresponding to the finite element equation set is formed as
Thus, this finite element sparse matrix equivalent admittance network is shown in fig. 3.
The nodes in fig. 4 correspond to the unknowns of the finite element matrix, and the transadmittance between the i and j nodes corresponds to the ith row and jth column elements of the non-diagonal elements of the sparse matrix. And the self-admittance of node i is the sum of the mutual admittances associated with all nodes i.
Since the ports connected to the subsystems to be analyzed are 1, 3, 8, the final objective is to extract the impedance network model corresponding to the ports 1, 3, 8. The equivalent admittance network shown in fig. 3 needs to be subjected to an iterative star-triangle transformation to eliminate non-port nodes.
Fig. 5 is a 3-port star-triangle conversion diagram, fig. 5 (a) is a star structure diagram, and fig. 5 (b) is a triangle structure diagram. The corresponding star-to-triangle transformation formula of fig. 5 is:
by equation (4), the internal node 4 may be eliminated.
The 3-port star-delta transform can be generalized to N-ports: assuming that there are N +1 nodes in the admittance circuit, and node N +1 is connected to all nodes 1,2, …, N, the N-port star-triangle transformation formula is:
based on the thought and the transformation method, the internal nodes of the non-ports of the finite element sparse matrix can be eliminated, and finally the admittance network of the ports is formed.
Fig. 6 is a schematic diagram of an internal node elimination process of a sparse matrix of an admittance network, and as shown in fig. 6, the internal node elimination process of the sparse matrix of the admittance network specifically includes:
(1) as shown in fig. 6 (a), the node 7 and the node 9 in fig. 4 are eliminated by the series-parallel relationship of the resistances:
and
。
(2) as shown in (b) of fig. 6, by star-to-triangle conversion
Cancel node 5, obtain
。
（3）As shown in (c) of fig. 6, using the formula
，
，
，
Admittance merging for the parallel branch in (b) of fig. 6.
(4) As shown in fig. 6 (d), the process of eliminating the nodes 4, 6, 2 is the same as the process of eliminating the node 5, and finally a 3-port admittance matrix is formed.
(5) Finally, the admittance matrix for ports 1, 3, 8 is formed as follows:
in the above-mentioned formula, the compound of formula,
representing sparse matrix elements between nodes 2,4
As a result of the 3 rd elimination,
representing sparse matrix elements between nodes 4,7
The negative first power of (1), and the others are similar.
Finding out nodes corresponding to a finite element sparse matrix unified by the whole system-level super large scale integrated circuit from the mth subsystem, marking the nodes as internal nodes, and eliminating the internal nodes by repeatedly utilizing a star-triangle transformation method to form a sparse matrix for analyzing the mth subsystem field;
supposing that the 1 st subsystem is processed at present, nodes corresponding to a finite element sparse matrix unified by the whole system-level very large scale integrated circuit do not belong to the 1 st subsystem are 101-585, the nodes are marked as internal nodes when the 1 st subsystem is processed, the internal nodes are eliminated by repeatedly utilizing a star-triangle transformation method, a finite element sparse matrix only containing the 1 st subsystem field and an admittance matrix of a system to be processed are formed, after elimination, the dimension of the whole sparse matrix is reduced to 100 from the original 585, and the time for solving a sparse matrix equation set is greatly reduced.
And 107, solving and analyzing the sparse matrix of the mth subsystem field to obtain the direct current voltage drop and the current density distribution on the mth subsystem field.
Step 107 specifically includes: solving the sparse matrix of the mth subsystem field to obtain the discrete field distribution, such as discrete electric potential field distribution, on the mth subsystem field; the dc voltage drop and current density distribution over the mth subsystem field are obtained based on this discrete potential field distribution.
The present invention also provides a system-in-a-circuit dc drop analysis system, the analysis system comprising:
and the multilayer integrated circuit layout acquisition module is used for acquiring the multilayer integrated circuit layout of the system-level integrated circuit.
And the mesh generation module is used for carrying out mesh generation on each layer of integrated circuit layout in the multilayer integrated circuit layout, and inserting the connection point of an external circuit and each layer of integrated circuit layout and the connection point of a via hole between different layers and each layer of integrated circuit layout into a mesh to form a mesh generation node.
And the subsystem division module is used for dividing the system-level integrated circuit into a plurality of subsystems by taking a layer as a unit.
And the finite element sparse matrix establishing module is used for numbering the grid division nodes of each subsystem in sequence, writing a finite element equation set for direct current voltage drop analysis according to the information column of each grid division node, and obtaining a finite element sparse matrix.
And the system-to-be-processed synthesizing module is used for synthesizing all subsystems except the mth subsystem into the system-to-be-processed when analyzing the direct current voltage drop of the mth subsystem.
And the star-triangle transformation module is used for eliminating the internal nodes of the system to be processed in the finite element sparse matrix by adopting a star-triangle transformation method to obtain a sparse matrix for analyzing the mth subsystem field.
The star-triangle conversion module specifically comprises: the admittance network equivalent submodule is used for equivalent the finite element sparse matrix into a sparse matrix of an admittance network which takes a finite element grid as association; and the internal node elimination submodule is used for repeatedly carrying out star-triangle transformation on the sparse matrix of the admittance network to eliminate the internal nodes of the system to be processed.
The admittance network equivalent submodule specifically comprises: admittance network equivalent unit for using formula
The finite element sparse matrix is equivalent to a sparse matrix of an admittance network which takes a finite element grid as association; wherein u is the node voltage, b is the right end term, and is essentially current source excitation, and A is the admittance matrix of the finite element mesh subdivision node.
The internal node elimination submodule specifically includes: an internal node elimination unit for reusing the sparse matrix of the admittance network
Performing a star-triangle transformation to eliminate internal nodes of the system to be processed;
wherein the content of the first and second substances,
for the second associated with admittance network node to be cancelled in admittance networkiThe mutual admittance of the individual admittance network nodes and the admittance network node to be cancelled,
for the second associated with admittance network node to be cancelled in admittance networkjThe mutual admittance of the individual admittance network nodes and the admittance network node to be cancelled,
for association with admittance network nodes to be cancellediAn admittance network node and a second associated with the admittance network node to be cancelledjMutual admittance of individual admittance network nodes, corresponding to sparse matrix non-diagonal elementsiLine and firstjThe elements of the column are,
for the mutual admittance of the kth admittance network node associated with the admittance network node to be cancelled and the admittance network node to be cancelled in the admittance network,pis the number of admittance network nodes associated with the admittance network node to be cancelled.
And the solving module is used for solving and analyzing the sparse matrix of the mth subsystem field to obtain the direct current voltage drop and the current density distribution on the mth subsystem field.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
the invention discloses a direct current voltage drop analysis method of a system-level integrated circuit, which comprises the following steps: acquiring a multilayer integrated circuit layout of a system-level integrated circuit; performing mesh generation on each layer of integrated circuit layout in the multilayer integrated circuit layout, and inserting a connection point of an external circuit and each layer of integrated circuit layout and a connection point of a via hole between different layers of integrated circuit layout and each layer of integrated circuit layout into a mesh to form a mesh generation node; writing a finite element equation set for direct-current voltage drop analysis according to the information column of each mesh division node to obtain a finite element sparse matrix; dividing the system level integrated circuit into a plurality of subsystems in units of layers; when the direct current pressure drop of the mth subsystem is analyzed, all subsystems except the mth subsystem in the multiple subsystems are synthesized into a system to be processed; eliminating internal nodes of a system to be processed in the finite element sparse matrix by adopting a star-triangle transformation method to obtain a sparse matrix for analyzing the mth subsystem field; and solving and analyzing the sparse matrix of the mth subsystem field to obtain the direct current voltage drop and the current density distribution on the mth subsystem field. The system level integrated circuit is divided into a plurality of subsystems, when the mth subsystem is analyzed, all subsystems except the mth subsystem are regarded as a system to be processed, internal nodes of the system to be processed in a finite element sparse matrix are eliminated by adopting a star-triangle transformation method, a sparse matrix for analyzing the mth subsystem field is obtained, only the sparse matrix of the mth subsystem but not the whole system field is solved, the solving process is greatly simplified, the solving speed is improved on the basis of ensuring the solving precision, and the direct current voltage drop of the system level super large scale integrated circuit is quickly and accurately analyzed.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The principle and the implementation manner of the present invention are explained by applying specific examples, the above description of the embodiments is only used to help understanding the method of the present invention and the core idea thereof, the described embodiments are only a part of the embodiments of the present invention, not all embodiments, and all other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without creative efforts belong to the protection scope of the present invention.
Claims (2)
1. A method for analyzing dc voltage drop of a system-in-a-chip integrated circuit, the method comprising:
acquiring a multilayer integrated circuit layout of a system-level integrated circuit;
performing mesh generation on each layer of integrated circuit layout in the multilayer integrated circuit layout, and inserting a connection point of an external circuit and each layer of integrated circuit layout and a connection point of a via hole between different layers of integrated circuit layout and each layer of integrated circuit layout into a mesh to form a mesh generation node;
dividing the system level integrated circuit into a plurality of subsystems in units of layers;
sequentially numbering the mesh division nodes of each subsystem, and writing a finite element equation set for direct-current voltage drop analysis according to the information columns of each mesh division node to obtain a finite element sparse matrix;
when the direct current pressure drop of the mth subsystem is analyzed, all subsystems except the mth subsystem in the multiple subsystems are synthesized into a system to be processed;
eliminating internal nodes of a system to be processed in the finite element sparse matrix by adopting a star-triangle transformation method to obtain a sparse matrix for analyzing the mth subsystem field;
solving and analyzing a sparse matrix of the mth subsystem field to obtain direct current voltage drop and current density distribution on the mth subsystem field;
the method for analyzing the m-th subsystem field comprises the following steps of eliminating internal nodes of a system to be processed in the finite element sparse matrix by adopting a star-triangle transformation method, and obtaining a sparse matrix for analyzing the m-th subsystem field, wherein the method specifically comprises the following steps:
the finite element sparse matrix is equivalent to a sparse matrix of an admittance network which takes a finite element grid as association;
repeatedly carrying out star-triangle transformation on the sparse matrix of the admittance network to eliminate internal nodes of the system to be processed, and obtaining a sparse matrix for analyzing the mth subsystem field;
wherein, the equivalence of the finite element sparse matrix into a sparse matrix of an admittance network using a finite element mesh as a correlation specifically includes:
using formulas
The finite element sparse matrix is equivalent to a sparse matrix of an admittance network which takes a finite element grid as association;
wherein u is node voltage, b is a right-end term, which is essentially current source excitation, and A is an admittance matrix of a finite element mesh subdivision node;
wherein, repeatedly performing star-triangle transformation on the sparse matrix of the admittance network to eliminate the internal nodes of the system to be processed specifically comprises:
formula for recycling sparse matrix of admittance network
Performing a star-triangle transformation to eliminate internal nodes of the system to be processed;
wherein the content of the first and second substances,
for the second associated with admittance network node to be cancelled in admittance networkiThe mutual admittance of the individual admittance network nodes and the admittance network node to be cancelled,
for the second associated with admittance network node to be cancelled in admittance networkjThe mutual admittance of the individual admittance network nodes and the admittance network node to be cancelled,
for association with admittance network nodes to be cancellediAn admittance network node and a second associated with the admittance network node to be cancelledjMutual admittance of individual admittance network nodes, corresponding to sparse matrix non-diagonal elementsiLine and firstjThe elements of the column are,
for the second associated with admittance network node to be cancelled in admittance networkkAdmittance networkThe mutual admittance of the node and the admittance network node to be cancelled,pis the number of admittance network nodes associated with the admittance network node to be cancelled.
2. A system-in-a-system integrated circuit dc drop analysis system, the analysis system comprising:
the multilayer integrated circuit layout acquisition module is used for acquiring a multilayer integrated circuit layout of the system-level integrated circuit;
the grid subdivision module is used for carrying out grid subdivision on each layer of integrated circuit layout in the multilayer integrated circuit layout, inserting a connection point of an external circuit and each layer of integrated circuit layout and a connection point of a via hole between different layers of integrated circuit layout and each layer of integrated circuit layout into a grid to form a grid subdivision node;
a subsystem division module for dividing the system-level integrated circuit into a plurality of subsystems in units of layers;
the finite element sparse matrix establishing module is used for numbering the grid division nodes of each subsystem in sequence, writing a finite element equation set for direct current voltage drop analysis according to the information column of each grid division node, and obtaining a finite element sparse matrix;
the system to be processed synthesis module is used for synthesizing all subsystems except the mth subsystem into a system to be processed when analyzing the direct current voltage drop of the mth subsystem;
the star-triangle transformation module is used for eliminating internal nodes of the system to be processed in the finite element sparse matrix by adopting a star-triangle transformation method to obtain a sparse matrix for analyzing the mth subsystem field;
the solving module is used for solving and analyzing the sparse matrix of the mth subsystem field to obtain the direct current voltage drop and the current density distribution on the mth subsystem field;
wherein, star-triangle transform module specifically includes:
the admittance network equivalent submodule is used for equivalent the finite element sparse matrix into a sparse matrix of an admittance network which takes a finite element grid as association;
the internal node elimination submodule is used for repeatedly carrying out star-triangle transformation on the sparse matrix of the admittance network to eliminate the internal nodes of the system to be processed;
the admittance network equivalent submodule specifically includes:
admittance network equivalent unit for using formula
The finite element sparse matrix is equivalent to a sparse matrix of an admittance network which takes a finite element grid as association;
wherein u is node voltage, b is a right-end term, which is essentially current source excitation, and A is an admittance matrix of a finite element mesh subdivision node;
wherein, the internal node elimination submodule specifically includes:
an internal node elimination unit for reusing the sparse matrix of the admittance network
Performing a star-triangle transformation to eliminate internal nodes of the system to be processed;
wherein the content of the first and second substances,
for the second associated with admittance network node to be cancelled in admittance networkiThe mutual admittance of the individual admittance network nodes and the admittance network node to be cancelled,
for the second associated with admittance network node to be cancelled in admittance networkjThe mutual admittance of the individual admittance network nodes and the admittance network node to be cancelled,
for association with admittance network nodes to be cancelledTo (1) aiAn admittance network node and a second associated with the admittance network node to be cancelledjMutual admittance of individual admittance network nodes, corresponding to sparse matrix non-diagonal elementsiLine and firstjThe elements of the column are,
for the second associated with admittance network node to be cancelled in admittance networkkThe mutual admittance of the individual admittance network nodes and the admittance network node to be cancelled,pis the number of admittance network nodes associated with the admittance network node to be cancelled.
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