CN112307696B - 100% reliability parallel structure without output conflict - Google Patents
100% reliability parallel structure without output conflict Download PDFInfo
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- CN112307696B CN112307696B CN202011214809.6A CN202011214809A CN112307696B CN 112307696 B CN112307696 B CN 112307696B CN 202011214809 A CN202011214809 A CN 202011214809A CN 112307696 B CN112307696 B CN 112307696B
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- 238000012544 monitoring process Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 2
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- 230000001052 transient effect Effects 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
- G06F30/343—Logical level
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
- G06F2119/02—Reliability analysis or reliability optimisation; Failure analysis, e.g. worst case scenario performance, failure mode and effects analysis [FMEA]
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Abstract
The application provides a 100% output conflict-free reliable parallel structure, which comprises a computer A, a computer B and a servo driver; the computer A comprises a fault logic A circuit, a driving A circuit, an instruction calculation A circuit, a control quantity output A circuit, a switch KA-A and a switch KA-B; wherein: the output end of the instruction calculating circuit A is respectively connected with the control quantity output circuit A and the fault logic circuit A, and the input end of the instruction calculating circuit A is connected with the output end of the control quantity output circuit A and the output end of the instruction calculating circuit B; the output end of the control quantity output A circuit is also connected with a pin 2 of a switch KA-A, a pin 1 of the switch KA-A is connected with a pin 3 of a switch KB-B, a pin 3 of the switch KA-A is connected with a pin 2 of the switch KA-B, a pin 1 of the switch KA-B is connected with a pin 3 of the switch KB-B, and a pin 3 of the switch KA-B is connected with a servo drive; the fault logic A circuit is connected with the switch KA-A and the switch KA-B through the drive A circuit respectively.
Description
Technical Field
The application relates to the architecture design technology of an aviation onboard computer system, in particular to a 100% reliability parallel structure without output conflict.
Background
The onboard embedded computer participating in the control of the aircraft belongs to core onboard equipment in the aviation aircraft, and a parallel architecture is adopted, so that the method for improving the reliability of products or ensuring the safety working characteristics is commonly used. In the case that the control object has no fault tolerance, the general parallel reliability structure principle is shown in fig. 1, and the structure of the classical parallel interconnection design system corresponding to the structure is shown in fig. 2, namely, a computer a and a computer B form a dual-control computer system, the computer B is a backup of the computer a, and output signals of the computer a and the computer B are commonly connected to a target device with no fault tolerance after passing through respective switches. The classical design structure shown in fig. 2 has clear and concise hierarchy, the computer a and the computer B are completely equivalent, and has been widely adopted, but the architecture design must strictly and completely ensure that the control of the fault logic a and the fault logic B on the switch KA-1 and the switch KB-1 cannot be in a state of being simultaneously turned on, that is, the switch KA-1 cannot be turned on the output of the computer B before the output is completely turned off, otherwise, signal collision is generated, transient disturbance of the system is induced slightly, and failure and damage of the control computer are caused seriously.
In order to ensure this point of view,
disclosure of Invention
In order to solve the technical problem, the application provides a reliable parallel structure with 100% no output conflict, which can eliminate the output signal conflict 100%.
In a first aspect, the present application provides a 100% output conflict free reliable parallel architecture comprising computer a, computer B, and servo drive; the computer A comprises a fault logic A circuit, a driving A circuit, an instruction calculation A circuit, a control quantity output A circuit, a switch KA-A and a switch KA-B; the computer B comprises ase:Sub>A fault logic B circuit, ase:Sub>A driving B circuit, an instruction calculating B circuit, ase:Sub>A control quantity output B circuit, ase:Sub>A switch KB-A and ase:Sub>A switch KB-B, wherein:
the output end of the instruction calculating circuit A is respectively connected with the control quantity output circuit A and the fault logic circuit A, and the input end of the instruction calculating circuit A is connected with the output end of the control quantity output circuit A and the output end of the instruction calculating circuit B; the output end of the control quantity output A circuit is also connected with a pin 2 of a switch KA-A, a pin 1 of the switch KA-A is connected with a pin 3 of a switch KB-B, a pin 3 of the switch KA-A is connected with a pin 2 of the switch KA-B, a pin 1 of the switch KA-B is connected with a pin 3 of the switch KB-B, and a pin 3 of the switch KA-B is connected with a servo drive; the fault logic A circuit is respectively connected with the switch KA-A and the switch KA-B through the drive A circuit;
the output end of the instruction calculating circuit B is respectively connected with the control quantity output circuit B and the fault logic circuit B, and the input end of the instruction calculating circuit B is connected with the output end of the control quantity output circuit B and the instruction calculating circuit A; the output end of the control quantity output B circuit is also connected with ase:Sub>A pin 2 of ase:Sub>A switch KB-A, ase:Sub>A pin 1 of the switch KB-A is suspended, ase:Sub>A pin 3 of the switch KB-A is connected with ase:Sub>A pin 2 of ase:Sub>A switch KB-B, ase:Sub>A pin 1 of the switch KB-B is suspended, and ase:Sub>A pin 3 of the switch KB-B is connected with ase:Sub>A pin 1 of ase:Sub>A switch Kase:Sub>A-ase:Sub>A and ase:Sub>A pin 1 of ase:Sub>A switch KA-B; the fault logic B circuit is connected with the switch KB-A and the switch KB-B through the drive B circuit respectively; the fault logic B circuit is connected with the fault logic A circuit.
Preferably, the switch Kase:Sub>A-ase:Sub>A, the switch KA-B, the switch KB-A and the switch KB-B are all single pole double throw switches.
Preferably, pin 3 of switch KB-A communicates with pin 1 of switch KB-A to output an open circuit condition, and pin 3 of switch KB-B communicates with pin 1 of switch KB-B to output an open circuit condition, without switch KB-A and switch KB-B being turned on.
Preferably, computer a has a higher output priority than computer B.
In a second aspect, the present application provides a 100% output conflict free reliable parallel architecture comprising computer a, computer B, and servo drive; the computer A comprises a fault logic A circuit, a driving A circuit, an instruction calculation A circuit, a control quantity output A circuit, a switch KA-A and a switch KA-B; the computer B comprises ase:Sub>A fault logic B circuit, ase:Sub>A driving B circuit, an instruction calculating B circuit, ase:Sub>A control quantity output B circuit, ase:Sub>A switch KB-A and ase:Sub>A switch KB-B, wherein:
the output end of the instruction calculating circuit A is respectively connected with the control quantity output circuit A and the fault logic circuit A, and the input end of the instruction calculating circuit A is connected with the output end of the control quantity output circuit A and the output end of the instruction calculating circuit B; the output end of the control quantity output A circuit is also connected with ase:Sub>A pin 2 of ase:Sub>A switch Kase:Sub>A-ase:Sub>A, ase:Sub>A pin 1 of the switch Kase:Sub>A-ase:Sub>A is suspended, ase:Sub>A pin 3 of the switch Kase:Sub>A-ase:Sub>A is connected with ase:Sub>A pin 2 of ase:Sub>A switch KA-B, ase:Sub>A pin 1 of the switch KA-B is suspended, and ase:Sub>A pin 3 of the switch KA-B is respectively connected with ase:Sub>A pin 1 of ase:Sub>A switch KB-A and ase:Sub>A pin 1 of the switch KB-B; the fault logic A circuit is respectively connected with the switch KA-A and the switch KA-B through the drive A circuit;
the output end of the instruction calculating circuit B is respectively connected with the control quantity output circuit B and the fault logic circuit B, and the input end of the instruction calculating circuit B is connected with the output end of the control quantity output circuit B and the instruction calculating circuit A; the output end of the control quantity output B circuit is also connected with ase:Sub>A pin 2 of ase:Sub>A switch KB-A, ase:Sub>A pin 1 of the switch KB-A is connected with ase:Sub>A pin 3 of ase:Sub>A KA-B, ase:Sub>A pin 3 of the switch KB-A is connected with ase:Sub>A pin 2 of the switch KB-B, ase:Sub>A pin 1 of the switch KB-B is connected with ase:Sub>A pin 3 of the KA-B, and ase:Sub>A pin 3 of the KB-B is connected with ase:Sub>A servo driver; the fault logic B circuit is connected with the switch KB-A and the switch KB-B through the drive B circuit respectively; the fault logic B circuit is connected with the fault logic A circuit.
Preferably, the switch Kase:Sub>A-ase:Sub>A, the switch KA-B, the switch KB-A and the switch KB-B are all single pole double throw switches.
Preferably, in the case that the switch KA-B is not turned on, the pin 3 of the switch KA-B is connected to the pin 1 of the switch KA-B to output an open state, and the fault logic a output signal is driven to connect the switch KA-a and the switch KA-B to control their on/off states.
Preferably, computer a has a higher output priority than computer B.
In summary, the application provides a 100% reliable parallel structure without output conflict, and under the condition of adding less additional hardware resources, by means of the uncontrolled normally-on pins which are empty on the inherent switch in the original design, the problem of conflict of redundant computing resource control output signals in the classical parallel system is overcome by changing the output signal parallel connection into the serial connection through the two-stage switch output, and the safety characteristic of computer work can be further effectively improved by designing 2-stage wrapping monitoring measures. The structure of the scheme I is suitable for an application environment in which the output priority of the computer A is higher than that of the computer B in the parallel system and the computer A is required to independently output signals; the structure of the scheme II is suitable for an application environment with higher output priority of the computer A than that of the computer B in the parallel system and high requirement on the system integrity; meanwhile, the 2 schemes are suitable for application environments with the requirement of 'safe cut-off after single failure'.
Drawings
FIG. 1 is a schematic block diagram of a parallel reliability architecture in the prior art;
FIG. 2 is a schematic diagram of a classical parallel system output design in the prior art;
FIG. 3 is a diagram of a design scheme I of a 100% output collision free reliable parallel architecture provided in the present application;
fig. 4 is a second design of a 100% output collision free reliable parallel structure provided in the present application.
Detailed Description
In order to more effectively ensure that control output signals are prevented from collision under a reliable parallel structure system, the design provides a reliable parallel structure design which has practical value, can eliminate output signal collision by 100% and can effectively overcome primary faults for a parallel redundancy computer in an onboard control system, and as shown in fig. 3 and 4, the design is as follows in detail:
the onboard embedded computer participating in the control of the aircraft belongs to core onboard equipment in the aviation aircraft, and a parallel architecture is adopted to be a common method for improving the reliability of products or ensuring the safety working characteristics, so that the classical parallel interconnection design architecture under the structure has a little defect, and the problem of the conflict of parallel computing resource output signals is solved. The proposal provides an optimized solution, can ensure that 100% of the computer systems with the reliability parallel structures have no output conflict, and is suitable for popularization and use in embedded control systems with certain reliability and safety requirements.
Example 1
As shown in FIG. 3, the pin 2 of the switch KB-A of the computer B is connected with the output signal of the control quantity output B, the pin 1 of the switch KB-A is suspended, the pin 2 of the switch KB-B is connected with the pin 3 of the switch KB-A, the pin 3 of the switch KB-A is connected with the pin 2 of the switch KB-B, the pin 3 of the switch KB-A is communicated with the pin 1 of the KB-A to output an open circuit state under the condition that the KB-A, KB-B is not turned on, the pin 3 of the KB-B is communicated with the pin 1 of the KB-B to output an open circuit state, the fault logic B output signal is driven to simultaneously control the on states of the KB-A switch and the KB-B switch, when the switch KB-A is turned on, the pin 3 of the switch KB-A is communicated with the pin 2 of the switch KB-B, and the pin 3 of the switch KB-B is communicated with the pin 2 of the switch KB-B, and the signal generated by the control quantity output B of the computer B is output to the outside of the computer B. The output of pin 3 of KB-B in computer B in FIG. 3 is common to pin 3 of KA-B in computer A, but is connected to pin 1 of switch KA-A and pin 1 of switch KA-B, respectively. The pin 2 of the switch KA-A of the computer A is connected with the output signal of the control quantity output A, the pin 3 of the switch KA-A is connected with the pin 2 of the switch KA-B, the pin 3 of the switch KA-A is communicated with the pin 1 of the switch KA-A under the condition that the switch KA-A is not turned on, the pin 3 of the switch KA-B is communicated with the pin 1 of the switch KA-B under the condition that the switch KA-B is not turned on, when the fault logic A output signal is driven to turn on the switch KA-A and the switch KA-B, the pin 3 of the switch KA-A is communicated with the pin 2 of the switch KA-A, and the pin 3 of the switch KA-B is communicated with the pin 2 of the switch KA-B, so that the signal output by the control quantity A is output to the outside of the computer A to servo driving.
It should be noted that, the structure of the first design is suitable for an application environment in which the output priority of the computer a is higher than that of the computer B in the parallel system, and the computer a is required to independently output signals.
Example two
As shown in FIG. 4, the pin 2 of the switch KA-A in the computer A is connected with the output signal of the control quantity output A, the pin 1 of the switch KA-A is suspended, the pin 3 of the switch KA-A is communicated with the pin 1 of the switch KA-A to output an open-circuit state when the switch KA-A is not turned on, the pin 2 of the switch KA-B is connected with the pin 3 of the switch KA-A, the pin 1 of the switch KA-B is suspended, the pin 3 of the switch KA-B is communicated with the pin 1 of the switch KA-B to output an open-circuit state when the switch KA-B is not turned on, and the fault logic A output signal is driven to connect the switch KA-A and the switch KA-B to control the on/off states of the switch KA-A and the switch KA-B. When the switch KA-A and the switch KA-B are turned on, the pin 3 of the switch KA-A is communicated with the pin 2 of the switch KA-A to output the signal of the control quantity A, and the pin 3 of the switch KA-B is communicated with the pin 2 of the switch KA-B to output the signal of the control quantity output A to the outside of the computer A. The output of pin 3 of KA-B in computer A in FIG. 4 is common to pin 3 of KB-B in computer B, but is connected to pin 1 of switch KB-A and pin 1 of switch KB-B, respectively. Pin 3 of switch KB-A is connected to pin 2 of switch KB-B. Under the condition that ase:Sub>A switch KB-A is not turned on, ase:Sub>A pin 3 of the KB-A is communicated with ase:Sub>A pin 1 of the KB-A, ase:Sub>A pin 3 of the KB-B is communicated with ase:Sub>A pin 1 of the KB-B to output signals sent by ase:Sub>A computer A, when ase:Sub>A fault logic B output signal is driven to turn on the switch KB-A and the switch KB-B, the pin 3 of the KB-A is communicated with ase:Sub>A pin 2 of the KB-A, the pin 3 of the KB-B is communicated with ase:Sub>A pin 2 of the KB-B, and the signals of ase:Sub>A control quantity output B are output to the outside of the computer B to servo driving.
It should be noted that, the structure of the second design is suitable for an application environment with higher output priority of the computer a than that of the computer B in the parallel system and high requirement on system integrity.
It can be understood that the first and second design schemes adopt 2-stage output wrapping to realize the safety monitoring of the output signal, namely the signal output by the control quantity output A is wrapped and connected to the instruction calculation A to realize the inner wrapping monitoring of the first stage while being connected with the pin 2 of the switch KA-A; the signal output by the control quantity output B is connected with the pin 2 of the switch KB-A in ase:Sub>A wrapping mode and is connected to the instruction computing B in ase:Sub>A wrapping mode, and therefore the inner wrapping monitoring of the first stage is achieved. The signals connected with the servo drive are respectively and externally wound to an instruction calculation A of the computer A and an instruction calculation B of the computer B, so that the second-stage safety monitoring of the output signals is realized.
Claims (8)
1. A 100% output conflict free reliable parallel architecture characterized in that the parallel architecture comprises a computer a, a computer B and a servo drive; the computer A comprises a fault logic A circuit, a driving A circuit, an instruction calculation A circuit, a control quantity output A circuit, a switch KA-A and a switch KA-B; the computer B comprises ase:Sub>A fault logic B circuit, ase:Sub>A driving B circuit, an instruction calculating B circuit, ase:Sub>A control quantity output B circuit, ase:Sub>A switch KB-A and ase:Sub>A switch KB-B, wherein:
the output end of the instruction calculating circuit A is respectively connected with the control quantity output circuit A and the fault logic circuit A, and the input end of the instruction calculating circuit A is connected with the output end of the control quantity output circuit A and the output end of the instruction calculating circuit B; the output end of the control quantity output A circuit is also connected with a pin 2 of a switch KA-A, a pin 1 of the switch KA-A is connected with a pin 3 of a switch KB-B, a pin 3 of the switch KA-A is connected with a pin 2 of the switch KA-B, a pin 1 of the switch KA-B is connected with a pin 3 of the switch KB-B, and a pin 3 of the switch KA-B is connected with a servo drive; the fault logic A circuit is respectively connected with the switch KA-A and the switch KA-B through the drive A circuit;
the output end of the instruction calculating circuit B is respectively connected with the control quantity output circuit B and the fault logic circuit B, and the input end of the instruction calculating circuit B is connected with the output end of the control quantity output circuit B and the instruction calculating circuit A; the output end of the control quantity output B circuit is also connected with ase:Sub>A pin 2 of ase:Sub>A switch KB-A, ase:Sub>A pin 1 of the switch KB-A is suspended, ase:Sub>A pin 3 of the switch KB-A is connected with ase:Sub>A pin 2 of ase:Sub>A switch KB-B, ase:Sub>A pin 1 of the switch KB-B is suspended, and ase:Sub>A pin 3 of the switch KB-B is connected with ase:Sub>A pin 1 of ase:Sub>A switch Kase:Sub>A-ase:Sub>A and ase:Sub>A pin 1 of ase:Sub>A switch KA-B; the fault logic B circuit is connected with the switch KB-A and the switch KB-B through the drive B circuit respectively; the fault logic B circuit is connected with the fault logic A circuit.
2. The reliable shunt structure of claim 1, wherein switch Kase:Sub>A-ase:Sub>A, switch Kase:Sub>A-B, switch KB-ase:Sub>A and switch KB-B are all single pole double throw switches.
3. The reliable parallel structure of claim 1 wherein pin 3 of switch KB-ase:Sub>A communicates with pin 1 of switch KB-ase:Sub>A to output an open state and pin 3 of switch KB-B communicates with pin 1 of switch KB-B to output an open state in the event that switch KB-ase:Sub>A, switch KB-B are not turned on.
4. The reliable parallel architecture of claim 1 wherein computer a has a higher output priority than computer B.
5. A 100% output conflict free reliable parallel architecture characterized in that the parallel architecture comprises a computer a, a computer B and a servo drive; the computer A comprises a fault logic A circuit, a driving A circuit, an instruction calculation A circuit, a control quantity output A circuit, a switch KA-A and a switch KA-B; the computer B comprises ase:Sub>A fault logic B circuit, ase:Sub>A driving B circuit, an instruction calculating B circuit, ase:Sub>A control quantity output B circuit, ase:Sub>A switch KB-A and ase:Sub>A switch KB-B, wherein:
the output end of the instruction calculating circuit A is respectively connected with the control quantity output circuit A and the fault logic circuit A, and the input end of the instruction calculating circuit A is connected with the output end of the control quantity output circuit A and the output end of the instruction calculating circuit B; the output end of the control quantity output A circuit is also connected with ase:Sub>A pin 2 of ase:Sub>A switch Kase:Sub>A-ase:Sub>A, ase:Sub>A pin 1 of the switch Kase:Sub>A-ase:Sub>A is suspended, ase:Sub>A pin 3 of the switch Kase:Sub>A-ase:Sub>A is connected with ase:Sub>A pin 2 of ase:Sub>A switch KA-B, ase:Sub>A pin 1 of the switch KA-B is suspended, and ase:Sub>A pin 3 of the switch KA-B is respectively connected with ase:Sub>A pin 1 of ase:Sub>A switch KB-A and ase:Sub>A pin 1 of the switch KB-B; the fault logic A circuit is respectively connected with the switch KA-A and the switch KA-B through the drive A circuit;
the output end of the instruction calculating circuit B is respectively connected with the control quantity output circuit B and the fault logic circuit B, and the input end of the instruction calculating circuit B is connected with the output end of the control quantity output circuit B and the instruction calculating circuit A; the output end of the control quantity output B circuit is also connected with ase:Sub>A pin 2 of ase:Sub>A switch KB-A, ase:Sub>A pin 1 of the switch KB-A is connected with ase:Sub>A pin 3 of ase:Sub>A KA-B, ase:Sub>A pin 3 of the switch KB-A is connected with ase:Sub>A pin 2 of the switch KB-B, ase:Sub>A pin 1 of the switch KB-B is connected with ase:Sub>A pin 3 of the KA-B, and ase:Sub>A pin 3 of the KB-B is connected with ase:Sub>A servo driver; the fault logic B circuit is connected with the switch KB-A and the switch KB-B through the drive B circuit respectively; the fault logic B circuit is connected with the fault logic A circuit.
6. The reliable shunt structure of claim 5, wherein switch Kase:Sub>A-ase:Sub>A, switch Kase:Sub>A-B, switch KB-ase:Sub>A and switch KB-B are all single pole double throw switches.
7. The reliable parallel architecture of claim 5, wherein in the event that switch KA-B is not turned on, pin 3 of switch KA-B communicates with pin 1 of KA-B to output an open state, and fault logic a output signals are driven to connect switch KA-a and switch KA-B to control their on/off states.
8. The reliable parallel architecture of claim 5, wherein computer a has a higher output priority than computer B.
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| CN202011214809.6A CN112307696B (en) | 2020-11-03 | 2020-11-03 | 100% reliability parallel structure without output conflict |
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| CN112307696B true CN112307696B (en) | 2023-12-22 |
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| CN113885306B (en) * | 2021-09-08 | 2024-06-04 | 中国航空工业集团公司西安航空计算技术研究所 | Signal output circuit supporting interchangeability under security architecture |
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| CN103150242A (en) * | 2012-12-27 | 2013-06-12 | 中国航空工业集团公司第六三一研究所 | Exact indicating circuit for internal fault of F/S type computer |
| CN105278525A (en) * | 2015-11-13 | 2016-01-27 | 兰州飞行控制有限责任公司 | Parallel steering engine drive circuit with fault monitoring function |
| CN105305387A (en) * | 2014-07-28 | 2016-02-03 | 倍加福有限责任公司 | Device and method for monitoring and switching a load circuit |
| CN205751249U (en) * | 2016-05-16 | 2016-11-30 | 安徽超远信息技术有限公司 | A kind of independent circuits equipment evading the green collision failure of semaphore |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103150242A (en) * | 2012-12-27 | 2013-06-12 | 中国航空工业集团公司第六三一研究所 | Exact indicating circuit for internal fault of F/S type computer |
| CN105305387A (en) * | 2014-07-28 | 2016-02-03 | 倍加福有限责任公司 | Device and method for monitoring and switching a load circuit |
| CN105278525A (en) * | 2015-11-13 | 2016-01-27 | 兰州飞行控制有限责任公司 | Parallel steering engine drive circuit with fault monitoring function |
| CN205751249U (en) * | 2016-05-16 | 2016-11-30 | 安徽超远信息技术有限公司 | A kind of independent circuits equipment evading the green collision failure of semaphore |
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