CN1122931C - Microprocessor architecture able to implement digital filtering operation and its digital filtering operation method - Google Patents
Microprocessor architecture able to implement digital filtering operation and its digital filtering operation method Download PDFInfo
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- CN1122931C CN1122931C CN 99122306 CN99122306A CN1122931C CN 1122931 C CN1122931 C CN 1122931C CN 99122306 CN99122306 CN 99122306 CN 99122306 A CN99122306 A CN 99122306A CN 1122931 C CN1122931 C CN 1122931C
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Abstract
The present invention relates to a microprocessor architecture of implementing digital filtering operations and a digital filtering operation method thereof. A limited response digital filtering operation and an inner product operation of digital signal processing are supplied by a progressive increase device/a demultiplier, a summation circuit of a microprocessor, a temporary memory group, etc. When the limited response digital filtering operation is carried out, the data of a filter can be automatically moved by the action of the progressive increase device/the demultiplier. Consequently, when the next operation is carried out, after new data is filled in and an index address is set, the operation is carried out immediately. Therefore, the microprocessor can effectively carry out a digital signal processing operation.
Description
The present invention is the technical field of relevant digital signal processing, refers to a kind of microprocessor architecture and digital filtering operation method of realizing digital filtering operation especially.
Press, finite response digital filter (Finite Impulse Response Filer, FIE) and inner product of vectors (Inner Product) be to be the fundamental operation square in the known digital signal processor (DSP), and the FIR computing is the processing of carrying out following formula:
Wherein, N is the exponent number of wave filter, x
nBe the n time input, y
nBe the n time output; c
i(i=0...N-1) be the fixed coefficient of wave filter.With N=4 is example:
y
n＝c
0x
n+c
1x
n-1+c
2x
n-2+c
3x
n-3，
The computing of next record data then is:
y
n+1＝c
0x
n+1+c
1x
n+c
2x
n-1+c
3x
n-2。
For can allow must computing can after each document is come in, carry out smoothly, in traditional digital signal processor, its next record data can cover the oldest data, and index moved on to a up-to-date document, and in the process of computing the automatic position of parameter, shown in Fig. 3 A, be arranged in the storer that carries out before the first stroke data is calculated ... c
0, c
1, c
2, c
3, x
n, x
N-1, x
N-2, x
N-3, index R1 and R2 point to c respectively
0And x
n, and will carry out before the next record computing, then earlier with x
N-3With x
N+1Cover, and index R2 is changed to x
N+1The place, shown in Fig. 3 B, and carry out at every turn every document institute must N multiplying the time, then be each with the new index Rn of extra address generator 31 generations, carry out multiply-add operation.Its compute mode is:
R2＝(R2-Base+i)％N+Base，
Wherein, N=4, i=0...N-1, Base are the substrate address that the x value is placed, R2 then is the first stroke data address of this computing.
Hence one can see that, and known digital signal processor is in order to carry out once multiplying in each cycle, so must carry out the computing work that index is revised with extra hardware.Yet among these computings, it need three times add/subtraction and modulo operation once, so must pay considerable hardware costs, and general micro controller is not because of containing hardware multiplier, so be difficult to provide efficiently the calculation function of this kind digital signal processing, therefore, based on considering of hardware resource, realize the function of digital filter computing its necessity being arranged promptly as the framework of a microprocessor how.
The inventor whence originally in the spirit of positive invention, is urgently thought a kind of microprocessor architecture and digital filtering operation method of the digital filtering operation realized that can address the above problem because of in this, and several times research experiment is eventually to finishing this novel progressive invention.
A purpose of the present invention is that a kind of microprocessor architecture of realizing digital filtering operation is being provided, and makes the finite response digital filtering of microprocessor tool digital signal processing and the function of inner product operation to use simple hardware resource.
Another object of the present invention is that a kind of method that realizes digital filtering operation with microprocessor is being provided, it can carry out computing by the data of moving wave filter automatically at once only new data must be inserted and set the index address when carrying out the next record computing after, and makes microprocessor effectively be carried out the finite response digital filtering operation of digital signal processing.
A kind of microprocessor architecture of realizing digital filtering operation of the present invention, it is to store a plurality of digital filtering coefficients in regular turn and treat that the storer of the input value of filtering carries out the finite response digital filtering operation one, it is characterized in that this microprocessor architecture mainly comprises:
One working storage group, it has first working storage and second working storage, to point to a digital filtering coefficient and an input value of this storer respectively;
One summation circuit, it is value digital filtering coefficient and the input value pointed that reads this first working storage and second working storage, adopt arithmetic logic unit so that this digital filtering coefficient and input value are multiplied each other, and the value that will multiply each other is added up: and
One incrementor, it is to increase progressively computing in order to the value to this first and second working storage;
Wherein, when this summation circuit carries out accumulating operation, the input value that this totalizer read is kept in, this incrementor increases progressively the value of this first and second working storage, and return respectively and deposit, and this totalizer with the value of first and second working storage of having increased progressively be the address and certainly this storer read a digital filtering coefficient and an input value respectively, and be that the input value that the address will be kept in writes in this storer with the value of second working storage that increased progressively, carry out computing next time again.
Wherein this summation circuit comprises:
One input working storage, it is the input value that is read in order to store;
One coefficient working storage, it is the digital filtering coefficient that is read in order to store;
One interim working storage, it is temporary in order to the input value that will read to this input working storage; And
One takes advantage of/adds arithmetic element, and it is with arithmetic logic unit this input working storage and this coefficient working storage content to be carried out multiplying, and multiplied result is added to an output working storage.
Wherein this to take advantage of/add arithmetic element be to carry out multiplying with cloth formula algorithm.
A kind of microprocessor architecture of realizing digital filtering operation of the present invention, it is to store a plurality of digital filtering coefficients in regular turn and treat that the storer of the input value of filtering carries out the finite response digital filtering operation one, it is characterized in that this microprocessor architecture mainly comprises:
One working storage group, it has first working storage and second working storage, to point to a digital filtering coefficient and an input value of this storer respectively;
One summation circuit, it is value digital filtering coefficient and the input value pointed that reads this first working storage and second working storage, adopt arithmetic logic unit so that this digital filtering coefficient and input value are multiplied each other, and the value that will multiply each other is added up: and
One demultiplier, it is in order to computing that the value of this first and second working storage is successively decreased;
Wherein, when this summation circuit carries out accumulating operation, the input value that this totalizer read is kept in, this demultiplier successively decreases the value of this first and second working storage, and return respectively and deposit, and this totalizer with the value of first and second working storage of having successively decreased be the address and certainly this storer read a digital filtering coefficient and an input value respectively, and be that the input value that the address will be kept in writes in this storer with the value of second working storage that successively decreased, carry out computing next time again.
Wherein this summation circuit comprises:
One input working storage, it is the input value that is read in order to store:
One coefficient working storage, it is the digital filtering coefficient that is read in order to store;
One interim working storage, it is temporary in order to the input value that will read to this input working storage; And
One takes advantage of/adds arithmetic element, and it is with arithmetic logic unit the content of this input working storage and this coefficient working storage to be carried out multiplying, and multiplied result is added to an output working storage.
Wherein this to take advantage of/add arithmetic element be to carry out multiplying with cloth formula algorithm.
A kind of method of the present invention with microprocessor realization digital filtering operation, it is to store the digital filtering coefficient in regular turn and treat that the storer of the input value of filtering carries out the finite response digital filtering operation, is characterized in that this method mainly comprises following step one:
(A) read first digit filter factor and first input value;
(B) the digital filtering coefficient and the input value that are read are carried out multiplying, and it is added up;
(C) keep this input value;
(D) read next digital filtering coefficient and next input value:
(E) input value that is kept is moved to the memory location that stores this next one input value, and be back to step (B) to repeat, until the product accumulation of last digital filtering coefficient and last input value is finished.
Wherein employed microprocessor has first and second working storage, and the value of this first and second working storage is pointed to this digital filtering coefficient and this input value respectively.
Wherein step (A) is that the memory read that the value of this first working storage is pointed is taken to a coefficient working storage, and the memory read that the value of second working storage is pointed is taken to an input working storage;
Wherein step (B) is that value with this coefficient working storage and this input working storage multiplies each other and is added to an output working storage.
Wherein step (C) is that value with this input working storage is stored to an interim working storage.
Wherein step (D) is that value with this first working storage adds a memory read pointed and is taken to this coefficient working storage, and the value of this first working storage increased progressively, and the value of this second working storage is added a memory read pointed be taken to this input value working storage, and the value of this this second working storage is increased progressively.
Wherein step (E) is the value memory location pointed that the value of this interim working storage is deposited in this second working storage.
Wherein step (D) is that value with this first working storage subtracts a memory read pointed and is taken to this coefficient working storage, and the value of this first working storage successively decreased, and the value of this second working storage is subtracted a memory read pointed be taken to this input value working storage, and the value of this second working storage is successively decreased.
Wherein step (E) is the value memory location pointed that the value of this interim working storage is deposited in this second working storage.
Because modern design of the present invention can provide on the industry and utilize, and truly have the enhancement effect, so apply for a patent in accordance with the law.
For making your juror can further understand structure of the present invention, feature and purpose thereof, the attached now detailed description with graphic and preferred embodiment as after, wherein:
Figure 1A and Figure 1B show the realize microprocessor architecture of digital filtering operation and the arrangement of data in storer of digital filtering operation method institute computing thereof of the present invention.
Fig. 2 is the system block diagrams that realizes the microprocessor architecture of digital filtering operation for of the present invention.
Fig. 3 A and Fig. 3 B show the known data arrangement of digital signal processor when carrying out digital filtering operation.
A relevant preferred embodiment that realizes the microprocessor architecture and the digital filtering operation method thereof of digital filtering operation of the present invention, please be earlier with reference to the storer arrangement shown in Figure 1A and Figure 1B, wherein, Figure 1A is shown in the storer arrangement of carrying out before the first stroke data is calculated and also is ... c
0, c
1, c
2, c
3, x
n, x
N-1, x
N-2, x
N-3..., index R1 and R2 point to c respectively
0And x
n, and when the computing of next record data, when the storer arrangement for shown in Figure 1B ... c
0, c
1, c
2, c
3, x
N+1, x
n, x
N-1, x
N-2..., index R1 and R2 then point to c respectively
0And x
N+1, then just can carry out computing with identical compute mode, do not do special processing and must not move, and can be achieved with the structure of microprocessor to the index of R1 or R2.
Fig. 2 promptly shows an embodiment who realizes the microprocessor architecture of digital filtering operation of the present invention, and it is to store a plurality of digital filtering coefficient c in regular turn to one
iAnd treat the input value x of filtering
iStorer 21 carry out the finite response digital filtering operation, and this microprocessor architecture mainly includes summation circuit 22, working storage group 23, incrementor 24 and multiplexer 25, wherein, this working storage group 23 has the first working storage R1 and the second working storage R2, in order to point to a digital filtering coefficient c of this storer 21 respectively
iAn and input value x
i, so that to carry out the access of storer.
This summation circuit 22 is in order to the value that reads this first working storage R1 and second working storage R2 digital filtering coefficient c pointed
iAnd input value x
i, adopt that arithmetic logic unit (ALU) with microprocessor realized take advantage of/add arithmetic element 221 and with this digital filtering coefficient c
iAnd input value x
iMultiply each other, and the value that will multiply each other is added up, this summation circuit 22 has buffer-stored settings such as coefficient working storage CR, input working storage XR, interim working storage TEMP and output working storage ADO in addition, the usefulness that stores data with as computing the time, this output working storage ADO is initialized to 0 again.
This incrementor 24 is in order to this first and second working storage R1, and the value of R2 increases progressively computing, and 25 of this multiplexers are to select one in order to the output of the output of this summation circuit 22 certainly or this incrementor 24 to enter this working storage group 23.
And can realize the computing of digital filtering by aforesaid microprocessor architecture, it is via the address bus 26 of microprocessor and data bus 27 and at first the value storer 21 pointed of this first working storage R1 to be read to this coefficient working storage CR, and the storer 21 that the value of the second working storage R2 is pointed reads to this input working storage XR, uses and obtains a digital filtering coefficient c respectively
iAn and input value x
i,
Obtained digital filtering coefficient c
iAnd input value x
iPromptly take advantage of/add arithmetic element 221 to be multiplied each other, and multiplied result is added to this output working storage ADO by this.
At this moment, the value of this input working storage XR also is stored among this interim working storage TEMP in addition to keep.
Calculate and during accumulating operation and carry out aforesaid taking advantage of in this summation circuit 22, this summation circuit 22 also can read the required data of computing next time from this storer 21, it is that to add one via this incrementor 24 be the address for value with this first working storage R1, and the storer 21 that it is pointed reads to this coefficient working storage CR, and the value of this first working storage R1 is increased progressively automatically via this incrementor 24; In addition adding one with the value of this second working storage R2 via this incrementor 24 is the address, and the storer 21 that it is pointed reads to this input working storage XR, and the value of this second working storage R2 is increased progressively automatically via this incrementor 24.
When this summation circuit 22 after this storer 21 reads the required data of computing, the value of this interim working storage TEMP is that the address deposits its storer pointed 21 in the value of this second working storage R2 that has increased progressively promptly, and can be automatically with an input value x
iAutomatically move to next memory location, be back to again afterwards and aforementionedly take advantage of the processing of calculating and adding up, so repeat to take advantage of the computing of calculating and adding up, until with last digital filtering coefficient c with summation circuit 22
iWith last input value x
iProduct accumulation till this output working storage ADO, can finish required finite response digital filtering operation, and the operation result that will be stored in this output working storage ADO is through this multiplexer 25 and export.
In the operational method of aforesaid microprocessor architecture and realization digital filtering, its required multiplying and multiplier that need not hardware, but can be achieved by the arithmetic logic unit of microprocessor, it is preferably with cloth formula algorithm (Booth Multiplication Algorithm) and finishes, or other any multiply periodic multiplication modes all can be used.
By above explanation as can be known, the microprocessor architecture of realizing digital filtering operation of the present invention and digital filtering operation method thereof have really been reached with microprocessor and have been carried out the finite response digital filtering operation, its in the process of computing be utilize incrementor 24 effect and automatically will be as the digital filtering coefficient c of multiplicand
iMove to next memory location, this incrementor 24 is carried out in the multiplication calculation process in arithmetic logic unit, can be automatically the value of the second working storage R2 and the first working storage R1 be added one and return and deposit it, this result who adds is used for the multiplication next time of same finite response digital filtering operation, and after the value that the second working storage R2 is pointed to when computing next time is written into, can the previous multiplicand of arithmetic logic unit will be stored in simultaneously, the value of the second working storage R2 is that the address sees through data bus 27 and is recycled in the storer 21 with this moment, also can make its not loopback, like this then correspond to simple inner product operation, input value x after promptly computing is finished
iData can not be moved, so reach the purpose that data moves.The computing that does not influence arithmetic logic unit of moving owing to these data, can carry out simultaneously with the multiplication that in arithmetic logic unit, carries out simultaneously, to increasing on the sequential, data is moved and the finite response digital filtering operation so can finish simultaneously very efficiently.
And for example when the data in storer 21 be during with the series arrangement of successively decreasing, that is digital filtering coefficient c
iAnd treat the input value x of filtering
iOrientation when opposite with Figure 1A and Figure 1B those shown, the microprocessor architecture of realizing digital filtering operation of the present invention and digital filtering operation method thereof can also a demultiplier replace the incrementor 24 of the foregoing description, and the computing that increases progressively in the aforementioned finite response digital filtering operation is replaced it with the computing of successively decreasing, also can reach identical effect, structure that it is whole and operational method and the above embodiments are suitable.
To sum up institute is old, and no matter the present invention is all showing it totally different in the feature of known techniques with regard to purpose, means and effect, for the quantum jump in the design that realizes digital filtering operation, earnestly ask your juror and perceive, grant quasi patent early, so that Jiahui society, the true feeling moral just.Only it should be noted that above-mentioned many embodiment give an example for convenience of explanation, the interest field that the present invention advocated should be as the criterion so that claim is described certainly, but not only limits to the foregoing description.
Claims (13)
1. the microprocessor architecture that can realize digital filtering operation, it is to store a plurality of digital filtering coefficients in regular turn and treat that the storer of the input value of filtering carries out the finite response digital filtering operation, is characterized in that this microprocessor architecture mainly comprises one:
One working storage group, it has first working storage and second working storage, to point to a digital filtering coefficient and an input value of this storer respectively;
One summation circuit, it is value digital filtering coefficient and the input value pointed that reads this first working storage and second working storage, adopt arithmetic logic unit so that this digital filtering coefficient and input value are multiplied each other, and the value that will multiply each other is added up: and
One incrementor, it is to increase progressively computing in order to the value to this first and second working storage;
Wherein, when this summation circuit carries out accumulating operation, the input value that this totalizer read is kept in, this incrementor increases progressively the value of this first and second working storage, and return respectively and deposit, and this totalizer with the value of first and second working storage of having increased progressively be the address and certainly this storer read a digital filtering coefficient and an input value respectively, and be that the input value that the address will be kept in writes in this storer with the value of second working storage that increased progressively, carry out computing next time again.
Wherein this summation circuit comprises:
One input working storage, it is the input value that is read in order to store;
One coefficient working storage, it is the digital filtering coefficient that is read in order to store;
One interim working storage, it is temporary in order to the input value that will read to this input working storage; And
One takes advantage of/adds arithmetic element, and it is with arithmetic logic unit this input working storage and this coefficient working storage content to be carried out multiplying, and multiplied result is added to an output working storage.
2. the microprocessor architecture of realizing digital filtering operation according to claim 1 is characterized in that, wherein this to take advantage of/add arithmetic element be to carry out multiplying with cloth formula algorithm.
3. the microprocessor architecture that can realize digital filtering operation, it is to store a plurality of digital filtering coefficients in regular turn and treat that the storer of the input value of filtering carries out the finite response digital filtering operation, is characterized in that this microprocessor architecture mainly comprises one:
One working storage group, it has first working storage and second working storage, to point to a digital filtering coefficient and an input value of this storer respectively;
One summation circuit, it is value digital filtering coefficient and the input value pointed that reads this first working storage and second working storage, adopt arithmetic logic unit so that this digital filtering coefficient and input value are multiplied each other, and the value that will multiply each other is added up: and
One demultiplier, it is in order to computing that the value of this first and second working storage is successively decreased;
Wherein, when this summation circuit carries out accumulating operation, the input value that this totalizer read is kept in, this demultiplier successively decreases the value of this first and second working storage, and return respectively and deposit, and this totalizer with the value of first and second working storage of having successively decreased be the address and certainly this storer read a digital filtering coefficient and an input value respectively, and be that the input value that the address will be kept in writes in this storer with the value of second working storage that successively decreased, carry out computing next time again.
Wherein this summation circuit comprises:
One input working storage, it is the input value that is read in order to store:
One coefficient working storage, it is the digital filtering coefficient that is read in order to store;
One interim working storage, it is temporary in order to the input value that will read to this input working storage; And
One takes advantage of/adds arithmetic element, and it is with arithmetic logic unit the content of this input working storage and this coefficient working storage to be carried out multiplying, and multiplied result is added to an output working storage.
4. the microprocessor architecture of realizing digital filtering operation according to claim 3 is characterized in that, wherein this to take advantage of/add arithmetic element be to carry out multiplying with cloth formula algorithm.
5. realize the method for digital filtering operation with microprocessor for one kind, it is to store the digital filtering coefficient in regular turn and treat that the storer of the input value of filtering carries out the finite response digital filtering operation, is characterized in that this method mainly comprises following step one:
(A) read first digit filter factor and first input value;
(B) the digital filtering coefficient and the input value that are read are carried out multiplying, and it is added up;
(C) keep this input value;
(D) read next digital filtering coefficient and next input value:
(E) input value that is kept is moved to the memory location that stores this next one input value, and be back to step (B) to repeat, until the product accumulation of last digital filtering coefficient and last input value is finished.
6. the method that realizes digital filtering operation with microprocessor according to claim 5, it is characterized in that, wherein employed microprocessor has first and second working storage, and the value of this first and second working storage is pointed to this digital filtering coefficient and this input value respectively.
7. the method that realizes digital filtering operation with microprocessor according to claim 6, it is characterized in that, wherein step (A) is that the memory read that the value of this first working storage is pointed is taken to a coefficient working storage, and the memory read that the value of second working storage is pointed is taken to an input working storage;
8. according to claim 7ly realize it is characterized in that the method for digital filtering operation that wherein step (B) is that value with this coefficient working storage and this input working storage multiplies each other and is added to one and exports working storage with microprocessor.
9. according to claim 8ly realize it is characterized in that the method for digital filtering operation that wherein step (C) is that value with this input working storage is stored to an interim working storage with microprocessor.
10. the method that realizes digital filtering operation with microprocessor according to claim 9, it is characterized in that, wherein step (D) is that value with this first working storage adds a memory read pointed and is taken to this coefficient working storage, and the value of this first working storage increased progressively, and the value of this second working storage is added a memory read pointed be taken to this input value working storage, and the value of this this second working storage is increased progressively.
11. the method with microprocessor realization digital filtering operation according to claim 10 is characterized in that wherein step (E) is the value memory location pointed that the value of this interim working storage is deposited in this second working storage.
12. the method that realizes digital filtering operation with microprocessor according to claim 9, it is characterized in that, wherein step (D) is that value with this first working storage subtracts a memory read pointed and is taken to this coefficient working storage, and the value of this first working storage successively decreased, and the value of this second working storage is subtracted a memory read pointed be taken to this input value working storage, and the value of this second working storage is successively decreased.
13. the method with microprocessor realization digital filtering operation according to claim 12 is characterized in that wherein step (E) is the value memory location pointed that the value of this interim working storage is deposited in this second working storage.
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Granted publication date: 20031001 Termination date: 20131029 |