CN112289854A - Array substrate and preparation method thereof - Google Patents

Array substrate and preparation method thereof Download PDF

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Publication number
CN112289854A
CN112289854A CN202011136809.9A CN202011136809A CN112289854A CN 112289854 A CN112289854 A CN 112289854A CN 202011136809 A CN202011136809 A CN 202011136809A CN 112289854 A CN112289854 A CN 112289854A
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gate
distance
drain
electrode
source
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CN112289854B (en
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卢马才
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

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Abstract

The application provides an array substrate and a preparation method thereof, wherein the array substrate comprises a substrate; the first grid is arranged above the substrate; an active layer disposed over the first gate, the active layer including a channel region; a gate insulating layer disposed over the active layer; the second grid electrode is arranged above the grid electrode insulating layer and covers the channel region of the active layer; the source electrode and the drain electrode are arranged at two ends of the active layer; wherein the second gate and the first gate partially overlap in a direction along the active layer channel region. According to the array substrate, the deviation of the bottom grid in the horizontal direction relative to the top grid is designed, and the width of the bottom grid is changed relative to the width of the top grid, so that the current passing through a channel region in the array substrate is enhanced, and the threshold voltage drift and the saturation current fluctuation are reduced.

Description

Array substrate and preparation method thereof
Technical Field
The application relates to the technical field of display, in particular to an array substrate and a preparation method thereof.
Background
Thin Film Transistors (TFTs) are the main driving elements in flat panel display devices such as liquid crystal display devices, organic electroluminescent diode display devices, and micro-leds, and are directly related to the development of high performance flat panel display devices.
OLEDs and Micro LEDs, as current driven devices, require greater current throughput and better device stability and in-plane voltage (Vth) uniformity. A similar oxide semiconductor thin film transistor such as a top gate IGZO TFT has a high mobility and is relatively suitable as a current drive display circuit. However, the current passing through the channel region in the top gate-type IGZO TFT is relatively low, which affects the stability of the device in the subsequent operation.
When the double-gate design is adopted to improve the passing current of the TFT device, the influence of the bottom gate, the bottom gate and the insulating layer of the bottom gate on the TFT device needs to be considered in the common double-gate design, so that the process window is smaller; in addition, the double-gate design also influences the distribution characteristics of the channel resistance of the TFT and influences the appearance of an output characteristic curve.
Disclosure of Invention
The application provides an array substrate and a preparation method thereof, which are used for effectively enhancing current passing through a channel region in the array substrate and reducing threshold voltage drift and saturation current fluctuation.
In order to achieve the above effects, the technical solution provided by the present application is as follows:
an array substrate, comprising:
a substrate;
a first gate disposed over the substrate;
an active layer disposed over the first gate, the active layer including a channel region;
a gate insulating layer disposed over the active layer;
a second gate electrode disposed over the gate insulating layer, the second gate electrode covering the channel region of the active layer;
a source electrode and a drain electrode disposed at both ends of the active layer;
wherein the second gate and the first gate partially overlap in a direction along the active layer channel region.
In the array substrate, along the direction of the channel region of the active layer, the distance between the second gate and the source is smaller than the distance between the first gate and the source, and the distance between the second gate and the drain is smaller than the distance between the first gate and the drain.
In the array substrate, along the direction of the channel region of the active layer, the distance between the second gate and the source is greater than the distance between the first gate and the source, and the distance between the second gate and the drain is less than the distance between the first gate and the drain.
In the array substrate, along the direction of the channel region of the active layer, the distance between the second gate and the source is smaller than the distance between the first gate and the source, and the distance between the second gate and the drain is larger than the distance between the first gate and the drain.
In the array substrate, the active layer comprises a source contact region contacting with the source electrode and a drain contact region contacting with the drain electrode; the source contact region and the drain contact region are separated by the channel region; the source electrode and the drain electrode are both positioned between the active layer and the substrate; the source electrode, the drain electrode and the first grid electrode are arranged at the same layer and at intervals.
In the array substrate, along the direction of the channel region of the active layer, the distance between the second gate and the source is smaller than the distance between the first gate and the source, and the distance between the second gate and the drain is smaller than the distance between the first gate and the drain.
In the array substrate, along the direction of the channel region of the active layer, the distance between the second gate and the source is greater than the distance between the first gate and the source, and the distance between the second gate and the drain is less than the distance between the first gate and the drain.
In the array substrate, along the direction of the channel region of the active layer, the distance between the second gate and the source is smaller than the distance between the first gate and the source, and the distance between the second gate and the drain is larger than the distance between the first gate and the drain.
The application also provides a preparation method of the array substrate, which comprises the following steps:
step S10: providing a substrate, forming a first metal layer on the substrate, and carrying out patterning treatment on the first metal layer to form a first grid;
step S20: sequentially forming a buffer layer and an active layer on the first gate, wherein the active layer comprises a channel region, a source contact region and a drain contact region, and the source contact region and the drain contact region are separated by the channel region;
step S30: sequentially forming a gate insulating layer and a second metal layer on the active layer, and carrying out patterning treatment on the second metal layer and the gate insulating layer to form a second gate, wherein the second gate covers a channel region of the active layer;
step S40: forming an interlayer insulating layer on the second grid electrode, and carrying out patterning treatment on the interlayer insulating layer to form a via hole positioned on the source electrode contact area and a via hole positioned above the drain electrode contact area;
step S50: forming a source electrode in contact with the source electrode contact region and a drain electrode in contact with the drain electrode contact region on the interlayer insulating layer;
step S60: and sequentially forming a passivation layer and an electrode layer on the source electrode and the drain electrode.
In the preparation method of the application, the second grid and the first grid are partially overlapped in the direction along the channel region of the active layer.
Has the advantages that: according to the array substrate, the deviation of the bottom grid in the horizontal direction relative to the top grid is designed, and the width of the bottom grid is changed relative to the width of the top grid, so that the current passing through a channel region in the array substrate is enhanced, and the threshold voltage drift and the saturation current fluctuation are reduced.
Drawings
The technical solutions and other advantages of the present application will become apparent from the following detailed description of specific embodiments of the present application when taken in conjunction with the accompanying drawings.
Fig. 1 is a schematic view of a first structure of an array substrate according to an embodiment of the present disclosure;
fig. 2 is a schematic view of a second structure of an array substrate according to an embodiment of the present disclosure;
fig. 3 is a schematic view illustrating a third structure of an array substrate according to an embodiment of the present disclosure;
fig. 4 is a schematic view of a first structure of an array substrate according to a second embodiment of the present application;
fig. 5 is a schematic view of a second structure of an array substrate according to a second embodiment of the present application;
fig. 6 is a schematic structural diagram of a third structure of an array substrate according to the second embodiment of the present application;
fig. 7 is a flowchart illustrating steps of a method for manufacturing an array substrate according to an embodiment of the present disclosure;
fig. 8A to 8F are schematic structural diagrams of the array substrate provided in the embodiment of the present application in the manufacturing process.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and are not to be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact of the first and second features, or may comprise contact of the first and second features not directly but through another feature in between. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
The following disclosure provides many different embodiments or examples for implementing different features of the application. In order to simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize applications of other processes and/or use of other materials.
In the prior art, when a double-gate design is adopted to improve the current passing of a TFT (thin film transistor) device, the influence of a bottom gate, the bottom gate and an insulating layer of the bottom gate on the TFT device needs to be considered in the common double-gate design, so that a process window is small; in addition, the double-gate design also influences the distribution characteristics of the channel resistance of the TFT and influences the appearance of an output characteristic curve. Based on the above, the application provides an array substrate and a preparation method thereof, which can solve the above-mentioned defect.
The technical solution of the present application will now be described with reference to specific embodiments.
Example one
Referring to fig. 1, a first structural diagram of an array substrate according to an embodiment of the present application is shown.
In this embodiment, the array substrate includes a substrate 10; a first gate electrode 20, a buffer layer 30, an active layer 40, a gate insulating layer 50, a second gate electrode 60, an interlayer insulating layer 70, a source electrode 81, a drain electrode 82, a passivation layer 90, and an electrode layer 100 disposed over the substrate 10.
In the embodiment, the substrate 10 is a PI substrate, mainly made of polyimide, and the PI material can effectively improve the light transmittance.
In this embodiment, the first gate 20 is a bottom gate; the first gate 20 is disposed above the substrate 10; the material of the first gate electrode 20 includes, but is not limited to, molybdenum, aluminum, copper, indium zinc oxide, indium tin oxide, and the like.
In the present embodiment, the buffer layer 30 is disposed above the first gate 20; the material of the buffer layer 30 includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, etc. or a stack thereof.
In the present embodiment, the active layer 40 is disposed above the buffer layer 30; the material of the active layer 40 includes, but is not limited to, indium gallium zinc oxide, indium tin oxide, indium zinc oxide, aluminum zinc oxide, and the like.
The active layer 40 includes a channel region 420, a source contact region 410, and a drain contact region 430; the source contact region 410 and the drain contact region 430 are separated by the channel region 420.
In the present embodiment, the gate insulating layer 50 is disposed above the active layer 40; the material of the gate insulating layer 50 includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, and the like, or a stack thereof.
In this embodiment, the second gate 60 is a top gate; the second gate 60 is disposed on the gate insulating layer 50; the material of the second gate 60 includes, but is not limited to, molybdenum, aluminum, copper, indium zinc oxide, indium tin oxide, and the like.
In the present embodiment, the interlayer insulating layer 70 is disposed above the second gate electrode 60; the interlayer insulating layer 70 material includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, etc., or a stack thereof.
The interlayer insulating layer 70 is provided with a first via hole, and the first via hole is located above the source contact region 410 and the drain contact region 430 of the active layer 40.
In the present embodiment, the source electrode 81 and the drain electrode 82 are disposed above the interlayer insulating layer 70; the source electrode 81 and the drain electrode 82 are disposed at both ends of the active layer 40; the material of the source electrode 81 and the drain electrode 82 includes, but is not limited to, molybdenum, aluminum, copper, indium zinc oxide, indium tin oxide, and the like.
The source electrode 81 contacts the source contact region 410 through a first via hole on the interlayer insulating layer 70; the drain electrode 82 contacts the drain contact region 420 through a first via hole in the interlayer insulating layer 70.
In the present embodiment, the passivation layer 90 is disposed above the source electrode 81 and the drain electrode 82; the passivation layer 90 is made of a material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, etc., or a stack thereof.
A second via hole is formed in the passivation layer 90, and the second via hole is located above the source 81.
In the present embodiment, the electrode layer 100 is disposed above the passivation layer 90; the electrode layer 100 contacts the source electrode 81 through a second via hole on the passivation layer 90; the material of the electrode layer 100 includes, but is not limited to, molybdenum, aluminum, copper, indium zinc oxide, indium tin oxide, and the like.
In the present embodiment, the second gate electrode 60 and the first gate electrode 20 partially overlap in a direction along the channel region 420 of the active layer 40.
In the present embodiment, a distance between the second gate electrode 60 and the source electrode 81 is smaller than a distance between the first gate electrode 20 and the source electrode 81 along the channel region 420 of the active layer 40.
Specifically, in this embodiment, the distance between the second gate 60 and the source 81 and the distance between the first gate 20 and the source 81 are different from 1um to 4 um.
In the present embodiment, a distance between the second gate electrode 60 and the drain electrode 82 is smaller than a distance between the first gate electrode 20 and the drain electrode 82 along the channel region 410 of the active layer 40.
Specifically, in this embodiment, the distance between the second gate 60 and the drain 82 and the distance between the first gate 20 and the drain 82 are different from 1um to 4 um.
Referring to fig. 2, a second structure of an array substrate according to an embodiment of the present application is schematically illustrated.
In this embodiment, the structure of the array substrate is similar to/the same as the first schematic structure of the array substrate provided in the first embodiment, and please refer to the description of the array substrate in the above application, which is not repeated herein, and the difference between the two is only:
in the present embodiment, a distance between the second gate electrode 60 and the source electrode 81 is greater than a distance between the first gate electrode 20 and the source electrode 81 along the channel region 410 of the active layer 40.
Specifically, in this embodiment, the distance between the second gate 60 and the source 81 and the distance between the first gate 20 and the source 81 are different from 1um to 4 um.
In the present embodiment, a distance between the second gate electrode 60 and the drain electrode 82 is smaller than a distance between the first gate electrode 20 and the drain electrode 82 along the channel region 410 of the active layer 40.
Specifically, in this embodiment, the distance between the second gate 60 and the drain 82 and the distance between the first gate 20 and the drain 82 are different from 1um to 4 um.
Referring to fig. 3, a third structural diagram of an array substrate according to an embodiment of the present application is shown.
In this embodiment, the structure of the array substrate is similar to/the same as the first schematic structure of the array substrate provided in the first embodiment, and please refer to the description of the array substrate in the above application, which is not repeated herein, and the difference between the two is only:
in the present embodiment, a distance between the second gate electrode 60 and the source electrode 81 is smaller than a distance between the first gate electrode 20 and the source electrode 81 in a direction of a channel region of the active layer 40.
Specifically, in this embodiment, the distance between the second gate 60 and the source 81 and the distance between the first gate 20 and the source 81 are different from 1um to 4 um.
In the present embodiment, a distance between the second gate electrode 60 and the drain electrode 82 is greater than a distance between the first gate electrode 20 and the drain electrode 82 along the channel region 410 of the active layer 40.
Specifically, in this embodiment, the distance between the second gate 60 and the drain 82 and the distance between the first gate 20 and the drain 82 are different from 1um to 4 um.
In this embodiment, by designing the deviation of the first gate 20 with respect to the second gate 60 in the horizontal direction and the variation of the width of the first gate 20 with respect to the second gate 60, the current passing through the channel region 420 in the array substrate is enhanced, so as to reduce the threshold voltage drift and the saturation current fluctuation.
Example two
Referring to fig. 4, a first structural diagram of an array substrate according to a second embodiment of the present application is shown.
In this embodiment, the array substrate includes a substrate 10; a first gate electrode 20, a source electrode 81, and a drain electrode 82 disposed on the substrate 10; an interlayer insulating layer 70 disposed over the first gate electrode 20, the source electrode 81, and the drain electrode 82; an active layer 40 disposed over the interlayer insulating layer 70; a gate insulating layer 50 disposed over the active layer 40; a second gate electrode 60 disposed over the gate insulating layer 50; a passivation layer 90 disposed over the second gate electrode 60; and an electrode layer 100 disposed over the passivation layer 90.
In the present embodiment, the source electrode 81 and the drain electrode 82 are both located between the active layer 40 and the substrate 10; the source 81, the drain 82 and the first gate 20 are disposed at the same layer and at intervals; the first gate 20 is located between the source 81 and the drain 82.
In the present embodiment, a distance between the second gate electrode 60 and the source electrode 81 is smaller than a distance between the first gate electrode 20 and the source electrode 81 along the channel region 420 of the active layer 40.
Specifically, in this embodiment, the distance between the second gate 60 and the source 81 and the distance between the first gate 20 and the source 81 are different from 1um to 4 um.
In the present embodiment, a distance between the second gate electrode 60 and the drain electrode 82 is smaller than a distance between the first gate electrode 20 and the drain electrode 82 along the channel region 410 of the active layer 40.
Specifically, in this embodiment, the distance between the second gate 60 and the drain 82 and the distance between the first gate 20 and the drain 82 are different from 1um to 4 um.
Referring to fig. 5, a second structure of the array substrate according to the second embodiment of the present application is schematically illustrated.
In this embodiment, the structure of the array substrate is similar to/the same as the first schematic structure of the array substrate provided in the second embodiment, and please refer to the description of the array substrate in the above application, which is not repeated herein, and the difference between the two is only:
in the present embodiment, a distance between the second gate electrode 60 and the source electrode 81 is greater than a distance between the first gate electrode 20 and the source electrode 81 along the channel region 410 of the active layer 40.
Specifically, in this embodiment, the distance between the second gate 60 and the source 81 and the distance between the first gate 20 and the source 81 are different from 1um to 4 um.
In the present embodiment, a distance between the second gate electrode 60 and the drain electrode 82 is smaller than a distance between the first gate electrode 20 and the drain electrode 82 along the channel region 410 of the active layer 40.
Specifically, in this embodiment, the distance between the second gate 60 and the drain 82 and the distance between the first gate 20 and the drain 82 are different from 1um to 4 um.
Referring to fig. 6, a third structural diagram of an array substrate according to the second embodiment of the present application is shown.
In this embodiment, the structure of the array substrate is similar to/the same as the first schematic structure of the array substrate provided in the second embodiment, and please refer to the description of the array substrate in the above application, which is not repeated herein, and the difference between the two is only:
in the present embodiment, a distance between the second gate electrode 60 and the source electrode 81 is smaller than a distance between the first gate electrode 20 and the source electrode 81 in a direction of a channel region of the active layer 40.
Specifically, in this embodiment, the distance between the second gate 60 and the source 81 and the distance between the first gate 20 and the source 81 are different from 1um to 4 um.
In the present embodiment, a distance between the second gate electrode 60 and the drain electrode 82 is greater than a distance between the first gate electrode 20 and the drain electrode 82 along the channel region 410 of the active layer 40.
Specifically, in this embodiment, the distance between the second gate 60 and the drain 82 and the distance between the first gate 20 and the drain 82 are different from 1um to 4 um.
Referring to fig. 7, a flowchart of steps of a method for manufacturing an array substrate according to an embodiment of the present disclosure is shown.
In this embodiment, the method for manufacturing the array substrate includes:
step S10: a substrate 10 is provided, a first metal layer is formed on the substrate 10, and the first metal layer is patterned to form a first gate 20, as shown in fig. 8A.
The substrate 10 is a PI substrate, mainly made of polyimide, and the PI material can effectively improve the light transmittance.
The material of the first gate electrode 20 includes, but is not limited to, molybdenum, aluminum, copper, indium zinc oxide, indium tin oxide, and the like.
Step S20: a buffer layer 30 and an active layer 40 are sequentially formed on the first gate electrode 20, the active layer 40 includes a channel region 420, a source contact region 410, and a drain contact region 430, and the source contact region 410 and the drain contact region 430 are separated by the channel region 410, as shown in fig. 8B.
The material of the buffer layer 30 includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, etc. or a stack thereof.
The material of the active layer 40 includes, but is not limited to, indium gallium zinc oxide, indium tin oxide, indium zinc oxide, aluminum zinc oxide, and the like.
Step S30: a gate insulating layer 50 and a second metal layer are sequentially formed on the active layer 40, and the second metal layer and the gate insulating layer 50 are patterned to form a second gate electrode 60, where the second gate electrode 60 covers a channel region of the active layer 40, as shown in fig. 8C.
The material of the gate insulating layer 50 includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, and the like, or a stack thereof.
The material of the second gate 60 includes, but is not limited to, molybdenum, aluminum, copper, indium zinc oxide, indium tin oxide, and the like.
Step S40: an interlayer insulating layer 70 is formed on the second gate electrode 60, and the interlayer insulating layer 70 is patterned to form a first via hole over the source contact region 410 and a first via hole over the drain contact region 430, as shown in fig. 8D.
The interlayer insulating layer 70 material includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, etc., or a stack thereof.
Step S50: a source electrode 81 contacting the source contact region 410 and a drain electrode 82 contacting the drain contact region 430 are formed on the interlayer insulating layer 70, as shown in fig. 8E.
The material of the source electrode 81 and the drain electrode 82 includes, but is not limited to, molybdenum, aluminum, copper, indium zinc oxide, indium tin oxide, and the like.
The source electrode 81 and the drain electrode 82 are disposed at both ends of the active layer 40; the source electrode 81 contacts the source contact region 410 through a first via hole on the interlayer insulating layer 70; the drain electrode 82 contacts the drain contact region 430 through a first via hole in the interlayer insulating layer 70.
Step S60: a passivation layer 90 and an electrode layer 100 are sequentially formed on the source electrode 81 and the drain electrode 82 as shown in fig. 8F.
The passivation layer 90 is made of a material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, etc., or a stack thereof.
The material of the electrode layer 100 includes, but is not limited to, molybdenum, aluminum, copper, indium zinc oxide, indium tin oxide, and the like.
In step S60, the method further includes opening the passivation layer 90 to form a second via hole located above the source electrode 81; the electrode layer 100 contacts the source electrode 81 through a second via hole on the passivation layer 90.
In the present embodiment, the second gate electrode 60 and the first gate electrode 20 partially overlap in a direction along the channel region 420 of the active layer 40.
A distance between the second gate electrode 60 and the source electrode 81 and a distance between the first gate electrode 20 and the source electrode 82 are not equal in a channel region direction of the active layer 40; the distance between the second gate 60 and the drain 82 is not equal to the distance between the first gate 20 and the drain 82.
Wherein a distance between the second gate electrode 60 and the source electrode 81 is greater than or less than a distance between the first gate electrode 20 and the source electrode 82 in a channel region direction of the active layer 40; the distance between the second gate electrode 60 and the drain electrode 82 is greater or less than the distance between the first gate electrode 20 and the drain electrode 82 in the direction of the channel region of the active layer 40; the present embodiment does not limit this.
Specifically, in the present embodiment, a distance between the second gate electrode 60 and the source electrode 81 is smaller than a distance between the first gate electrode 20 and the source electrode 81 along the channel region direction of the active layer 40.
Specifically, in this embodiment, the distance between the second gate 60 and the source 81 and the distance between the first gate 20 and the source 81 are different from 1um to 4 um.
In the present embodiment, a distance between the second gate electrode 60 and the drain electrode 82 is greater than a distance between the first gate electrode 20 and the drain electrode 82 along the channel region 410 of the active layer 40.
Specifically, in this embodiment, the distance between the second gate 60 and the drain 82 and the distance between the first gate 20 and the drain 82 are different from 1um to 4 um.
In this embodiment, by designing the deviation of the first gate 20 with respect to the second gate 60 in the horizontal direction and the variation of the width of the first gate 20 with respect to the second gate 60, the current passing through the channel region 420 in the array substrate is enhanced, so as to reduce the threshold voltage drift and the saturation current fluctuation.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The array substrate and the manufacturing method thereof provided by the embodiments of the present application are described in detail above, and the principle and the implementation manner of the present application are explained in the present application by applying specific examples, and the description of the embodiments above is only used to help understanding the technical scheme and the core idea of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.

Claims (10)

1. An array substrate, comprising:
a substrate;
a first gate disposed over the substrate;
an active layer disposed over the first gate, the active layer including a channel region;
a gate insulating layer disposed over the active layer;
a second gate electrode disposed over the gate insulating layer, the second gate electrode covering the channel region of the active layer;
a source electrode and a drain electrode disposed at both ends of the active layer;
wherein the second gate and the first gate partially overlap in a direction along the active layer channel region.
2. The array substrate of claim 1, wherein a distance between the second gate and the source is smaller than a distance between the first gate and the source, and a distance between the second gate and the drain is smaller than a distance between the first gate and the drain in a direction of a channel region of the active layer.
3. The array substrate of claim 1, wherein a distance between the second gate and the source is greater than a distance between the first gate and the source, and a distance between the second gate and the drain is less than a distance between the first gate and the drain in a direction of a channel region of the active layer.
4. The array substrate of claim 1, wherein a distance between the second gate and the source is smaller than a distance between the first gate and the source, and a distance between the second gate and the drain is larger than a distance between the first gate and the drain in a direction of a channel region of the active layer.
5. The array substrate of claim 1, wherein the active layer comprises a source contact region in contact with the source electrode and a drain contact region in contact with the drain electrode; the source contact region and the drain contact region are separated by the channel region; the source electrode and the drain electrode are both positioned between the active layer and the substrate; the source electrode, the drain electrode and the first grid electrode are arranged at the same layer and at intervals.
6. The array substrate of claim 5, wherein a distance between the second gate and the source is smaller than a distance between the first gate and the source, and a distance between the second gate and the drain is smaller than a distance between the first gate and the drain in a direction of a channel region of the active layer.
7. The array substrate of claim 5, wherein a distance between the second gate and the source is greater than a distance between the first gate and the source, and a distance between the second gate and the drain is less than a distance between the first gate and the drain in a direction of a channel region of the active layer.
8. The array substrate of claim 5, wherein a distance between the second gate and the source is smaller than a distance between the first gate and the source, and a distance between the second gate and the drain is larger than a distance between the first gate and the drain in a direction of a channel region of the active layer.
9. A preparation method of an array substrate is characterized by comprising the following steps:
step S10: providing a substrate, forming a first metal layer on the substrate, and carrying out patterning treatment on the first metal layer to form a first grid;
step S20: sequentially forming a buffer layer and an active layer on the first gate, wherein the active layer comprises a channel region, a source contact region and a drain contact region, and the source contact region and the drain contact region are separated by the channel region;
step S30: sequentially forming a gate insulating layer and a second metal layer on the active layer, and carrying out patterning treatment on the second metal layer and the gate insulating layer to form a second gate, wherein the second gate covers a channel region of the active layer;
step S40: forming an interlayer insulating layer on the second grid electrode, and carrying out patterning treatment on the interlayer insulating layer to form a via hole positioned on the source electrode contact area and a via hole positioned above the drain electrode contact area;
step S50: forming a source electrode in contact with the source electrode contact region and a drain electrode in contact with the drain electrode contact region on the interlayer insulating layer;
step S60: and sequentially forming a passivation layer and an electrode layer on the source electrode and the drain electrode.
10. The method of claim 9, wherein the second gate and the first gate partially overlap in a direction along the active layer channel region.
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Publication number Priority date Publication date Assignee Title
JPH04150071A (en) * 1990-10-15 1992-05-22 Fuji Xerox Co Ltd High pressure thin film transistor
JP2844895B2 (en) * 1990-10-18 1999-01-13 富士ゼロックス株式会社 High breakdown voltage amorphous silicon thin film transistor
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