CN112289789A - Pnp triggered ggnmos structure - Google Patents

Pnp triggered ggnmos structure Download PDF

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Publication number
CN112289789A
CN112289789A CN202011232123.XA CN202011232123A CN112289789A CN 112289789 A CN112289789 A CN 112289789A CN 202011232123 A CN202011232123 A CN 202011232123A CN 112289789 A CN112289789 A CN 112289789A
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injection region
region
ggnmos
pnp
interdigital
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孙康明
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Chongqing Technology and Business Institute Chongqing Radio and TV University
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Chongqing Technology and Business Institute Chongqing Radio and TV University
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Priority to CN202011232123.XA priority Critical patent/CN112289789A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H01L27/027—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements specially adapted to provide an electrical current path other than the field effect induced current path
    • H01L27/0274—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements specially adapted to provide an electrical current path other than the field effect induced current path involving a parasitic bipolar transistor triggered by the electrical biasing of the gate electrode of the field effect transistor, e.g. gate coupled transistors

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The invention relates to the technical field of electrostatic protection of integrated circuits, in particular to a pnp-triggered GGNMOS structure, which comprises a GGNMOS structure based on a dynamic substrate and a substrate triggering technology, wherein the GGNMOS structure is a multi-interdigital parallel layout structure, two interdigital parts positioned in the middle of the multi-interdigital parallel layout structure are central interdigital parts, drain electrodes of the two central interdigital parts are connected together, a first N well region is arranged between the drain electrodes of the two central interdigital parts, a second N + injection region, a P + injection region and a third N + injection region are sequentially arranged in the first N well region in an isolated manner, the P + injection region is connected with an IO PAD, and the second N + injection region and the third N + injection region are connected with a power supply end VDD. The invention solves the problems of higher trigger voltage and non-uniform conduction of the traditional GGNMOS due to the inherent trigger mechanism and interdigital structure of the traditional GGNMOS.

Description

Pnp triggered ggnmos structure
Technical Field
The invention relates to the technical field of electrostatic protection of integrated circuits, in particular to a pnp-triggered ggnmos structure.
Background
As the feature size of CMOS processes scales down to the nanometer scale, the design and implementation of ESD protection circuits becomes increasingly challenging. Common ESD protection devices include resistors, diodes, bipolar transistors, MOS transistors, Silicon Controlled Rectifiers (SCR), and the like. Because the compatibility of the MOS tube and the CMOS process is good, the MOS tube is often adopted to construct a protection circuit. An NMOS transistor under CMOS process conditions has a parasitic N-P-N (source-P-substrate-drain) transistor that can sink a large amount of current when turned on. By utilizing the phenomenon, a protection circuit with a higher ESD withstand voltage value can be designed in a smaller area, wherein the most typical device structure is a Grounded-Gate NMOS (GGNMOS).
GGNMOS structures are widely used for on-chip ESD protection due to their inactive discharge mechanism and compatibility with CMOS processes. However, the conventional GGNMOS has a technical problem that the amplification factor is reduced as the base width is increased due to its inherent trigger mechanism and multi-finger cross-parallel structure, so that the Snap-back is not easily turned on. And as the number of fingers (NMOS cells) increases, it becomes difficult to uniformly turn on each finger (NMOS cell). Therefore, the GGNMOS structure has the defects of higher trigger voltage and non-uniform conduction. The substrate trigger technology and the dynamic substrate technology are common methods for solving the problems of too high trigger voltage and multi-finger non-uniform turn-on, as shown in fig. 1.
The substrate triggering technology means that a parasitic transistor in a substrate is turned on along with avalanche breakdown of a parasitic diode Dn, so that a triggering current for triggering a GGNMOS is supplied to the substrate. The dynamic substrate technology is that an additional N well is inserted between the source electrode of the outermost interdigital (NMOS unit) on the GGNMOS and the P + protection ring, and is connected to the IO PAD through an N + injection region. In case of ESD stress the extra N-well is biased to a higher voltage, which makes it necessary for the substrate current triggered to the P + guard ring to bypass this extra N-well, which helps to trigger all fingers (NMOS cells), especially the outermost fingers (NMOS cells), uniformly. However, the trigger current of the dynamic substrate based GGNMOS still comes from the avalanche breakdown of the diode Dn. This means that the trigger voltage Vt1Close to the transient breakdown voltage of the CMOS process used, the trigger voltage is still high, about 9.2V, and is therefore not suitable for ESD protection in low voltage CMOS processes.
Disclosure of Invention
The invention aims to provide a pnp triggered GGNMOS structure, which solves the problems of high trigger voltage and non-uniform conduction of the traditional GGNMOS due to the inherent trigger mechanism and interdigital structure of the traditional GGNMOS.
In order to achieve the above purpose, a pnp-triggered GGNMOS structure is provided, which includes a GGNMOS structure based on a dynamic substrate and a substrate triggering technology, the GGNMOS structure is a multi-finger parallel layout structure, two fingers located at the middle position in the multi-finger parallel layout structure are central fingers, drains of the two central fingers are connected together, a first N well region is arranged in the middle of the drains of the two central fingers, a second N + injection region 206, a P + injection region 103 and a third N + injection region 207 are sequentially isolated from each other in the first N well region, the P + injection region 103 is connected with an IO PAD, and the second N + injection region 206 and the third N + injection region 207 are connected with a power supply terminal VDD.
1. The first N well region is arranged to construct a longitudinal PNP transistor, a PNP transistor is formed between the second N + injection region 206 and the P + injection region 103, a PNP transistor is formed between the P + injection region 103 and the third N + injection region 207, the two PNP transistors are bilaterally symmetric, emitters of the two PNP transistors are connected to the P + injection region 103, the P + injection region 103 is connected to the IO PAD, and a base B (the second N + injection region 206 and the third N + injection region 207) of the PNP is connected to the power supply terminal VDD. The trigger mechanism of the GGNMOS is different from the avalanche breakdown trigger mechanism of a diode Dn in the traditional GGNMOS, the NMOS is triggered by utilizing the conduction current of the embedded PNP transistor, as long as the voltage of an emitter (IO PAD) of the PNP exceeds the voltage of a base (power supply end VDD) of the PNP transistor by 0.7V (which is far lower than the avalanche breakdown voltage of the diode Dn by 9.2V), the two PNP transistors are conducted, and the trigger current provided by the vertical PNP transistor can be directly injected into a substrate to trigger the NMOS, so the GGNMOS has lower trigger voltage. And because diode Dn avalanche breakdown voltage is 9.2V, may be higher than the operating voltage of protection circuit, therefore the avalanche breakdown trigger mechanism of traditional GGNMOS may cause the damage to the protection circuit, and the trigger voltage of this scheme is 0.7V, is far less than electrostatic voltage and diode Dn avalanche breakdown voltage, and trigger condition is lower more easily to trigger, also can not cause the damage to the protection circuit, consequently can provide more protection effect for the protection circuit.
2. The introduction of the first N-well region enables the establishment of an SCR path between the central finger and the substrate contact, resulting in an enhanced ability of the GGNMOS structure to handle ESD currents.
3. The application of the dynamic substrate technology to the GGNMOS structure of the scheme is beneficial to uniformly triggering all the fingers on the GGNMOS structure, particularly the fingers on the outermost side.
Further, the multi-finger parallel layout structure is centrosymmetric with respect to the P + implantation region 103, two central fingers are respectively a first central finger and a second central finger which are centrosymmetric with respect to the P + implantation region 103, drains of the first central finger and the second central finger are a first N + implantation region 203, a source of the first central finger is a fourth N + implantation region 202, and a source of the second central finger is a fifth N + implantation region 204.
Further, a P + protection ring 101 is arranged at the edge of the multi-interdigital parallel layout structure, and the P + protection ring 101 is grounded.
The arrangement of the P + guard ring 101 can effectively improve the fringe electric field and improve the breakdown voltage of the device.
Further, a second N well region and a plurality of P well regions are sequentially isolated between the P + guard ring 101 and the fourth N + injection region 202; a third N well region and a plurality of P well regions are sequentially arranged between the P + guard ring 101 and the fifth N + injection region 204 in an isolated manner; the P well region corresponds to the interdigital in the multi-interdigital parallel layout structure, and an nmos unit is arranged in the P well region; a sixth N + injection region 201 is arranged in the second N well region, a seventh N + injection region 205 is arranged in the third N well region, and the sixth N + injection region 201 and the seventh N + injection region 205 are both connected to the IO PAD.
The arrangement of the second and third nwell regions is such that, in case of ESD stress, the second and third nwell regions are biased to a higher voltage, which makes it necessary for the current triggered by the substrate to the P + guard ring to bypass the second and third nwell regions, which helps to uniformly trigger all the fingers (NMOS cells), especially the outermost fingers (NMOS cells), in the multi-finger parallel layout structure.
Furthermore, the isolation structures on the GGNMOS structure are all STI structures.
The STI structure is a process for manufacturing isolation regions between active regions of transistors on a substrate, and can effectively ensure that N-type and P-type doped regions can be thoroughly separated. Compared with the traditional intrinsic oxidation isolation technology, the shallow trench isolation technology can reduce the leakage current between electrodes and bear larger breakdown voltage.
Further, SAB silicide layers 301 are provided on both the gate and drain of the nmos cell.
The SAB silicide layer 301 reduces the resistivity of the polysilicon on the gate.
Drawings
FIG. 1 is a longitudinal cross-sectional view of a GGNMOS structure based on dynamic substrate technology;
FIG. 2 is a longitudinal cross-sectional view of a pnp-triggered ggnmos structure of the present invention;
FIG. 3 is a partial top view of a multi-interdigitated GGNMOS structure of the present invention;
FIG. 4 is a TLP test result comparison graph of the eight-finger GGMOS structure of the present invention and the existing eight-finger GGMOS structure.
Detailed Description
The following is further detailed by way of specific embodiments:
reference numerals in the drawings of the specification include: p + guard ring 101, sixth N + implant 201, fourth N + implant 202, first N + implant 203, fifth N + implant 204, seventh N + implant 205, second N + implant 206, third N + implant 207, P + implant 103, SAB silicide 301.
Examples
A pnp triggered GGNMOS structure is shown in figures 1 and 2 and comprises a GGNMOS structure based on a dynamic substrate and substrate triggering technology, wherein the GGNMOS structure is a multi-interdigital parallel layout structure, and a substrate of the GGNMOS structure is a P-type substrate. The multi-interdigital parallel layout structure comprises a plurality of interdigital fingers which are connected in parallel, in the embodiment, the multi-interdigital parallel layout structure is formed by connecting eight interdigital fingers in parallel, the eight interdigital fingers are arranged in parallel on the length of a channel of an NMOS unit, and the multi-interdigital parallel layout structure is shown in figure 3. Two interdigital parts (a fourth interdigital part and a fifth interdigital part) positioned in the middle position in the multi-interdigital parallel layout structure are central interdigital parts, the drain electrodes of the two central interdigital parts are connected together, a first N well region is arranged in the middle of the drain electrodes of the two central interdigital parts, and a second N + injection region 206, a P + injection region 103 and a third N + injection region 207 are sequentially and isolatedly arranged in the first N well region.
The multi-finger parallel layout structure is centrosymmetric about the P + injection region 103, two central fingers are respectively a first central finger and a second central finger which are centrosymmetric about the P + injection region 103, the drains of the first central finger and the second central finger are a first N + injection region 203, the source of the first central finger is a fourth N + injection region 202, and the source of the second central finger is a fifth N + injection region 204.
As shown in fig. 1, a P + guard ring 101 is disposed at an edge of the multi-finger parallel layout structure, and the P + guard ring 101 is grounded. A second N well region (N-well), three P well regions (not shown in fig. 1), a central P well region (P-well), three P well regions (not shown in fig. 1), and a third N well region (N-well) are sequentially disposed on the P-type substrate from left to right. The STI structure is arranged outside the P + guard ring 101 to be isolated from the outside. STI structures are arranged between the adjacent P + guard ring 101, the second N well region, the plurality of P well regions, the central P well region, the plurality of P well regions, the third N well region and the P + guard ring 101 for isolation.
A sixth N + injection region 201 is arranged in the second nwell region, a seventh N + injection region 205 is arranged in the third nwell region, and both the sixth N + injection region 201 and the seventh N + injection region 205 are connected to the IO PAD.
As shown in fig. 2, after the first N well region is inserted into the center of the first N + injection region 203, the first N + injection region 203 is an annular N + injection region, and the central P well region (P-well) is divided into a first P well region, a first N well region and a second P well region. STI structures are arranged between the first P well region, the first N well region and the second P well region for isolation. STI structures are arranged between the second N + implantation region 206, the P + implantation region 103 and the third N + implantation region 207 for isolation.
Three P-well regions (not shown in fig. 2) are disposed between the second N-well region and the first P-well region, three P-well regions (not shown in fig. 2) are disposed between the second P-well region and the third N-well region, and each P-well region has an NMOS unit therein. The first P-well region corresponds to a first center finger (i.e., a fourth finger), the source of the first center finger is a fourth N + implant region 202, and the drain of the first center finger is a first N + implant region 203. The second P-well region corresponds to the second center finger (i.e., the fifth finger), the source is the fifth N + implant region 204, and the drain is the first N + implant region 203.
On the left half part of the P-type substrate, three P well regions between the second N well region and the first P well region respectively correspond to a first interdigital, a second interdigital and a third interdigital of the multi-interdigital parallel layout structure; on the right half part of the P-type substrate, three P well regions of the second P well region and the third N well region respectively correspond to a sixth interdigital, a seventh interdigital and an eighth interdigital of the multi-interdigital parallel layout structure.
The source and the gate of each NMOS unit in the GGNMOS structure are all grounded, and SAB silicification layers 301 are arranged on the gate and the drain of each NMOS unit in each P well region.
The second N + injection region 206 and the third N + injection region 207 are connected to a power supply terminal VDD, and the P + injection region 103, the sixth N + injection region 201 of the second N-well region, and the seventh N + injection region 205 of the third N-well region are all connected to an IO PAD.
The specific implementation process is as follows:
after a first N well region is arranged in the drain (a first N + injection region 203) after the first center finger and the second center finger are connected, and a second N + injection region 206, a P + injection region 103 and a third N + injection region 207 are arranged in the middle of the first N well region, 2 vertical PNP transistors are constructed, wherein a PNP transistor is formed between the second N + injection region 206 and the P + injection region 103, another PNP transistor is formed between the P + injection region 103 and the third N + injection region 207, the two PNP transistors are bilaterally symmetrical and have emitters connected to the P + injection region 103, the P + injection region 103 is connected to an IO PAD, and the base B (the second N + injection region 206 and the third N + injection region 207) of the PNP is connected to the power supply terminal VDD.
According to the scheme, the built PNP transistor conduction current is used for triggering the NMOS, as long as the voltage of the PNP emitter (IO PAD) exceeds the voltage of the base (power supply end VDD) of the PNP transistor by 0.7V (which is far lower than the diode Dn avalanche breakdown voltage by 9.2V), the two PNP transistors are conducted, the trigger current provided by the longitudinal PNP transistor can be directly injected into the P-type substrate to trigger each NMOS unit, and therefore the GGNMOS has a low trigger voltage.
The introduction of the first nwell region enables the establishment of an SCR path between the central finger (fourth finger and fifth finger) and the substrate contact. As shown in fig. 2, a P + implantation region 103, a first N well region, a P-type substrate, and a fourth N + implantation region 202 form a PNPN junction, and the P + implantation region 103, the first N well region, the P-type substrate, and a fifth N + implantation region 204 form a PNPN junction, so that two SCR paths are established, so that the capability of the GGNMOS structure to process ESD current can be mainly NMOS and secondarily by SCR paths, thereby enhancing the capability of the GGNMOS structure to process ESD current as a whole.
After the trigger current provided by the vertical PNP transistor is directly injected into the P-type substrate, due to the dynamic substrate technology, an additional second nwell region is inserted between the source of the outermost finger (first finger) on the GGNMOS and the P + guard ring 101, and the sixth N + injection region 201 of the second nwell region is connected to the IO PAD. In case of ESD stress the additional second nwell region is biased to a higher voltage, which makes the current triggered by the P-type substrate to the P + guard ring have to bypass this additional second nwell region, increasing the path for the current to flow, which helps to trigger the first, second, third and fourth fingers evenly, especially the outermost finger (first finger). The third nwell region is identical to the second nwell region in that the current triggered by the P-type substrate to the P + guard ring must also bypass this additional third nwell region, which helps to trigger the fifth finger, the sixth finger, the seventh finger and the eighth finger uniformly, especially the outermost finger (eighth finger).
The results of testing the conventional eight finger GGNMOS and the inventive eight finger GGNMOS with a transmission line pulse generator (TLP) are shown in fig. 4. The trigger voltage of the GGNMOS proposed by this scheme is 5.1V in the power-up case (VDD ═ 1.8V) and 3.5V in the power-down case, while the conventional dynamic GGNMOS has a larger trigger voltage (6.3V) because its triggering is controlled by avalanche breakdown of the P-sub/N + junction. This indicates that the embedded PNP conducts before the diode Dn. In fact, under ESD stress, the new GGNMOS is a fully turned on device, even without involving the avalanche breakdown mechanism of Dn, as long as the inserted PNP can provide the required trigger current to turn on the parasitic NPN transistor. Under power-on conditions, the base of the PNP is pulled up to VDD, and the PNP can be conducted only when the emitter voltage Ve of the PNP is larger than VDD + 0.7V. Therefore, the GGNMOS of the scheme has lower trigger voltage.
The foregoing is merely an example of the present invention, and common general knowledge in the field of known specific structures and characteristics is not described herein in any greater extent than that known in the art at the filing date or prior to the priority date of the application, so that those skilled in the art can now appreciate that all of the above-described techniques in this field and have the ability to apply routine experimentation before this date can be combined with one or more of the present teachings to complete and implement the present invention, and that certain typical known structures or known methods do not pose any impediments to the implementation of the present invention by those skilled in the art. It should be noted that, for those skilled in the art, without departing from the structure of the present invention, several changes and modifications can be made, which should also be regarded as the protection scope of the present invention, and these will not affect the effect of the implementation of the present invention and the practicability of the patent. The scope of the claims of the present application shall be determined by the contents of the claims, and the description of the embodiments and the like in the specification shall be used to explain the contents of the claims.

Claims (6)

1. The utility model provides a pnp triggered GGNMOS structure, includes the GGNMOS structure based on dynamic substrate and substrate trigger technique, the GGNMOS structure is many fingers parallel layout structure, two fingers that lie in the intermediate position in the many fingers parallel layout structure are central finger, and the drain electrode of two central fingers links together its characterized in that: a first N well region is arranged between the drains of the two central fingers, a second N + injection region 206, a P + injection region 103 and a third N + injection region 207 are sequentially arranged in the first N well region in an isolated manner, the P + injection region 103 is connected with an IO PAD, and the second N + injection region 206 and the third N + injection region 207 are connected with a power supply end VDD.
2. A pnp-triggered ggnmos structure according to claim 1, characterized in that: the multi-finger parallel layout structure is centrosymmetric about the P + injection region 103, two central fingers are respectively a first central finger and a second central finger which are centrosymmetric about the P + injection region 103, the drains of the first central finger and the second central finger are a first N + injection region 203, the source of the first central finger is a fourth N + injection region 202, and the source of the second central finger is a fifth N + injection region 204.
3. A pnp-triggered ggnmos structure according to claim 2, characterized in that: the edge of the multi-interdigital parallel layout structure is provided with a P + protection ring 101, and the P + protection ring 101 is grounded.
4. A pnp-triggered ggnmos structure according to claim 3, wherein: a second N well region and a plurality of P well regions are sequentially arranged between the P + guard ring 101 and the fourth N + injection region 202 in an isolated manner; a third N well region and a plurality of P well regions are sequentially arranged between the P + guard ring 101 and the fifth N + injection region 204 in an isolated manner; the P well region corresponds to the interdigital in the multi-interdigital parallel layout structure, and an nmos unit is arranged in the P well region; a sixth N + injection region 201 is arranged in the second N well region, a seventh N + injection region 205 is arranged in the third N well region, and the sixth N + injection region 201 and the seventh N + injection region 205 are both connected to the IO PAD.
5. A pnp-triggered ggnmos structure according to claim 1 or 4, wherein: and the isolation structures on the GGNMOS structure are all STI structures.
6. A pnp-triggered ggnmos structure according to claim 4, wherein: the gate and drain of the nmos cell are both provided with an SAB suicide layer 301.
CN202011232123.XA 2020-11-06 2020-11-06 Pnp triggered ggnmos structure Pending CN112289789A (en)

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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103151351A (en) * 2013-03-29 2013-06-12 西安电子科技大学 Self substrate trigger ESD (Electro-Static Discharge) protecting device using dynamic substrate resistance technology, and application

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103151351A (en) * 2013-03-29 2013-06-12 西安电子科技大学 Self substrate trigger ESD (Electro-Static Discharge) protecting device using dynamic substrate resistance technology, and application

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
SUN,KM等: "《A PNP-triggered dynamic substrate GGNMOS with improved performances》", 《SOLID-STATE ELECTRONICS》 *

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Application publication date: 20210129