CN112289740B - Method for manufacturing through hole - Google Patents
Method for manufacturing through hole Download PDFInfo
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- CN112289740B CN112289740B CN202011174800.7A CN202011174800A CN112289740B CN 112289740 B CN112289740 B CN 112289740B CN 202011174800 A CN202011174800 A CN 202011174800A CN 112289740 B CN112289740 B CN 112289740B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/101—Forming openings in dielectrics
Abstract
The invention discloses a method for manufacturing a through hole, which comprises the following steps: step one, forming a through hole opening, wherein the through hole opening exposes the surface of the semiconductor substrate at the bottom of the interlayer film; step two, carrying out a pre-through hole cleaning process to remove a natural oxide layer at the bottom of an opening of the through hole, wherein the step two comprises the following steps: step 21, growing a first oxide layer; step 22, performing first oxide layer etching by adopting a sputtering etching process, wherein after the first oxide layer etching is completed, the residual thickness of the superimposed layer of the oxide layer on the bottom surface of the through hole opening is smaller than the thickness of the first oxide layer left on the side surface; and step 23, performing second oxide layer etching by adopting a SiCoNi etching process, wherein the etching thickness of the oxide layer by the second oxide layer etching is equal to the growth thickness of the first oxide layer. The invention can simultaneously avoid the front cleaning process of the through hole to generate loss on the surface of the semiconductor substrate at the bottom of the through hole opening to enlarge the critical dimension of the through hole opening, expand the process window and improve the product performance.
Description
Technical Field
The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for manufacturing a via hole.
Background
As shown in fig. 1A to 1C, a schematic device structure in each step of a conventional method for manufacturing a through hole is shown; the conventional method for manufacturing the through hole comprises the following steps:
step one, as shown in fig. 1A, a via opening 104 is formed through the interlayer film 103 by performing photolithography, and the via opening 104 exposes the surface of the semiconductor substrate 101 at the bottom of the interlayer film 103.
Typically, the semiconductor substrate 101 comprises a silicon substrate.
The material of the interlayer film 103 is silicon dioxide.
A semiconductor device is formed on the semiconductor substrate 101, and the tops of the gate structure, the source region and the drain region of the semiconductor device are all formed with the corresponding via openings 104.
The semiconductor device includes an NMOS and a PMOS.
The process node of the semiconductor device is below 14 nm. In process nodes below 14nm, in order to improve the performance of the device, such as the carrier mobility of the channel region, an embedded epitaxial layer 102 structure is typically formed, for example: an embedded SiP epitaxial layer is formed in the source region or the drain region of the NMOS; and forming an embedded SiGe epitaxial layer in the source region or the drain region of the PMOS.
After the first step is completed, the step of carrying out amorphization ion implantation is further included before the second step is started. Amorphization ion implantation can also be prevented from being performed after the sputter etching process in the subsequent step two.
Step two, performing a pre-via cleaning process to remove the natural oxide layer on the surface of the semiconductor substrate 101 at the bottom of the via opening 104, including the following sub-steps:
step 21, as shown in fig. 1B, a first oxide layer etching is performed by using a sputter etching process, where the sputter etching process is shown by arrow lines corresponding to the marks 106, and the first oxide layer etching etches the natural oxide layer on the bottom surface of the through hole opening 104.
Step 22, as shown in fig. 1C, performing a second oxide layer etching, where the second oxide layer etching uses chemical cleaning including NF3 and NH3 by using reactants, and the second oxide layer etching etches the remaining natural oxide layer on the bottom surface of the via opening 104, so as to ensure that the natural oxide layer on the bottom surface of the via opening 104 is etched cleanly.
Typically, to ensure clean etching of the native oxide layer, the sputter etching process and the chemical cleaning of the second oxide layer are set to be equal, e.g., the etching thickness is equalThe total etching thickness is-> The thickness of the autothermal oxide layer is generally +.>In this way, the sputtering etching process can easily etch through the natural oxide layer at the bottom of the via opening 104 and generate a loss on the surface of the semiconductor substrate 101, that is, the thickness d101 of the embedded epitaxial layer 102 can be reduced. The chemical cleaning of the second oxide etching will make the interlayer film of the via opening 104Loss occurs, which increases the width d102 of the via opening 104, which increases the critical dimension of the via opening 104.
The method also comprises the steps of:
step three, depositing and forming a Ti layer and a TiN layer;
step four, performing an annealing process;
depositing a tungsten layer, wherein the tungsten layer completely fills the through hole opening 104;
and step six, removing the tungsten layer, the TiN layer and the Ti layer outside the through hole opening 104 by performing a metal chemical mechanical polishing process, wherein the through hole is formed by the Ti layer, the TiN layer and the tungsten layer filled in the through hole opening 104.
Disclosure of Invention
The invention aims to provide a through hole manufacturing method, which can simultaneously avoid the phenomenon that the surface of a semiconductor substrate at the bottom of an opening of a through hole is worn by a cleaning process before the through hole to enlarge the critical dimension of the opening of the through hole, enlarge a process window and improve the product performance.
In order to solve the technical problems, the manufacturing method of the through hole provided by the invention comprises the following steps:
and step one, photoetching and etching to form a through hole opening penetrating through the interlayer film, wherein the through hole opening exposes the surface of the semiconductor substrate at the bottom of the interlayer film.
Step two, a pre-through hole cleaning process is carried out to remove a natural oxide layer on the surface of the semiconductor substrate at the bottom of the through hole opening, and the method comprises the following sub-steps:
and step 21, growing a first oxide layer, wherein the first oxide layer covers the bottom surface and the side surface of the through hole opening.
Step 22, performing first oxide layer etching by using a sputtering etching process, wherein the first oxide layer etching etches the natural oxide layer on the bottom surface of the through hole opening and the superimposed layer of the first oxide layer, and the first oxide layer is arranged to prevent the first oxide layer etching from generating etching loss on the surface of the semiconductor substrate at the bottom of the through hole opening.
After the first oxide layer is etched, the residual thickness of the superimposed layer on the bottom surface of the through hole opening is smaller than the thickness of the first oxide layer remaining on the side surface of the through hole opening.
And step 23, performing second oxide layer etching, wherein the second oxide layer etching adopts chemical cleaning of reactants including NF3 and NH3, and the thickness of the oxide layer etched by the second oxide layer etching is equal to that of the first oxide layer grown in step 21, so that the residual part of the superimposed layer on the bottom surface of the through hole opening and the first oxide layer on the side surface of the through hole opening are removed, and the width of the through hole opening is maintained.
In a further improvement, in step 21, the first oxide layer is also formed on a surface outside the via opening.
A further improvement is that the first oxide layer on the surface outside the via opening is removed in the first oxide layer etch of step 22 or in combination with the first oxide layer etch of step 22 and the second oxide layer etch of step 23.
In a further improvement, in step 22, the first oxide layer etching does not etch the first oxide layer on the side surface of the through hole opening, and after the first oxide layer etching is completed, all the first oxide layer on the side surface of the through hole opening remains.
A further improvement is that the semiconductor substrate comprises a silicon substrate.
In a further improvement, the interlayer film is made of silicon dioxide.
A further improvement is that the material of the natural oxide layer and the first oxide layer is silicon dioxide.
A further improvement is that the thickness of the natural oxide layer before the through hole cleaning process is carried out is
A further improvement is that the thickness of the first oxide layer is
A further improvement is that the first oxide layer is grown using an ALD process.
In a further improvement, in step 22, the etching thickness of the first oxide layer etching is
In step 23, the etching thickness of the second oxide layer is
In a further improvement, a semiconductor device is formed on the semiconductor substrate, and the corresponding through hole openings are formed on the tops of the gate structure, the source region and the drain region of the semiconductor device.
A further improvement is that the semiconductor device comprises an NMOS and a PMOS.
Further improvement is that the process node of the semiconductor device is below 14 nm.
A further improvement is that an embedded SiP epitaxial layer is formed in the source region or the drain region of the NMOS;
and forming an embedded SiGe epitaxial layer in the source region or the drain region of the PMOS.
Further improvement is that the method further comprises the steps of:
step three, depositing and forming a Ti layer and a TiN layer;
step four, performing an annealing process;
depositing a tungsten layer, wherein the tungsten layer completely fills the through hole opening;
and step six, removing the tungsten layer, the TiN layer and the Ti layer outside the through hole opening by a metal chemical mechanical polishing process, and forming the through hole by the Ti layer, the TiN layer and the tungsten layer filled in the through hole opening.
Further improvement is that after the first step is completed, the step of amorphization ion implantation is further included before the second step is started.
According to the invention, in the pre-through hole cleaning process after the through hole opening is formed, the step of forming the first oxide layer is added, then the first oxide layer etching adopting the sputtering etching process and the second oxide layer etching adopting the chemical cleaning of reactants including NF3 and NH3 are correspondingly arranged according to the introduction of the first oxide layer, in the first oxide layer etching, the characteristics that only the bottom surface of the through hole opening is etched but the side surface is not etched by utilizing the sputtering etching process are utilized, and most of the oxide layers on the bottom surface of the through hole opening, namely the superimposed layers of the first oxide layers, can be naturally oxidized and removed in the first oxide layer etching; in the second oxide layer etching, the etching thickness is directly set according to the growth thickness of the first oxide layer, most of the oxide layer on the bottom surface of the through hole opening is removed before the second oxide layer etching starts, so that the first oxide layer on the side surface of the through hole opening can be removed when the etching thickness of the second oxide layer etching is equal to the growth thickness of the first oxide layer, the oxide layer on the bottom surface of the through hole opening is removed, the chemical cleaning of the second oxide layer etching does not generate loss on the surface of the semiconductor substrate, the sputtering etching process does not generate loss on the surface of the semiconductor substrate due to the existence of the first oxide layer in the first oxide layer etching, and finally the invention can realize that the loss is not generated on the surface of the semiconductor substrate of the through hole opening, thus ensuring and improving the performance of the device.
Meanwhile, in the second oxide layer etching, the chemical cleaning process of the second oxide layer etching only etches the first oxide layer on the side surface, and the chemical cleaning of the second oxide layer etching is stopped after the first oxide layer is consumed, so that the chemical cleaning of the second oxide layer etching does not generate loss on an interlayer film on the side surface of the through hole opening, the width of the through hole opening is not influenced, and finally, the critical size of the through hole opening is not influenced, wherein the critical size of the through hole opening corresponds to the minimum width of the through hole opening.
Drawings
The invention is described in further detail below with reference to the attached drawings and detailed description:
FIGS. 1A-1C are schematic views of a device structure at various steps in a conventional via fabrication method;
FIG. 2 is a flow chart of a method of fabricating a via in accordance with an embodiment of the present invention;
fig. 3A to 3D are schematic device structures at each step of the method for manufacturing a through hole according to the embodiment of the present invention.
Detailed Description
FIG. 2 is a flow chart of a method of fabricating a via according to an embodiment of the present invention; fig. 3A to 3D are schematic views of device structures in steps of a method for manufacturing a through hole according to an embodiment of the present invention; the manufacturing method of the through hole comprises the following steps:
step one, as shown in fig. 3A, a via opening 4 is formed through the interlayer film 3 by performing photolithography, and the via opening 4 exposes the surface of the semiconductor substrate 1 at the bottom of the interlayer film 3.
In the embodiment of the present invention, the semiconductor substrate 1 includes a silicon substrate.
The material of the interlayer film 3 is silicon dioxide.
A semiconductor device is formed on the semiconductor substrate 1, and the tops of the gate structure, the source region and the drain region of the semiconductor device are all formed with the corresponding through hole openings 4.
The semiconductor device includes an NMOS and a PMOS.
The process node of the semiconductor device is below 14 nm. In process nodes below 14nm, in order to improve the performance of the device, such as the carrier mobility of the channel region, an embedded epitaxial layer 2 structure is typically formed, for example: an embedded SiP epitaxial layer is formed in the source region or the drain region of the NMOS; and forming an embedded SiGe epitaxial layer in the source region or the drain region of the PMOS.
After the first step is completed, the step of carrying out amorphization ion implantation is further included before the second step is started.
Step two, performing a pre-through-hole cleaning process to remove a natural oxide layer on the surface of the semiconductor substrate 1 at the bottom of the through-hole opening 4, including the following sub-steps:
step 21, as shown in fig. 3B, a first oxide layer 5 is grown, where the first oxide layer 5 covers the bottom surface and the side surface of the via opening 4.
In the embodiment of the present invention, the material of the natural oxide layer and the material of the first oxide layer 5 are both silicon dioxide.
The first oxide layer 5 is grown using an ALD process. The first oxide layer 5 is also formed on the surface outside the via opening 4.
Step 22, as shown in fig. 3C, performing a first oxide layer etching by using a sputter etching process, where the sputter etching process is shown by arrow lines corresponding to the marks 6, and the first oxide layer etching etches the natural oxide layer on the bottom surface of the through hole opening 4 and the superimposed layer of the first oxide layer 5, and by setting the first oxide layer 5, the first oxide layer etching is prevented from generating etching loss on the surface of the semiconductor substrate 1 at the bottom of the through hole opening 4. That is, the thickness d1 of the embedded epitaxial layer 2 corresponding to fig. 3A can be maintained in the corresponding fig. 3C after the completion of step 22.
The sputter etching process also causes rounding of the pattern top of the interlayer film 3 on both sides of the via opening, i.e., a rounded structure as shown by reference numeral 7. The rounded structure 7 can be removed in a subsequent cmp process, so that it does not affect the performance of the device.
After the first oxide layer etching is completed, the remaining thickness of the superimposed layer on the bottom surface of the via opening 4 is smaller than the thickness of the first oxide layer 5 remaining on the side surface of the via opening 4.
In the embodiment of the present invention, the etching thickness of the first oxide layer etching is greater than or equal to the growth thickness of the first oxide layer 5, so that the first oxide layer 5 on the surface outside the via opening 4 is removed in the first oxide layer etching in step 22. The method can also be as follows: the first oxide etch has an etch thickness that is less than the grown thickness of the first oxide layer 5, such that the first oxide layer 5 on the surface outside the via opening 4 needs to be removed in combination with the first oxide etch of step 22 and the second oxide etch of subsequent step 23.
The first oxide layer etching does not etch the first oxide layer 5 on the side surface of the through hole opening 4, and after the first oxide layer etching is completed, all the first oxide layer 5 on the side surface of the through hole opening 4 remains.
Step 23, as shown in fig. 3D, performing a second oxide layer etching, where the chemical cleaning of the reactants including NF3 and NH3 is used in the second oxide layer etching, where the thickness of the oxide layer etched by the second oxide layer etching is equal to the thickness of the first oxide layer 5 grown in step 21, so that the remaining portion of the superimposed layer on the bottom surface of the via opening 4 and the first oxide layer 5 on the side surface of the via opening 4 are removed, and at the same time, the width of the via opening 4 is maintained, that is, the width D2 of the corresponding via opening 4 in fig. 3A can be maintained in fig. 3D after step 23 is completed.
The etching selectivity ratio of the chemical cleaning of the second oxide layer etching to the oxide layer and the silicon is larger than 80:1, so that the chemical cleaning of the second oxide layer etching can not generate loss on the surface of the semiconductor substrate 1, namely, the loss on silicon, siGe and SiP can be ignored, and therefore, the loss on the surface of the semiconductor substrate 1 can be avoided by ensuring that the sputtering etching process of the step 22 can not generate loss on the surface of the semiconductor substrate 1 in the embodiment of the invention.
The method also comprises the steps of:
step three, depositing and forming a Ti layer and a TiN layer;
step four, performing an annealing process;
depositing a tungsten layer, wherein the tungsten layer completely fills the through hole opening 4;
and step six, removing the tungsten layer, the TiN layer and the Ti layer outside the through hole opening 4 by performing a metal chemical mechanical polishing process, and forming the through hole by the Ti layer, the TiN layer and the tungsten layer filled in the through hole opening 4.
The method of the embodiment of the invention will now be described with reference to the following parameters:
the thickness of the natural oxide layer before the through hole pre-cleaning process is carried out is
The thickness of the first oxide layer 5 is
In step 22, the first oxide layer etching has an etching thickness of
In step 23, the etching thickness of the second oxide layer is
In the embodiment of the invention, the step of forming the first oxide layer 5 is added in the pre-through hole cleaning process after the through hole opening 4 is formed, and then the first oxide layer etching adopting the sputtering etching process and the second oxide layer etching adopting the chemical cleaning are correspondingly arranged according to the introduction of the first oxide layer 5, and in the first oxide layer etching, the characteristics that the sputtering etching process only etches the bottom surface of the through hole opening 4 but does not etch the side surface are utilized, so that most oxide layers on the bottom surface of the through hole opening 4, namely the natural oxide layers and the overlapped layers of the first oxide layer 5, can be removed in the first oxide layer etching; in the second oxide layer etching, the etching thickness is directly set according to the growth thickness of the first oxide layer 5, and most of the oxide layer on the bottom surface of the through hole opening 4 is removed before the second oxide layer etching starts, so that the etching thickness of the second oxide layer etching is equal to the growth thickness of the first oxide layer 5, the first oxide layer 5 on the side surface of the through hole opening 4 can be completely removed while the oxide layer on the bottom surface of the through hole opening 4 is removed, the chemical cleaning of the second oxide layer etching can not generate loss on the surface of the semiconductor substrate 1, and the sputtering etching process can not generate loss on the surface of the semiconductor substrate 1 in the first oxide layer etching, so that the semiconductor substrate 1 surface of the through hole opening 4 is not damaged, and the performance of the device can be well ensured and improved, for example, for small advanced process nodes such as process nodes below 14nm, the embedded epitaxial layer 2 of embedded germanium epitaxial layer 2 such as PMOS (P-channel metal oxide semiconductor epitaxial) can be usually formed, and the carrier epitaxial layer 2 can not generate loss on the bottom surface of the semiconductor substrate 1, and the performance of the device can not be greatly improved, and the performance of the embedded epitaxial layer 2 can not generate important to the through hole epitaxial layer 2 can be greatly improved.
Meanwhile, in the second oxide layer etching of the embodiment of the invention, the chemical cleaning of the second oxide layer etching only etches the first oxide layer 5 on the side surface, and the chemical cleaning of the second oxide layer etching is stopped after the first oxide layer 5 is consumed, so that the chemical cleaning of the second oxide layer etching does not generate loss on the interlayer film 3 on the side surface of the through hole opening 4, thereby not influencing the width of the through hole opening 4, and finally, not influencing the critical dimension of the through hole opening 4, wherein the critical dimension of the through hole opening 4 corresponds to the minimum width of the through hole opening 4, and the embodiment of the invention can avoid enlarging the critical dimension of the through hole opening 4, thereby being beneficial to continuously reducing the dimension of a device, and further improving the corresponding performance and reducing the cost.
The present invention has been described in detail by way of specific examples, but these should not be construed as limiting the invention. Many variations and modifications may be made by one skilled in the art without departing from the principles of the invention, which is also considered to be within the scope of the invention.
Claims (17)
1. A method of manufacturing a through hole, comprising the steps of:
step one, photoetching and etching to form a through hole opening penetrating through an interlayer film, wherein the through hole opening exposes the surface of a semiconductor substrate at the bottom of the interlayer film;
step two, a pre-through hole cleaning process is carried out to remove a natural oxide layer on the surface of the semiconductor substrate at the bottom of the through hole opening, and the method comprises the following sub-steps:
step 21, growing a first oxide layer, wherein the first oxide layer covers the bottom surface and the side surface of the through hole opening;
step 22, performing first oxide layer etching by adopting a sputtering etching process, wherein the first oxide layer etching etches the natural oxide layer on the bottom surface of the through hole opening and the superimposed layer of the first oxide layer, and the first oxide layer is arranged to prevent the first oxide layer etching from generating etching loss on the surface of the semiconductor substrate at the bottom of the through hole opening;
after the first oxide layer is etched, the residual thickness of the superimposed layer on the bottom surface of the through hole opening is smaller than the thickness of the first oxide layer remained on the side surface of the through hole opening;
and step 23, performing second oxide layer etching, wherein the second oxide layer etching adopts chemical cleaning of reactants including NF3 and NH3, and the thickness of the oxide layer etched by the second oxide layer etching is equal to that of the first oxide layer grown in step 21, so that the residual part of the superimposed layer on the bottom surface of the through hole opening and the first oxide layer on the side surface of the through hole opening are removed, and the width of the through hole opening is maintained.
2. The method of manufacturing a through-hole according to claim 1, wherein: in step 21, the first oxide layer is also formed on the surface outside the via opening.
3. The method of manufacturing a through-hole according to claim 2, wherein: the first oxide layer on the surface outside the via opening is removed in the first oxide layer etch of step 22 or in combination with the first oxide layer etch of step 22 and the second oxide layer etch of step 23.
4. The method of manufacturing a through-hole according to claim 1, wherein: in step 22, the first oxide layer etching does not etch the first oxide layer on the side surface of the through hole opening, and after the first oxide layer etching is completed, all the first oxide layer on the side surface of the through hole opening remains.
5. The method of manufacturing a through-hole according to claim 1, wherein: the semiconductor substrate includes a silicon substrate.
6. The method of manufacturing a through-hole according to claim 5, wherein: the interlayer film is made of silicon dioxide.
7. The method of manufacturing a through-hole according to claim 5, wherein: the natural oxide layer and the first oxide layer are both made of silicon dioxide.
8. The method of manufacturing a through-hole according to claim 7, wherein: before the through hole cleaning process is carried outThe thickness of the natural oxide layer is
9. The method of manufacturing a through-hole according to claim 8, wherein: the thickness of the first oxide layer is
10. The method of manufacturing a through-hole according to claim 9, wherein: the first oxide layer is grown by an ALD process.
11. The method of manufacturing a through-hole according to claim 9, wherein: in step 22, the first oxide layer etching has an etching thickness of
In step 23, the etching thickness of the second oxide layer is
12. The method of manufacturing a through-hole according to claim 5, wherein: the semiconductor substrate is provided with a semiconductor device, and the tops of a grid structure, a source region and a drain region of the semiconductor device are respectively provided with a corresponding through hole opening.
13. The method of manufacturing a through-hole according to claim 12, wherein: the semiconductor device includes an NMOS and a PMOS.
14. The method of manufacturing a through-hole according to claim 13, wherein: the process node of the semiconductor device is below 14 nm.
15. The method of manufacturing a through-hole according to claim 14, wherein: an embedded SiP epitaxial layer is formed in the source region or the drain region of the NMOS;
and forming an embedded SiGe epitaxial layer in the source region or the drain region of the PMOS.
16. The method of manufacturing a through-hole according to claim 1, wherein: the method also comprises the steps of:
step three, depositing and forming a Ti layer and a TiN layer;
step four, performing an annealing process;
depositing a tungsten layer, wherein the tungsten layer completely fills the through hole opening;
and step six, removing the tungsten layer, the TiN layer and the Ti layer outside the through hole opening by a metal chemical mechanical polishing process, and forming the through hole by the Ti layer, the TiN layer and the tungsten layer filled in the through hole opening.
17. The method of manufacturing a through-hole according to claim 16, wherein: after the first step is completed, the step of carrying out amorphization ion implantation is further included before the second step is started.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2011143836A1 (en) * | 2010-05-21 | 2011-11-24 | 香港商莫斯飞特半导体有限公司 | Method for manufacturing trench with thick insulating bottom and semiconductor device thereof |
| CN110211921A (en) * | 2019-05-23 | 2019-09-06 | 上海华力集成电路制造有限公司 | The manufacturing method of contact hole |
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| CN1241253C (en) * | 2002-06-24 | 2006-02-08 | 丰田合成株式会社 | Semiconductor element and mfg method |
| DE102013014881B4 (en) * | 2012-09-12 | 2023-05-04 | Fairchild Semiconductor Corporation | Enhanced silicon via with multi-material fill |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2011143836A1 (en) * | 2010-05-21 | 2011-11-24 | 香港商莫斯飞特半导体有限公司 | Method for manufacturing trench with thick insulating bottom and semiconductor device thereof |
| CN110211921A (en) * | 2019-05-23 | 2019-09-06 | 上海华力集成电路制造有限公司 | The manufacturing method of contact hole |
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