CN112289266B - Pixel compensation circuit, display device and pixel compensation method - Google Patents

Pixel compensation circuit, display device and pixel compensation method Download PDF

Info

Publication number
CN112289266B
CN112289266B CN202011187155.2A CN202011187155A CN112289266B CN 112289266 B CN112289266 B CN 112289266B CN 202011187155 A CN202011187155 A CN 202011187155A CN 112289266 B CN112289266 B CN 112289266B
Authority
CN
China
Prior art keywords
module
switch
signal
driving
reset
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202011187155.2A
Other languages
Chinese (zh)
Other versions
CN112289266A (en
Inventor
陈彩琴
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Vivo Mobile Communication Co Ltd
Original Assignee
Vivo Mobile Communication Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Vivo Mobile Communication Co Ltd filed Critical Vivo Mobile Communication Co Ltd
Priority to CN202011187155.2A priority Critical patent/CN112289266B/en
Publication of CN112289266A publication Critical patent/CN112289266A/en
Application granted granted Critical
Publication of CN112289266B publication Critical patent/CN112289266B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of El Displays (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

The application discloses a pixel compensation circuit, a display device and a pixel compensation method, and belongs to the technical field of communication. Wherein, the pixel compensation circuit includes: the device comprises a light emitting diode, a data signal transmission end, a high voltage transmission end, a reset signal transmission end, a scanning signal input end, a switching signal input end, a compensation module, a driving module and a reset module; at least one of the driving module, the compensation module and the reset module comprises an NMOS tube; the scanning control signal transmitted by the scanning signal input end and the switching signal transmitted by the switching signal input end jointly control the reset module, the driving module, the compensation module and the light-emitting diode to work in a reset state, a compensation state and a light-emitting state. According to the embodiment of the application, the structure and the control logic of the pixel compensation circuit can be simplified.

Description

Pixel compensation circuit, display device and pixel compensation method
Technical Field
The application belongs to the technical field of communication, and particularly relates to a pixel compensation circuit, a display device and a pixel compensation method.
Background
An Active Matrix/Organic Light Emitting Diode (AMOLED) display device is configured with a plurality of Organic Light Emitting Diodes (OLEDs), and each OLED corresponds to a pixel compensation circuit.
In the related art, the pixel compensation circuit includes 7 Thin Film Transistor (TFT) driving switches and 1 capacitor, wherein the TFT driving switches are positive channel field effect transistors (PMOS transistors), and input signals of the pixel compensation circuit include the following signals: an nth row light-emitting switch signal (EM [ n ]), an nth row scanning signal (Scan [ n ]), an nth-1 row scanning signal (Scan [ n-1]), an initial reset signal (Vi), a data signal (Vdata), and a high-order signal (Vdd). The connection structure of the 7 TFT drive switches and the 1 capacitor is complex, the occupied space is large, the number of OLEDs which can be installed in the same area is small, and therefore the pixel density (Pixel Per Inc, PPI) of the AMOLED display device is low.
Disclosure of Invention
An object of the embodiments of the present application is to provide a pixel compensation circuit, a display device and a pixel compensation method, which can solve the problem of low PPI of the AMOLED display device in the related art.
In order to solve the technical problem, the present application is implemented as follows:
in a first aspect, an embodiment of the present application provides a pixel compensation circuit, including: the device comprises a light emitting diode, a data signal transmission end, a high voltage transmission end, a reset signal transmission end, a scanning signal input end, a switching signal input end, a compensation module, a driving module and a reset module; at least one of the driving module, the compensation module and the reset module comprises a switching transistor;
the scanning signal input end is respectively connected with the first control end of the compensation module, the control end of the reset module and the first control end of the driving module, and the switching signal input end is respectively connected with the second control end of the compensation module and the second control end of the driving module;
the input end of the compensation module is connected with the data signal transmission end, the input end of the driving module is connected with the high voltage transmission end, and the input end of the reset module is connected with the reset signal transmission end;
the output end of the compensation module, the output end of the driving module and the output end of the reset module are respectively connected with the anode of the light-emitting diode, and the cathode of the light-emitting diode is connected with the reference voltage transmission end.
In a second aspect, an embodiment of the present application provides a display device, including the pixel compensation circuit described in the first aspect.
In a third aspect, an embodiment of the present application provides a pixel compensation method applied to the display device according to the second aspect, where the method includes:
under a first working state, transmitting a first scanning control signal through the scanning signal input end; under the action of the first scanning control signal, the reset module respectively communicates the reset signal transmission end with the anode of the light emitting diode and the output end of the compensation module so as to reset the anode voltage of the light emitting diode and reset the compensation voltage provided by the compensation module to the driving module;
in a second working state, a second scanning control signal is transmitted through the scanning signal input end, a first switch control signal is transmitted through the switch signal input end, and the compensation module provides compensation voltage for the driving module; under the action of the second scanning control signal, the reset module disconnects the reset signal transmission end from the anode of the light emitting diode and the output end of the compensation module respectively; under the combined action of the second scanning control signal and the first switch control signal, the data signal transmission end is communicated with the driving module; under the action of the compensation voltage provided by the compensation module, the driving module communicates the high-voltage transmission end with the anode of the light-emitting diode so as to start the light-emitting diode to work.
In the embodiment of the application, the switching transistor is arranged in at least one of the driving module, the compensation module and the reset module, and the scanning control signal transmitted by the scanning signal input end and the switching control signal transmitted by the switching signal input end control the driving module, the compensation module and the reset module to work in different working states, so that the pixel compensation function is realized, simultaneously, the control logic of the pixel compensation circuit can be simplified, the structure of the pixel compensation circuit is simplified, the occupied space of the pixel compensation circuit can be reduced, and the PPI of the display device is further improved.
Drawings
Fig. 1 is a circuit diagram of a first pixel compensation circuit according to an embodiment of the present disclosure;
FIG. 2 is a timing diagram of a scan control signal and a switch control signal in a first pixel compensation circuit according to an embodiment of the present disclosure;
fig. 3 is a circuit diagram of a second pixel compensation circuit according to an embodiment of the present application;
FIG. 4 is a timing diagram of a scan control signal and a switch control signal in a second pixel compensation circuit according to an embodiment of the present application;
fig. 5 is a circuit diagram of a third pixel compensation circuit provided in an embodiment of the present application;
FIG. 6 is a timing diagram of scan control signals and switch control signals in a third pixel compensation circuit according to an embodiment of the present application;
fig. 7 is a flowchart of a pixel compensation method according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The terms first, second and the like in the description and in the claims of the present application are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It will be appreciated that the data so used may be interchanged under appropriate circumstances such that embodiments of the application may be practiced in sequences other than those illustrated or described herein, and that the terms "first," "second," and the like are generally used herein in a generic sense and do not limit the number of terms, e.g., the first term can be one or more than one. In addition, "and/or" in the specification and claims means at least one of connected objects, a character "/" generally means that a preceding and succeeding related objects are in an "or" relationship.
The pixel compensation circuit, the display device and the pixel compensation method provided by the embodiments of the present application are described in detail below with reference to the accompanying drawings.
Implementation mode one
Referring to fig. 1 and fig. 2, in which fig. 1 is a circuit diagram of a first pixel compensation circuit according to an embodiment of the present disclosure; fig. 2 is a timing pulse diagram of a scan control signal and a switch control signal in a first pixel compensation circuit according to an embodiment of the present disclosure. As shown in fig. 1, a first pixel compensation circuit provided in an embodiment of the present application includes:
a light emitting diode 1, a data signal transmission terminal (i.e., a signal transmission terminal for transmitting a data signal Vdata as shown in fig. 1), a high voltage transmission terminal (i.e., a transmission terminal for transmitting a high voltage signal Vdd as shown in fig. 1), a reset signal transmission terminal (i.e., a signal transmission terminal for transmitting a reset signal Vi as shown in fig. 1), a Scan signal input terminal (i.e., a transmission terminal for transmitting a Scan control signal Scan [ n ] as shown in fig. 1), a switching signal input terminal (i.e., a signal transmission terminal for transmitting a switching signal EM [ n ] as shown in fig. 1), a compensation module 2, a driving module 3, and a reset module 4; at least one of the driving module 3, the compensation module 2 and the reset module 4 comprises a switching transistor.
The switching transistor may be specifically an NMOS transistor, for example: a Low Temperature Polysilicon (LTPS) NMOS transistor or an Oxide thin film transistor (further, for example, Indium Gallium Zinc Oxide (IGZO) or Indium Tin Zinc Oxide (ITZO)) NMOS transistor.
The specific circuit structure of the pixel compensation circuit may be: the scan signal input terminal is respectively connected with the first control terminal of the compensation module 2 (which may be a gate of T3 shown in fig. 1), the control terminal of the reset module 4 (which may be a gate of T4 shown in fig. 1) and the first control terminal of the driving module 3 (which may be a gate of T6 shown in fig. 1), and the switch signal input terminal is respectively connected with the second control terminal of the compensation module 2 (which may be a gate of T2 shown in fig. 1) and the second control terminal of the driving module 3 (which may be a gate of T5 shown in fig. 1);
an input terminal (which may be a source of T2 shown in fig. 1) of the compensation module 2 is connected to the data signal transmission terminal, an input terminal (which may be a source of T5 shown in fig. 1) of the driving module 3 is connected to the high voltage transmission terminal, and an input terminal (which may be a drain of T4 shown in fig. 1) of the reset module 4 is connected to the reset signal transmission terminal;
an output terminal (which may be the second terminal of C1 shown in fig. 1) of the compensation module 2, an output terminal (which may be the drain of T6 shown in fig. 1) of the driving module 3, and an output terminal (which may be the source of T4 shown in fig. 1) of the reset module 4 are all connected to an anode of the light emitting diode 1, and a cathode of the light emitting diode 1 is connected to a reference voltage transmission terminal.
In practical application, the light emitting diode 1 is an OLED, a plurality of pixel compensation circuits arranged in an array can be mounted on the same AMOLED display device, and each pixel compensation circuit is provided with an OLED, so that the Scan [ N ] signal represents a Scan control signal of the pixel compensation circuit in the nth row, and the EM [ N ] signal represents a light emitting switch control signal of the pixel compensation circuit in the nth row, in the embodiment of the present application, the pixel compensation circuit in the nth row is not controlled by the Scan [ N-1] signal of the pixel compensation circuit in the [ N-1] th row, thereby simplifying the control logic and circuit complexity of the pixel compensation circuit, and further, the integrated control circuit (IC) generating the Scan [ N ] signal and the EM [ N ] signal is also prevented from outputting the Scan [ N-1] signal to the pixel compensation circuit in the nth row, thereby simplifying the number of control signals output by the IC, thereby enabling the production cost of the IC to be reduced.
The data signal Vdata, the high voltage signal Vdd, and the reset signal Vi may be stable voltage signals, and specifically, the high voltage signal Vdd may be a high potential signal of about 4.6v (volts); the reset signal Vi may be a voltage signal between-2.5 v to-3.5 v; the reference voltage transmission terminal is used for transmitting a reference voltage Vss, and the reference voltage Vss can be a low-potential signal between-3 v and-3.5 v.
In a first working state, the Scan [ n ] signal transmitted by the scanning signal input end controls the reset module 4 to communicate the reset signal transmission end with the anode of the light emitting diode 1 and the output end of the compensation module 2 respectively so as to reset the anode voltage of the light emitting diode 1 and reset the compensation voltage provided by the compensation module 2 to the driving module 3.
It should be noted that, in the process of resetting the compensation voltage provided by the compensation module 2 to the driving module 3, the EM [ n ] signal transmitted by the switching signal input terminal also controls the compensation module 2 to charge and store energy, and controls the driving module 3 to disconnect the high voltage transmission terminal from the light emitting diode 1.
In a second working state, the Scan [ n ] signal transmitted by the Scan signal input terminal controls the reset module 4 to disconnect the reset signal transmission terminal from the anode of the light emitting diode 1 and the output terminal of the compensation module 2, the Scan [ n ] signal transmitted by the Scan signal input terminal and the EM [ n ] signal transmitted by the switch signal input terminal control the data signal transmission terminal to communicate with the driving module 3, and the driving module 3 enables the high voltage transmission terminal to communicate with the anode of the light emitting diode 1 under the action of the compensation voltage provided by the compensation module 2, so as to start the light emitting diode 1 to work.
In a specific implementation, the driving module 3 connects the high voltage transmission terminal to the anode of the light emitting diode 1 under the effect of the compensation voltage provided by the compensation module 2, which can be understood as: the compensation module 2 provides compensation voltage for the driving module 3 to eliminate the voltage consumed by the conduction threshold voltage of the driving module 3, so that when the driving module 3 communicates the high voltage transmission end with the anode of the light emitting diode 1, the conduction threshold voltage of the driving module 3 can be avoided to reduce the anode voltage of the light emitting diode 1, thereby improving the current flowing through the light emitting diode 1 and enabling the light emitting brightness of the light emitting diode 1 to be more stable.
It should be noted that the pixel compensation circuit provided in this embodiment of the application may further include a third operating state, where in the third operating state, the Scan [ n ] signal transmitted by the Scan signal input terminal controls the reset module 4 to disconnect the reset signal transmission terminal from the anode of the light emitting diode 1 and the output terminal of the compensation module 2, respectively, and the Scan [ n ] signal transmitted by the Scan signal input terminal and the EM [ n ] signal transmitted by the switch signal input terminal control the compensation module 2 to store energy.
The first operation state may be referred to as a reset state, the third operation state may be referred to as a compensation state, and the second operation state may be referred to as a light-emitting state. The pixel compensation circuit can perform reset, compensation and light emitting functions in a driving period, and in the third working state, the compensation module 2 stores energy, so that in the second working state, the threshold voltage (i.e. Vgsth) of the driving module 3 is eliminated through the compensation module 2, and thus, the current flowing through the light emitting diode is more stable.
As shown in fig. 1, in a first pixel compensation circuit provided in the embodiment of the present application, a driving module 3 includes: a drive transistor switch T1, a first transistor switch T5, and a second transistor switch T6;
a source of a first crystal switch T5 is connected to the high voltage transmission terminal, a gate of the first crystal switch T5 is connected to the switching signal input terminal, and a drain of the first crystal switch T5 is connected to the source of the driving crystal switch T1;
the drain of the driving transistor switch T1 is connected to the source of the second transistor switch T6, the gate of the driving transistor switch T1 is connected to the source of the driving transistor switch T1 through the compensation module 2, and the drain of the driving transistor switch T1 is also connected to the data signal transmission terminal through the compensation module 2;
the drain of the second crystal switch T6 is respectively connected to the anode of the led 1, the reset module 4 and the compensation module 2, and the gate of the second crystal switch T6 is connected to the scan signal input terminal.
In addition, the compensation module 2 includes: a third transistor switch T2, a fourth transistor switch T3, and a capacitor C1;
a source of the third transistor switch T2 is connected to the data signal transmission terminal, a drain of the third transistor switch T2 is connected to the drain of the driving transistor switch T1, and a gate of the third transistor switch T2 is connected to the switch signal input terminal;
a source of the fourth crystal switch T3 is connected to a source of the driving crystal switch T1, a drain of the fourth crystal switch T3 is connected to a gate of the driving crystal switch T1 and a first end of the capacitor C1, respectively, and a gate of the fourth crystal switch T3 is connected to the scan signal input terminal;
a second end of the capacitor C1 is connected to the reset module 4 and the anode of the light emitting diode 1, respectively.
Further, the reset module 4 includes: a fifth crystal switch T4, a gate of the fifth crystal switch T4 being connected to the scan signal input terminal; the source electrode of the fifth crystal switch T4 is connected to the reset signal transmission end; the drain of the fifth transistor switch T4 is connected to the second terminal of the capacitor C1.
In the embodiment shown in fig. 1, the driving transistor switch T1, the first transistor switch T5, the fourth transistor switch T3 and the fifth transistor switch T4 are NMOS transistors; the third transistor switch T2 and the second transistor switch T6 are PMOS transistors.
In this embodiment, the Scan [ n ] signal may be referred to as a first pulse signal, the EM [ n ] signal may be referred to as a second pulse signal, and the timing pulse diagrams of the first pulse signal and the second pulse signal are shown in fig. 2.
Specifically, in the first frame time t1, the Scan [ n ] signal is high (also called high pulse signal), and the EM [ n ] signal is high. At this time, T3, T4, and T5 as NMOS transistors are turned on, and T2 and T6 as PMOS transistors are turned off. At this time, the potential of the a-potential is equal to Vdd as shown in fig. 1, and the potentials across C1 are Vdd and Vi, respectively, at which time C1 charges, i.e., the gate voltage of T1 starts to rise slowly.
Then, in the second frame time t2, the Scan [ n ] signal is high, and the EM [ n ] signal is low (which may also be referred to as a low pulse signal). At this time, T5 serving as an NMOS transistor is turned off, T2 and T6 serving as PMOS transistors are turned on, and T3 and T4 serving as NMOS transistors are turned on. As shown in fig. 1, the potential at point C is Vdata, the gate and drain of T1 are shorted, the potential at point a is VA ═ Vdd, which is greater than Vgsth, i.e., when T1 corresponds to a diode, and T1 is turned on, at which time C1 starts to discharge until T1 is turned off when C1 discharges to a point a potential Vdata + Vth. In this process, the threshold voltage Vgsth of T1 can be stored in C1.
Finally, during a third frame time t3, Scan [ n ]]The signal is at a low potential, EM [ n ]]The signal is high. T3 and T4 as NMOS transistors are turned off, T6 as PMOS transistor is turned on, T5 as NMOS transistor is turned on, and T2 as PMOS transistor is turned off. At this time, the potential of the gate (i.e., point a) of T1 is: vdata + Vth, drain (i.e., point C) potential: vdata, source potential is: vdd, and therefore the potential difference Vgs between the gate and source of T1 is (Vdata + Vgsth) -Vdd, so that the current through T1 is: ids ═ (1/2) K [ Vgs-Vth [ ]]2＝(1/2)K(Vdata-Vdd)2The current Ids flows through the light emitting diode 1 to cause the light emitting diode 1 to emit light.
Wherein K is Cox×μ×W/L，CoxRepresents: gate capacitance per unit area; μ denotes: mobility of channel electron motion; W/L represents: and the width-length ratio of the T1 NMOS tube.
In the process, the compensation module 2 provides the compensation voltage, which may be equal to Vgsth, to the driving module 3 to compensate for the conduction voltage difference of T1.
In a specific implementation, the MOS transistor turned on means that a source and a drain of the MOS transistor are turned on, and the MOS transistor turned off means that the source and the drain of the MOS transistor are turned off.
In this embodiment, T3 and T4 are configured as NMOS structures, so that T3 and T4 are turned off in T3 having a longer time length, and T3 and T4 are turned on only in T1 and T2 having shorter time lengths, and therefore, the on time of T3 and T4 can be shortened, so that the leakage voltage of T3 and T4 when turned on can be reduced, so that the power consumption of the pixel compensation circuit can be reduced, and the leakage of the voltage stored in the compensation circuit can be further reduced in T1 and T2, so that the luminance of the light emitting diode can be improved in T3.
In an alternative embodiment, T1 is an LTPS NMOS transistor, and T3 and T4 are oxide NMOS transistors.
In specific implementation, compared with LTPS NMOS, the oxide NMOS has better off-current characteristics, so that leakage current of T3 and T4 in an off state can be reduced, power consumption of the pixel compensation circuit can be reduced, and luminance of the light emitting diode can be improved.
In addition, the LTPS NMOS structure is adopted for the T1, so that the T1 has enough driving capability.
Of course, at least one of T6, T3, and T4 may be an LTPS NMOS transistor, which is not particularly limited herein.
In the embodiment of the application, compared with the circuit structure of 7T1C in the prior art, the NMOS transistor is arranged in the pixel compensation circuit, the number of TFT driving switches can be reduced, and the pixel compensation function can be realized only by 6T1C, and the scanning signal of the n-1 th line of leds is not required to be collected to control the pixel compensation circuit of the n-1 th line of leds, so that the circuit complexity and the control logic of the pixel compensation circuit can be simplified, and the improvement of the yield of the pixel driving circuit is facilitated. In addition, the size of the pixel compensation circuit can be reduced by simplifying the circuit complexity of the pixel compensation circuit and reducing the number of TFTs (thin film transistors), so that more light-emitting diodes and corresponding pixel compensation circuits can be arranged on the AMOLED display device with a fixed area, and the pixel density of the AMOLED display device is improved.
Second embodiment
Referring to fig. 3 and fig. 4, in which, fig. 3 is a circuit diagram of a second pixel compensation circuit according to an embodiment of the present application; fig. 4 is a timing pulse diagram of a scan control signal and a switch control signal in a second pixel compensation circuit according to an embodiment of the present application.
The difference from the first pixel compensation circuit shown in fig. 1 and 2 is that in the pixel compensation circuit shown in fig. 3, T1, T5 and T6 are NMOS transistors; t2, T3 and T4 are PMOS tubes.
In this embodiment, the Scan [ n ] signal and the EM [ n ] signal are pulse signals as shown in FIG. 4.
Specifically, in the first frame time t1, the Scan [ n ] signal is at a low voltage level (which may also be referred to as a low pulse signal), and the EM [ n ] signal is at a high voltage level. At this time, by the Scan [ n ] signal and the EM [ n ] signal, T3 and T4 as PMOS transistors are turned on, T6 as NMOS transistors are turned off, T5 as NMOS transistors are turned on, and T2 as PMOS transistors are turned off. At this time, the potential at point a is equal to Vdd as shown in fig. 3, and the potentials at both ends of C1 are Vdd and Vi, respectively, at which time C1 charges, i.e., the gate voltage of T1 starts to rise slowly.
Then, during a second frame time t2, the Scan [ n ] signal is low and the EM [ n ] signal is low. At this time, T5 and T6 as NMOS transistors are turned off, and T2, T3 and T4 as PMOS transistors are turned on. As shown in fig. 3, the potential at point C is Vdata, the gate and drain of T1 are shorted, the potential at point a is VA ═ Vdd, which is greater than Vgsth, i.e., when T1 corresponds to a diode, and T1 is turned on, at which time C1 starts to discharge until T1 is turned off when C1 discharges to a point a potential Vdata + Vth. In this process, the threshold voltage Vgsth of T1 can be stored in C1.
Finally, during a third frame time t3, Scan [ n ]]The signal is high potential, EM [ n ]]The signal is high. T5 and T6 as NMOS transistors are turned on, and T3, T4 and T2 as PMOS transistors are turned off. At this time, the potential of the gate (i.e., point a) of T1 is: vdata + Vth, drain (i.e., point C) potential: vdata, source potential is: vdd, and therefore the potential difference Vgs between the gate and source of T1 is (Vdata + Vgsth) -Vdd, so that the current through T1 is: ids ═ (1/2) K [ Vgs-Vth [ ]]2＝(1/2)K(Vdata-Vdd)2The current Ids flows through the light emitting diode 1 to cause the light emitting diode 1 to emit light.
Wherein K is Cox×μ×W/L，CoxRepresents: gate capacitance per unit area; μ denotes: mobility of channel electron motion; W/L represents: and the width-length ratio of the T1 NMOS tube.
In the process, the compensation module 2 provides the compensation voltage, which may be equal to Vgsth, to the driving module 3 to compensate for the conduction voltage difference of T1.
In this embodiment, the T3, T4, and T2 may be LTPS PMOS transistors, the T5 and T6 may be oxide NMOS transistors, and the T1 may be LTPS NMOS transistors.
In this embodiment, T5 and T6 may be oxide NMOS transistors, and when T5 and T6 are turned off, leakage currents of T5 and T6 can be reduced by using good turn-off characteristics of the oxide NMOS transistors, thereby reducing power consumption of the pixel compensation circuit.
The pixel compensation circuit provided in this embodiment can achieve the same functions as the pixel compensation circuit shown in fig. 1 by changing the pulse variation trend of the Scan [ n ] signal and the EM [ n ] signal, and obtain the same beneficial effects, and no further description is provided herein to avoid repetition.
Third embodiment
Referring to fig. 5 and fig. 6, in which fig. 5 is a circuit diagram of a third pixel compensation circuit according to an embodiment of the present application; fig. 6 is a timing pulse diagram of a scan control signal and a switch control signal in a third pixel compensation circuit according to an embodiment of the present application.
The difference from the first pixel compensation circuit shown in fig. 1 and 2 is that, in the pixel compensation circuit shown in fig. 5, T1, T2, T3 and T4 are NMOS transistors; t5 and T6 are PMOS tubes.
In this embodiment, the Scan [ n ] signal and the EM [ n ] signal are pulse signals as shown in FIG. 6.
Specifically, in the first frame time t1, the Scan [ n ] signal is at a high level (which may also be referred to as a high pulse signal), and the EM [ n ] signal is at a low level (which may also be referred to as a low pulse signal). At this time, T3 and T4 as NMOS transistors are turned on, T5 as PMOS transistors are turned on, T2 as NMOS transistors are turned off, and T6 as PMOS transistors are turned off. At this time, the potential of the a-potential is equal to Vdd as shown in fig. 5, and the potentials across C1 are Vdd and Vi, respectively, at which time C1 charges, i.e., the gate voltage of T1 starts to rise slowly.
Then, in the second frame time t2, the Scan [ n ] signal is high, and the EM [ n ] signal is high. At this time, T5 and T6 as PMOS transistors are turned off, and T2, T3 and T4 as NMOS transistors are turned on. As shown in fig. 5, the potential at point C is Vdata, the gate and drain of T1 are shorted, the potential at point a is VA ═ Vdd, which is greater than Vgsth, i.e., when T1 corresponds to a diode, and T1 is turned on, at which time C1 starts to discharge until T1 is turned off when C1 discharges to make the potential at point a be Vdata + Vth. In this process, the threshold voltage Vgsth of T1 can be stored in C1.
Finally, during a third frame time t3, Scan [ n ]]The signal is at a low potential, EM [ n ]]The signal is at a low potential. T2, T3 and T4 as NMOS transistors are turned off, and T5 and T6 as PMOS transistors are turned on. At this time, the potential of the gate (i.e., point a) of T1 is: vdata + Vth, drain (i.e., point C) potential: vdata, source potential is: vdd, and therefore the potential difference Vgs between the gate and source of T1 is (Vdata + Vgsth) -Vdd, so that the current through T1 is: ids ═ (1/2) K [ Vgs-Vth [ ]]2＝(1/2)K(Vdata-Vdd)2The current Ids flows through the light emitting diode 1 to cause the light emitting diode 1 to emit light.
Wherein K is Cox×μ×W/L，CoxRepresents: gate capacitance per unit area; μ denotes: mobility of channel electron motion; W/L represents: and the width-to-length ratio of the T1 MOS tube.
In the process, the compensation module 2 provides the compensation voltage, which may be equal to Vgsth, to the driving module 3 to compensate for the conduction voltage difference of T1.
In this embodiment, T3 and T4 may be oxide NMOS transistors, and when T3 and T4 are turned off, leakage currents of T3 and T4 can be reduced by using good turn-off characteristics of the oxide NMOS transistors, thereby reducing power consumption of the pixel compensation circuit.
The pixel compensation circuit provided in this embodiment can achieve the same functions as the pixel compensation circuit shown in fig. 1 by changing the pulse variation trend of the Scan [ n ] signal and the EM [ n ] signal, and obtain the same beneficial effects, and no further description is provided herein to avoid repetition.
The embodiment of the application also provides a display device, and the display device can comprise any one of the pixel compensation circuits provided by the embodiment of the application.
In a specific implementation, the display device provided in the embodiments of the present application may be specifically referred to as an AMOLED display device, and the AMOLED display device may include a plurality of pixel compensation circuits distributed in an array, and may further include a control IC, so that the control IC outputs a pixel driving signal (including a scan control signal and a switch control signal) of each row of the pixel compensation circuits.
Wherein the Scan control signal Scan [ n +1] of the pixel compensation circuit of the (n +1) th row is delayed by a length of t1 time frame from the Scan control signal Scan [ n ] of the pixel compensation circuit of the n-th row, and the switching control signal EM [ n +1] of the pixel compensation circuit of the (n +1) th row is delayed by a length of t1 time frame from the switching control signal WM [ n ] of the pixel compensation circuit of the n-th row.
Specifically, as shown in fig. 2, 4 and 6, the Scan [ n +1] signal in the second time frame t2 is the same as the Scan [ n ] signal in the first time frame t1, and the Scan [ n +1] signal in the third time frame t3 is the same as the Scan [ n ] signal in the second time frame t 2; and the EM [ n +1] signal in the second time frame t2 is the same as the EM [ n ] signal in the first time frame t1, the EM [ n +1] signal in the third time frame t3 is the same as the EM [ n ] signal in the second time frame t2, and so on.
Where N may be any integer between 0 and the number N of rows of pixel compensation circuits included in the AMOLED display device.
It should be noted that the AMOLED display device provided in the embodiment of the present application may be a display device having an LTPS AMOLED hard screen, a flexible screen, or a folded screen, or may be a display device having a Low Temperature Polycrystalline Oxide (LTPO) AMOLED pixel driving circuit, that is, the pixel driving circuit in the AMOLED display device includes an LTPO NMOS transistor.
In the AMOLED display device provided by the embodiment of the application, the pixel compensation circuit with a simple structure and a simple control logic is configured, so that the occupied space of the pixel compensation circuit can be reduced, the complexity of the pixel driving signals output by the control IC can be simplified, the pixel density of the AMOLED display device can be increased, and the production cost of the AMOLED display device can be reduced.
Referring to fig. 7, which is a flowchart illustrating a pixel compensation method according to an embodiment of the present application, the pixel compensation method can be applied to a display device according to an embodiment of the present application, and as shown in fig. 7, the pixel compensation method can include the following steps:
701, transmitting a first scanning control signal through the scanning signal input end in a first working state; under the action of the first scanning control signal, the reset module respectively communicates the reset signal transmission end with the anode of the light emitting diode and the output end of the compensation module so as to reset the anode voltage of the light emitting diode and reset the compensation voltage provided by the compensation module to the driving module;
step 702, in a second working state, transmitting a second scanning control signal through the scanning signal input terminal, and transmitting a first switching control signal through the switching signal input terminal, and the compensation module providing a compensation voltage to the driving module; under the action of the second scanning control signal, the reset module disconnects the reset signal transmission end from the anode of the light emitting diode and the output end of the compensation module respectively; under the combined action of the second scanning control signal and the first switch control signal, the data signal transmission end is communicated with the driving module; under the action of the compensation voltage provided by the compensation module, the driving module communicates the high-voltage transmission end with the anode of the light-emitting diode so as to start the light-emitting diode to work.
In practice, the first operating state has the same meaning as the first operating state in the pixel compensation circuit in the embodiment shown in fig. 1 to 6, and the second operating state has the same meaning as the second operating state in the pixel compensation circuit in the embodiment shown in fig. 1 to 6, which is not repeated herein.
As an optional implementation, the scan signal input terminal is configured to transmit a first pulse signal, and the switch signal input terminal is configured to transmit a second pulse signal; in a first frame time and a second frame time, the first pulse signal is a high pulse signal, in a third frame time, the first pulse signal is a low pulse signal, and the second pulse signal corresponds to the first pulse signal;
wherein the driving period of the first pulse signal and the second pulse signal includes the first frame time, the second frame time, and the third frame time arranged in time sequence, and a sum of time lengths of the first frame time and the second frame time is less than a time length of the third frame time.
It should be noted that the pixel compensation method provided in the embodiment of the present application is applied to a display device including the pixel compensation circuit in the embodiment shown in fig. 1 to 6, and the pixel compensation method provided in the embodiment of the present application corresponds to the workflow of the pixel compensation circuit in the embodiment shown in fig. 1 to 6, and repeated details are not repeated here.
The pixel compensation method provided by the embodiment of the present application has the same beneficial effects as the pixel compensation circuit provided by the embodiment of the present application, and is not repeated herein for avoiding repetition.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. Further, it should be noted that the scope of the methods and apparatus of the embodiments of the present application is not limited to performing the functions in the order illustrated or discussed, but may include performing the functions in a substantially simultaneous manner or in a reverse order based on the functions involved, e.g., the methods described may be performed in an order different than that described, and various steps may be added, omitted, or combined. In addition, features described with reference to certain examples may be combined in other examples.
Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner. Based on such understanding, the technical solutions of the present application may be embodied in the form of a software product, which is stored in a storage medium (e.g., ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a terminal (e.g., a mobile phone, a computer, a server, an air conditioner, or a network device) to execute the pixel compensation circuit AMOLED display apparatus or the executed processes according to the embodiments of the present application.
While the present embodiments have been described with reference to the accompanying drawings, it is to be understood that the invention is not limited to the precise embodiments described above, which are meant to be illustrative and not restrictive, and that various changes may be made therein by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (8)

1. A pixel compensation circuit, comprising: the device comprises a light emitting diode, a data signal transmission end, a high voltage transmission end, a reset signal transmission end, a scanning signal input end, a switching signal input end, a compensation module, a driving module and a reset module; at least one of the driving module, the compensation module and the reset module comprises a switching transistor;
the scanning signal input end is respectively connected with the first control end of the compensation module, the control end of the reset module and the first control end of the driving module, and the switching signal input end is respectively connected with the second control end of the compensation module and the second control end of the driving module;
the input end of the compensation module is connected with the data signal transmission end, the input end of the driving module is connected with the high voltage transmission end, and the input end of the reset module is connected with the reset signal transmission end;
the output end of the compensation module, the output end of the driving module and the output end of the reset module are respectively connected with the anode of the light-emitting diode, and the cathode of the light-emitting diode is connected with a reference voltage transmission end;
the driving module includes: a drive crystal switch, a first crystal switch and a second crystal switch;
the source electrode of the first crystal switch is connected with the high-voltage transmission end, the grid electrode of the first crystal switch is connected with the switch signal input end, and the drain electrode of the first crystal switch is connected with the source electrode of the driving crystal switch;
the drain electrode of the driving crystal switch is connected with the source electrode of the second crystal switch, the grid electrode of the driving crystal switch is connected with the source electrode of the driving crystal switch through the compensation module, and the drain electrode of the driving crystal switch is also connected with the data signal transmission end through the compensation module;
the drain electrode of the second crystal switch is respectively connected with the anode of the light-emitting diode, the reset module and the compensation module, and the grid electrode of the second crystal switch is connected with the scanning signal input end;
the compensation module includes: a third crystal switch, a fourth crystal switch and a capacitor;
the source electrode of the third crystal switch is connected with the data signal transmission end, the drain electrode of the third crystal switch is connected with the drain electrode of the driving crystal switch, and the grid electrode of the third crystal switch is connected with the switch signal input end;
the source electrode of the fourth crystal switch is connected with the source electrode of the driving crystal switch, the drain electrode of the fourth crystal switch is respectively connected with the grid electrode of the driving crystal switch and the first end of the capacitor, and the grid electrode of the fourth crystal switch is connected with the scanning signal input end;
the second end of the capacitor is respectively connected with the reset module and the anode of the light-emitting diode;
the reset module includes: a fifth crystal switch, a grid of which is connected with the scanning signal input end; the source electrode of the fifth crystal switch is connected to the reset signal transmission end; the drain electrode of the fifth crystal switch is connected to the second end of the capacitor.
2. The pixel compensation circuit of claim 1, wherein the driving transistor switch, the third transistor switch, the fourth transistor switch, and the fifth transistor switch are NMOS transistors; the first crystal switch and the second crystal switch are PMOS tubes.
3. The pixel compensation circuit of claim 2, wherein the driving transistor switches are Low Temperature Polysilicon (LTPS) NMOS transistors, and the third, fourth, and fifth transistor switches are oxide NMOS transistors.
4. The pixel compensation circuit of claim 1, wherein the driving transistor switch, the first transistor switch, the fourth transistor switch, and the fifth transistor switch are NMOS transistors; the third crystal switch and the second crystal switch are PMOS tubes.
5. The pixel compensation circuit of claim 1, wherein the driving transistor switch, the first transistor switch, and the second transistor switch are NMOS transistors; the third, fourth and fifth transistor switches are PMOS transistors.
6. A display device comprising the pixel compensation circuit according to any one of claims 1 to 5.
7. A pixel compensation method applied to the display device according to claim 6, the method comprising:
under a first working state, transmitting a first scanning control signal through the scanning signal input end; under the action of the first scanning control signal, the reset module respectively communicates the reset signal transmission end with the anode of the light emitting diode and the output end of the compensation module so as to reset the anode voltage of the light emitting diode and reset the compensation voltage provided by the compensation module to the driving module;
in a second working state, a second scanning control signal is transmitted through the scanning signal input end, a first switch control signal is transmitted through the switch signal input end, and the compensation module provides compensation voltage for the driving module; under the action of the second scanning control signal, the reset module disconnects the reset signal transmission end from the anode of the light emitting diode and the output end of the compensation module respectively; under the combined action of the second scanning control signal and the first switch control signal, the data signal transmission end is communicated with the driving module; under the action of the compensation voltage provided by the compensation module, the driving module communicates the high-voltage transmission end with the anode of the light-emitting diode so as to start the light-emitting diode to work.
8. The method of claim 7, wherein the scan signal input terminal is used for transmitting a first pulse signal, and the switch signal input terminal is used for transmitting a second pulse signal; in a first frame time and a second frame time, the first pulse signal is a high pulse signal, in a third frame time, the first pulse signal is a low pulse signal, and the second pulse signal corresponds to the first pulse signal;
wherein the driving period of the first pulse signal and the second pulse signal includes the first frame time, the second frame time, and the third frame time arranged in time sequence, and a sum of time lengths of the first frame time and the second frame time is less than a time length of the third frame time.
CN202011187155.2A 2020-10-30 2020-10-30 Pixel compensation circuit, display device and pixel compensation method Active CN112289266B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202011187155.2A CN112289266B (en) 2020-10-30 2020-10-30 Pixel compensation circuit, display device and pixel compensation method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202011187155.2A CN112289266B (en) 2020-10-30 2020-10-30 Pixel compensation circuit, display device and pixel compensation method

Publications (2)

Publication Number Publication Date
CN112289266A CN112289266A (en) 2021-01-29
CN112289266B true CN112289266B (en) 2021-11-16

Family

ID=74353186

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202011187155.2A Active CN112289266B (en) 2020-10-30 2020-10-30 Pixel compensation circuit, display device and pixel compensation method

Country Status (1)

Country Link
CN (1) CN112289266B (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103839514A (en) * 2012-11-27 2014-06-04 乐金显示有限公司 Organic light emitting diode display device and method of driving the same
KR20160141366A (en) * 2015-05-28 2016-12-08 엘지디스플레이 주식회사 Organic Light Emitting Display and Circuit thereof
CN110176213A (en) * 2018-06-08 2019-08-27 京东方科技集团股份有限公司 Pixel circuit and its driving method, display panel

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10347658B2 (en) * 2017-03-16 2019-07-09 Shenzhen China Star Optoelectronics Technology Co., Ltd Pixel driving circuit and OLED display device that effectively compensate for threshold voltage imposed on a driving TFT

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103839514A (en) * 2012-11-27 2014-06-04 乐金显示有限公司 Organic light emitting diode display device and method of driving the same
KR20160141366A (en) * 2015-05-28 2016-12-08 엘지디스플레이 주식회사 Organic Light Emitting Display and Circuit thereof
CN110176213A (en) * 2018-06-08 2019-08-27 京东方科技集团股份有限公司 Pixel circuit and its driving method, display panel

Also Published As

Publication number Publication date
CN112289266A (en) 2021-01-29

Similar Documents

Publication Publication Date Title
CN110223636B (en) Pixel driving circuit, driving method thereof and display device
US11244614B2 (en) Pixel driver circuit, display device and pixel driving method
CN104464643B (en) Display device, pixel driving circuit and driving method of pixel driving circuit
CN100590691C (en) Display and its pixel circuit
CN109192140B (en) Pixel driving circuit and display device
CN108538249B (en) Pixel driving circuit and method and display device
CN109509430B (en) Pixel driving circuit and method and display device
JP6037477B2 (en) AMOLED drive compensation circuit, method and display device thereof
CN109119029B (en) Pixel circuit, driving method thereof, display device and electronic equipment
CN111508426A (en) Pixel circuit, driving method thereof and display panel
CN108470544B (en) Pixel driving circuit and driving method thereof, array substrate and display device
CN111754938A (en) Pixel circuit, driving method thereof and display device
CN111599313B (en) Pixel driving circuit, driving method and display panel
CN212276788U (en) Pixel circuit and display device
CN113096593A (en) Pixel unit, array substrate and display terminal
CN113593481B (en) Display panel and driving method thereof
CN114333702B (en) Display panel and driving circuit thereof
CN109509434B (en) Pixel driving circuit, display device and driving method
CN109192139B (en) Pixel compensation circuit
US8289309B2 (en) Inverter circuit and display
CN209785530U (en) Pixel compensation circuit
CN112289266B (en) Pixel compensation circuit, display device and pixel compensation method
CN108510945B (en) OLED pixel compensation circuit
US20240177669A1 (en) Pixel circuit and driving method therefor, and display device
CN115578978A (en) Pixel circuit, driving method thereof and display panel

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant