CN112286842B - Bus for memory controller and memory device interconnection - Google Patents
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4247—Bus transfer protocol, e.g. handshake; Synchronisation on a daisy chain bus
Abstract
The present application provides a bus for memory controller and memory device interconnection, comprising: a plurality of unidirectional point-to-point data buses configured to serially connect a plurality of memory devices in sequence with a memory controller to form a loop; a plurality of control buses configured to connect the plurality of memory devices with the memory controller, respectively.
Description
Technical Field
The present application relates to the field of memory technology, and in particular, to a bus for interconnecting a memory controller and a memory device.
Background
In a conventional arrangement, a shared bi-directional bus is used to connect the controller and the plurality of memory devices, for example, the ONFI bus standard is a bus interface standard that connects the NAND flash controller and the NAND flash devices. The biggest disadvantage of such a bus system is that the speed of the bus is largely dependent on the bus load. As more devices are connected on the bus (also referred to as bus lanes), the load on the bus increases due to additional pin loads and additional interconnect loads (e.g., PCB routing and wire bonding). In addition, there is a need for a more complex, scalable and power-hungry bus interface design and tuning scheme to increase bus speed, an example of which is shown in fig. 1a and 1 b. The shared bi-directional bus is typically composed of a multi-bit data bus and strobe signals. If the control status signal is returned from the memory device to the controller, the control bus may be unidirectional (FIG. 1 a) or bidirectional (FIG. 1 b). Bus loading problems become more severe as more memory devices are required on the same bus to increase the memory capacity of each bus.
A common bus topology for overcoming bus loading problems is to connect memory devices in a Daisy chain fashion. The connections between all devices on the bus channel are point-to-point and high speed operation can be achieved by reducing bus load. Each memory device on the daisy chain adds additional delay to the overall transmission delay. The additional delay may be a good trade-off, especially if it is significantly smaller than the overall bus transfer delay. For example, for a 16-length daisy-chain and NAND flash memory device transmitting 4KB blocks at Gbps data rates, the additional transmission delay is on the order of tens of nanoseconds, which is significantly less than the microsecond order of block transmission time. Because the point-to-point connections of the daisy chain are typically unidirectional, approximately twice the number of pins are required on the controller and memory device, thereby reducing the interconnect design efficiency of the bandwidth design per pin.
Disclosure of Invention
In one embodiment of the invention, a bus for interconnecting a memory controller and a memory device is provided, comprising: a plurality of unidirectional point-to-point data buses configured to serially connect a plurality of memory devices in sequence with a memory controller to form a loop; a plurality of control buses configured to connect the plurality of memory devices with the memory controller, respectively.
In another embodiment of the present invention, there is provided a bus for interconnecting a memory controller and a memory device, comprising: a plurality of bi-directional point-to-point data buses configured to connect a plurality of memory devices to a memory controller to form links; a plurality of control buses configured to connect the plurality of memory devices with the memory controller, respectively.
In another embodiment of the present invention, there is provided a bus for interconnecting a memory controller and a memory device, comprising: a plurality of bidirectional point-to-point data buses configured to serially connect a plurality of memory devices with a memory controller in sequence to form a loop; a plurality of control buses configured to connect the plurality of memory devices with the memory controller, respectively.
In one embodiment, the plurality of memory devices and the memory controller are connected in series to form a loop through unidirectional point-to-point control buses, respectively. In another embodiment, the plurality of memory devices and the memory controller are respectively connected through a plurality of control buses which are unidirectionally shared. In another embodiment, the plurality of memory devices and the memory controller are respectively connected through a plurality of control buses which are shared in both directions.
In an embodiment, the plurality of memory devices and/or the memory device and the memory controller are connected by through silicon vias. In another embodiment, the plurality of memory devices are stacked in the same package structure and interconnected by through silicon vias.
In an embodiment, at least one bidirectional data bus interface of the memory device supports dual mode: conventional mode of small load driving between memory devices, enhanced mode of large load driving between memory devices and memory controller.
In an embodiment, the plurality of memory devices are different types of memory; the plurality of memory devices are NAND flash memory or storage class memory storage or a combination of both.
In an embodiment, the memory controller is configured to connect with the plurality of memory devices to form one or more of a unidirectional point-to-point data bus loop, a bidirectional point-to-point data bus loop, or a data bus link in one direction.
In one embodiment, a method of operating a memory controller and a memory device is provided, using the bus described above, one of the plurality of memory devices performing a read or write operation through a first branch, and another of the plurality of memory devices performing a read or write operation through a second branch. The first branch and the second branch form a loop.
In another embodiment of the present invention, a bus for interconnecting a memory controller and a memory device, comprises:
a plurality of unidirectional point-to-point data buses configured to serially connect a plurality of memory devices in sequence with a memory controller, wherein a part of unidirectional point-to-point data buses are in a direction of outputting from the memory controller to the memory devices, and a part of unidirectional point-to-point data buses are in a direction of inputting from the memory devices to the memory controller;
a plurality of point-to-point control buses configured to respectively connect the plurality of memory devices with the memory controller.
In one embodiment, the plurality of point-to-point control buses includes a plurality of unidirectional point-to-point total control lines, wherein a unidirectional point-to-point total control line transmission direction is output from the memory controller to the memory device. In another embodiment, the plurality of point-to-point control buses includes a plurality of unidirectional point-to-point total control lines, wherein a portion of the unidirectional point-to-point total control line transmission directions are output from the memory controller to the memory device and a portion of the unidirectional point-to-point total control line transmission directions are input from the memory device to the memory controller. In another embodiment, the plurality of point-to-point control buses are bidirectional buses.
In one embodiment, an apparatus is provided for implementing direct interconnection of a plurality of memory devices to a memory controller using the bus described above.
In one embodiment, all of the memory devices in the daisy chain connection or the loop connection are packaged in one apparatus, while the memory controller and the memory devices may be packaged in the same apparatus or the memory controller may be in another apparatus alone.
In one embodiment, the interconnection is implemented in the same packaged memory device using techniques such as through silicon vias (Through silicon via, TSVs) or short staggered wire bonds (short staggered wire bonding).
Drawings
The appended drawings illustrate only exemplary embodiments of the invention and therefore do not limit its scope, as the inventive concepts lend themselves to other equally effective embodiments.
FIG. 1a is a schematic diagram of an interconnect bus between a controller and a device in the prior art;
FIG. 1b is a schematic diagram of an interconnect bus between a controller and a device in the prior art;
FIG. 2a is a schematic diagram of an interconnection bus between a controller and a device according to an embodiment of the present invention;
FIG. 2b is a schematic diagram of an interconnection bus between a controller and a device according to an embodiment of the present invention;
FIG. 2c is a schematic diagram of an interconnection bus between a controller and a device according to an embodiment of the present invention;
FIG. 3a is a schematic diagram of an interconnection bus between a controller and a device according to an embodiment of the present invention;
FIG. 3b is a schematic diagram of an interconnection bus between a controller and a device according to an embodiment of the present invention;
FIG. 3c is a schematic diagram of an interconnection bus between a controller and a device according to an embodiment of the present invention;
FIG. 4a is a schematic diagram of an interconnection bus between a controller and a device according to an embodiment of the present invention;
FIG. 4b is a schematic diagram of an interconnection bus between a controller and a device according to an embodiment of the present invention;
FIG. 4c is a schematic diagram of an interconnection bus between a controller and a device according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a controller performing a read operation on a device according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a controller writing to a device in accordance with an embodiment of the invention;
FIG. 7a is a schematic diagram of an interconnection bus between a controller and a device according to an embodiment of the present invention;
FIG. 7b is a schematic diagram of an interconnection bus between a controller and a device according to an embodiment of the present invention;
FIG. 7c is a schematic diagram of an interconnection bus between a controller and a device according to an embodiment of the present invention;
FIG. 8a is a schematic diagram of an interconnection bus between a controller and a device according to an embodiment of the present invention;
FIG. 8b is a schematic diagram of an interconnection bus between a controller and a device according to an embodiment of the present invention;
FIG. 8c is a schematic diagram of an interconnection bus between a controller and a device according to an embodiment of the present invention;
FIG. 9 is a schematic diagram of a controller performing read and write operations on a device according to an embodiment of the present invention;
FIG. 10 is a schematic diagram of a controller performing read and write operations on a device according to an embodiment of the present invention;
FIG. 11 is a schematic diagram of a controller and apparatus using two TSV cross-column links in accordance with an embodiment of the present invention.
Detailed Description
Various aspects and examples of the present application will now be described. The following description provides specific details for a thorough understanding and enabling description of these examples. However, it will be understood by those skilled in the art that the present application may be practiced without many of these details.
In other instances, well-known structures or functions may not be shown or described in detail to facilitate a concise and thorough understanding of the relevant description.
The terminology used in the description presented below is intended to be interpreted in its broadest reasonable manner, even though it is being used in conjunction with a detailed description of certain specific examples of the application. Certain terms may even be emphasized below, however, any terms that are intended to be interpreted in any limited manner are specifically and distinctly defined in the descriptive section.
FIG. 2a depicts an embodiment of the invention in which memory controller 101 and memory devices 201-204 are both connected in a daisy-chain fashion with unidirectional point-to-point control bus 103 and unidirectional point-to-point data bus 102. The transmission direction of the partial unidirectional point-to-point data bus 102 is the direction of the output from the memory controller to the memory device, and the transmission direction of the partial unidirectional point-to-point data bus 102 is the direction of the input from the memory device to the memory controller.
FIG. 2b depicts an embodiment of the invention in which memory controller 101 and memory devices 201-204 are connected in a daisy chain fashion between two sets of unidirectional point-to-point control buses 103 and unidirectional point-to-point data buses 102. The transmission direction of the part of unidirectional point-to-point total control lines is the direction output from the memory controller to the memory device, the transmission direction of the part of unidirectional point-to-point total control lines is the direction input from the memory device to the memory controller, namely, one group of control buses is the output direction of the controller, and the other group of control buses is the input direction of the controller.
FIG. 2c depicts an embodiment of the present invention in which memory controller 101 and memory devices 201-204 are both connected in a daisy-chain fashion with a bidirectional point-to-point control bus 103 and a unidirectional point-to-point data bus 102.
FIG. 3a depicts an embodiment of the present invention in which memory controller 101 and memory devices 201-204 are both daisy-chained in a loop (or ring) of unidirectional point-to-point control bus 103 and unidirectional point-to-point data bus 102.
FIG. 3b depicts an embodiment of the invention in which memory controller 101 and memory devices 201-204 are connected in a shared control bus of unidirectional point-to-point control bus 103, and unidirectional point-to-point data bus 102 is connected in a circular loop (or daisy-chain) fashion.
FIG. 3c depicts an embodiment of the invention in which memory controller 101 and memory devices 201-204 are connected in a shared control bus of bi-directional point-to-point control bus 103, unidirectional point-to-point data bus 102 is connected in a circular loop (or daisy-chain) fashion.
The present embodiment forms a loop by connecting the last memory device of the daisy chain back to the memory controller and limits data to travel in only one direction in the daisy chain to increase the efficiency of the daisy chain connection of the system. The number of pins in the memory device is reduced relative to the prior art in this embodiment to achieve a daisy chain connection. Furthermore, the loop connection reduces the worst-case number of Hops (Hops) from the memory device to the controller to half compared to conventional daisy-chain designs, thus reducing bus latency.
FIG. 4a depicts an embodiment of the invention in which memory controller 101 and memory devices 201-204 are connected by unidirectional point-to-point control bus 103 having bus direction control capability and bidirectional point-to-point data buses connected in a pipelined daisy chain (pipelined daisy chain) fashion, the data buses being linked in series in one direction, thereby connecting memory devices 201-204 in the same direction, the memory devices 201-204 each making a bidirectional data connection. In other embodiments, the data buses may also be linked in series in different directions.
FIG. 4b depicts an embodiment of the invention in which memory controller 101 and memory devices 201-204 are connected by unidirectional shared control bus 103 having bus direction control capability and bi-directional point-to-point data bus 102 connected in a pipelined daisy-chain fashion, the data buses forming links in one direction, thereby connecting memory devices 201-204 in the same direction, the memory devices 201-204 each making a bi-directional data connection. In other embodiments, the data buses may also be linked in series in different directions.
FIG. 4c depicts an embodiment of the invention in which memory controller 101 and memory devices 201-204 are connected by a bi-directional shared control bus 103 having bus direction control capability and a bi-directional point-to-point data bus 102 connected in a pipelined daisy-chain fashion, the data buses forming links in one direction, thereby connecting memory devices 201-204 in the same direction, the memory devices 201-204 each making a bi-directional data connection. The control bus needs to provide bus direction information to all memory devices in the daisy chain connection. Fig. 5 depicts one example of control when the memory controller 101 READs data from an addressed memory device, bus direction control is set to READ (READ), and the data transfer direction is from the memory device to the memory controller. Fig. 6 depicts one example of control when the memory controller 101 WRITEs data to an addressed memory device, the bus direction control is set to WRITE (WRITE), and the data transfer direction is from the memory controller to the memory device. The memory controller of fig. 4a, 4b, 4c has the pin efficiency of the shared data bus of fig. 1a or 1b, but can operate at higher speeds due to the point-to-point bus load.
When the data bus direction of a point-to-point connection changes, some additional time is typically required to calibrate the timing and synchronize the two memory devices involved in the data transfer. In an example system where the memory device is a NAND flash memory device that performs block transfer, the change in data bus direction occurs only at the boundaries of the block transfer. If the time of calibration or synchronization is small compared to the rate of change of the data bus direction, then the time of calibration or synchronization is acceptable. In one embodiment of the invention, a clock signal may be distributed from the controller to all memory devices as part of the control bus so that each memory device may use it to reduce the synchronization time when switching the direction of the data bus. In addition, data strobe signals may be included in the data bus design to simplify the clock signal and data recovery design and to reduce recovery time when changing the data bus direction.
FIG. 7a depicts a system having a memory controller supporting two pipelined daisy-chained data bus connections, including one pipelined daisy-chained data bus of memory devices 201-204 and one pipelined daisy-chained data bus of memory devices 301-304. The memory controller is linked to the pipeline buses of the memory devices 201-204 by a set of unidirectional point-to-point control buses 103. The memory controller is linked with the pipelined buses of memory devices 301-304 by another set of unidirectional point-to-point control buses 103. The memory controller can only transfer data to one addressed memory device in each pipeline daisy chain at the same time.
FIG. 7b depicts a system having a memory controller supporting two pipelined daisy-chained data bus connections, including one pipelined daisy-chained data bus of memory devices 201-204 and one pipelined daisy-chained data bus of memory devices 301-304. All memory devices in the system share the same unidirectional control bus 401. The memory controller can only transfer data to one addressed memory device in each pipeline daisy chain at the same time.
FIG. 7c depicts a system having a memory controller supporting two pipelined daisy-chained data bus connections, including one pipelined daisy-chained data bus of memory devices 201-204 and one pipelined daisy-chained data bus of memory devices 301-304. All memory devices in the system share the same bidirectional control bus 103. The memory controller can only transfer data to one addressed memory device in each pipeline daisy chain at the same time.
FIG. 8a depicts an embodiment of the invention in which all data buses form a daisy chain of loop circuits, i.e., connecting data buses between two memory devices in two pipeline daisy chains that are remote from the memory controller 101. All memory devices 201-204, 301-304 in this system are serially linked by unidirectional point-to-point control bus 103 to form a daisy chain of loops. The memory controller can access any two memory devices in the loop simultaneously.
FIG. 8b depicts an embodiment of the invention in which all data buses form a daisy chain of loop circuits, i.e., connecting data buses between two memory devices in two pipeline daisy chains that are remote from the memory controller 101. All memory devices 201-204, 301-304 in this system share the same single control bus. The memory controller can access any two memory devices in the loop simultaneously.
FIG. 8c depicts an embodiment of the invention in which all data buses form a daisy chain of loop circuits, i.e., connecting data buses between two memory devices in two pipeline daisy chains that are remote from the memory controller 101. All memory devices 201-204, 301-304 in this system share the same bidirectional control bus. The memory controller can access any two memory devices in the loop simultaneously.
FIG. 9 depicts one embodiment of the invention in which the data buses form a daisy chain of loop circuits. All memory devices in this system share the same control bus. In this figure, the memory controller 101 reads from both the memory device 202 and the memory device 203, the memory controller 101 reads data in the addressed memory device 202 through a first branch formed by the data buses of the memory devices 202, 201, and the memory controller 101 reads data in the addressed memory device 203 through a second branch formed by the data buses between the memory devices 203, 204, 304-301.
FIG. 10 depicts an embodiment of the invention in which the daisy chain of data buses is in a loop. All memory devices in this system share the same control bus. In this figure, the memory controller 101 is reading from the memory device 202 and simultaneously writing to the memory device 203, the memory controller 101 reads data in the addressed memory device 202 through a first branch formed by the data buses of the memory devices 202, 201, and writes data into the addressed memory device 203 through a second branch formed by the data buses between the memory devices 203, 204, 304-301.
Wherein the first branch and the second branch are combined to form a loop. With respect to the links shown in fig. 7, the memory controller 101 in fig. 8 may operate on two memory devices in a daisy chain of pipelines at the same time, e.g., read operations at the same time, write operations at the same time, or both read and write operations, respectively.
In an embodiment of the invention, the memory controller is configured to be connected to the plurality of memory devices to form one or more of a unidirectional point-to-point data bus loop, a bidirectional point-to-point data bus loop, or a data bus link in one direction, i.e. the memory controller 101 in fig. 3a, 3b, 3c, 4a, 4b, 4c, and 8 may be extended to include a plurality of memory devices in a pipelined daisy chain connection or a loop daisy chain connection, and the various embodiments illustrated above may be combined with each other.
In an embodiment, the plurality of memory devices are NAND flash memory, such as slow NAND flash memory or fast NAND flash memory, or Storage Class Memory (SCM) memory, such as 3DXP memory, or non-volatile memory, or a combination thereof.
In one embodiment of the invention, all memory devices in a pipeline daisy chain connection or a loop connection are identical, having similar memory types and similar memory access times. In another embodiment of the invention, the memory devices in the daisy chain connection or the loop connection are different, e.g. have different memory types and/or different access delays. In the latter case, the memory controller needs to include additional timing control logic to track the state of all memory devices in the system. For example, in fig. 8, 204 is a memory device having a long memory access time and 201 has a short memory access time.
In one embodiment, the plurality of memory devices are stacked in the same package structure and interconnected by through silicon vias. The plurality of memory devices and/or the memory devices and the memory controller are connected through silicon through holes.
In this application, the memory controller may be connected to one or more memory devices to form one or more loops or links, i.e., the memory controller is configured to be connected to the plurality of memory devices to form one or more of a unidirectional point-to-point data bus loop, a bidirectional point-to-point data bus loop, or a data bus link in one direction. For example, the memory controller 101 shown in FIGS. 7 a-7 c forms two links with memory devices 201-204 and memory devices 301-304, respectively. It should be appreciated that other connections between the memory controller and the plurality of memory devices may be used, for example, to form two loops.
In one embodiment of the invention, all of the memory devices in the daisy chain connection or the loop connection are packaged in one apparatus, while the memory controller and the memory devices may be packaged in the same apparatus or the memory controller may be in another apparatus alone. As shown in fig. 11, the memory devices 201, 301, 202, 302 are packaged in one apparatus, the memory devices 201, 301, 202, 302 are in the same daisy chain connection or loop connection, the memory controller 101 and the memory devices 201, 301, 202, 302 are packaged in the same apparatus or are packaged separately in another apparatus, the present invention uses a technology such as through silicon vias (Through silicon via, TSV) to implement interconnection, the bus load between the memory devices in the same package structure can be reduced, and the bus load between the memory devices in the same package structure can be kept small. The speed between a memory controller and an adjacent memory device in a daisy chain or loop may be limited by a point-to-point bus. In another embodiment of the invention, the memory devices in the same package structure may also be interconnected using short cross wire bonding (short staggered wire bonding) techniques.
In an embodiment, at least one bidirectional data bus interface of the memory device supports dual mode: conventional mode of small load driving between memory devices, enhanced mode of large load driving between memory devices and memory controller.
It should be noted that all or any of the embodiments described above may be combined with one another unless otherwise stated or such embodiments may be functionally and/or architecturally exclusive of one another.
Although the present application has been described in connection with the specific exemplary embodiments cited herein, the present application is not limited to the embodiments described herein but may be practiced with modification and alteration within the spirit and scope of the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
From the foregoing, it will be appreciated that specific embodiments of the application have been described herein for purposes of illustration, but that various modifications may be made without deviating from the scope of the application. Accordingly, the application is not to be limited except as by the appended claims.
Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. The present application relates to embodiments having these features in common even if the particular features are recited in different dependent claims. Any reference signs in the claims shall not be construed as limiting the scope.
Features and aspects of different embodiments can be incorporated into other embodiments, and the embodiments shown in this document can be implemented without all of the illustrated or described features or aspects. Those skilled in the art will note that while specific examples of, and embodiments for, the present systems and methods are described for illustrative purposes, various modifications can be made without departing from the spirit and scope of the present application. Furthermore, features of one embodiment may be incorporated into another embodiment even if the features are not described together in a single embodiment in this document. Accordingly, the application is described by the appended claims.
Claims (11)
1. A bus for interconnecting a memory controller and a memory device, comprising:
the memory device comprises a plurality of unidirectional point-to-point data buses, a plurality of memory devices and a memory controller, wherein the plurality of memory devices are connected in series in sequence to form links, the transmission direction of part of unidirectional point-to-point data buses is the direction from the memory controller to the memory device, and the transmission direction of part of unidirectional point-to-point data buses is the direction from the memory device to the memory controller;
a plurality of point-to-point control buses configured to respectively connect the plurality of memory devices with the memory controller.
2. The bus of claim 1, wherein the memory controller performs a read operation through a first leg formed by a partial unidirectional point-to-point data bus transfer direction being the direction from the memory controller output to the memory device, and the memory controller performs a read operation through a second leg formed by a partial unidirectional point-to-point data bus transfer direction being the direction from the memory controller output to the memory device, wherein the first leg and the second leg form a loop.
3. The bus of claim 1, wherein the memory controller performs a read operation through a first leg formed by a partial unidirectional point-to-point data bus transfer direction being the direction from the memory controller output to the memory device, and the memory controller performs a write operation through a second leg formed by a partial unidirectional point-to-point data bus transfer direction being the direction from the memory controller output to the memory device, wherein the first leg and the second leg form a loop.
4. The bus of claim 1, wherein the plurality of memory devices and the memory controller are each connected by a plurality of control buses that are bi-directionally shared.
5. Bus according to claim 1, characterized in that between the plurality of memory devices and/or between the memory devices and the memory controller are connected by means of through-silicon vias.
6. The bus of claim 5, wherein the plurality of memory devices are stacked in a same package structure and interconnected by through silicon vias.
7. The bus of claim 1, wherein the plurality of point-to-point control buses comprises a plurality of unidirectional point-to-point total control buses, wherein a unidirectional point-to-point total control bus transmission direction is a direction output from the memory controller to the memory device.
8. The bus of claim 1, wherein the plurality of point-to-point control buses comprises a plurality of unidirectional point-to-point total control buses, wherein a portion of unidirectional point-to-point total control bus transmission directions are directions from the memory controller to the memory device and a portion of unidirectional point-to-point total control bus transmission directions are directions from the memory device to the memory controller.
9. The bus of claim 1, wherein the plurality of point-to-point control buses are bidirectional buses.
10. The bus of claim 1, wherein the memory controller is coupled to one or more memory devices to form one or more loops or links.
11. An apparatus for implementing a plurality of memory devices directly interconnected with a memory controller using a bus as claimed in any one of claims 1 to 10.
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| Application Number | Priority Date | Filing Date | Title |
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| PCT/CN2020/091333 WO2021012767A1 (en) | 2019-07-22 | 2020-05-20 | Bus for interconnection between memory controller and memory devices |
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| CN2019106612837 | 2019-07-22 | ||
| CN201910661283 | 2019-07-22 |
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