CN112271162B - Semiconductor device and manufacturing method - Google Patents
Semiconductor device and manufacturing method Download PDFInfo
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- CN112271162B CN112271162B CN202011017654.7A CN202011017654A CN112271162B CN 112271162 B CN112271162 B CN 112271162B CN 202011017654 A CN202011017654 A CN 202011017654A CN 112271162 B CN112271162 B CN 112271162B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/564—Details not otherwise provided for, e.g. protection against moisture
Abstract
The invention provides a semiconductor device and a manufacturing method, comprising the following steps: a stacked structure on the substrate and a dielectric layer covering the substrate surface and the stacked structure; a first sealing ring and a second sealing ring which penetrate through the dielectric layer to the substrate are formed in the dielectric layer covering the surface of the substrate, the first sealing ring and the second sealing ring surround the stacked structure, and the first sealing ring is located between the second sealing ring and the stacked structure; and a through hole penetrating through the dielectric layer and exposing the substrate is formed in the dielectric layer between the first sealing ring and the second sealing ring, and a filling layer is formed in the through hole. Therefore, the medium layer between the first sealing ring and the second sealing ring can be supported after the filling layer is formed in the through hole, the medium layer between the first sealing ring and the second sealing ring is prevented from inclining, the first sealing ring and the second sealing ring with high quality are further formed, the effect of the formed sealing rings is improved, and the high-quality sealing rings are beneficial to improving the alignment precision of the subsequent process.
Description
Technical Field
The present invention relates to semiconductor devices and manufacturing technologies, and in particular, to a semiconductor device and a manufacturing method thereof.
Background
When a chip is packaged, it needs to be cut first, and the mechanical force of cutting may cause a micro crack at the edge of the chip, and the crack may extend to the circuit area of the chip to cause damage to the circuit area. In order to protect the circuit region of the chip, a seal ring (seal ring) is generally disposed between the circuit region of the chip and the scribe line to prevent cracks from extending to the circuit region of the chip.
The seal ring is formed mainly by forming two deep grooves in the dielectric layer and then filling the deep grooves. However, after two deep grooves are formed in the dielectric layer, the dielectric layer between the deep grooves is prone to toppling, so that the line widths of the two deep grooves are inconsistent, filling of the deep groove with the smaller line width is hindered, the effect of the formed sealing ring is affected, and alignment of a subsequent process is affected.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which can improve the effect of a formed seal ring.
In order to achieve the purpose, the invention has the following technical scheme:
a semiconductor device, comprising:
the device comprises a substrate, a stacked structure on the substrate and a dielectric layer covering the surface of the substrate and the stacked structure;
forming a first sealing ring and a second sealing ring which penetrate through the dielectric layer to the substrate in the dielectric layer covering the surface of the substrate, wherein the first sealing ring and the second sealing ring surround the stacked structure and the first sealing ring is positioned between the second sealing ring and the stacked structure;
and a through hole which penetrates through the medium layer and exposes out of the substrate is formed in the medium layer between the first sealing ring and the second sealing ring, and a filling layer is formed in the through hole.
Optionally, the through hole penetrates through the dielectric layer into the substrate to support the dielectric layer between the first sealing ring and the second sealing ring.
Optionally, the through hole penetrates through the dielectric layer to the substrate, and the hardness of the filling material of the filling layer is greater than the hardness of the dielectric material of the dielectric layer.
Optionally, the number of the through holes is multiple, and the through holes are annularly arranged along the first sealing ring to surround the stacked structure.
Optionally, the dielectric layer between the first seal ring and the second seal ring encloses a dielectric ring, the through holes are annularly arranged along the first seal ring, and the through holes in adjacent rings are arranged in a staggered manner in the width direction of the dielectric ring.
Optionally, the semiconductor device is a three-dimensional memory.
A method of manufacturing a semiconductor device, comprising:
providing a substrate, forming a stacked structure on the substrate and forming a dielectric layer covering the surface of the substrate and the stacked structure;
forming a through hole which penetrates through the dielectric layer and exposes the substrate in the dielectric layer covering the surface of the substrate, and forming a filling layer in the through hole;
forming a first sealing ring and a second sealing ring which penetrate through the dielectric layer to the substrate in the dielectric layer covering the surface of the substrate, wherein the first sealing ring and the second sealing ring surround the stacked structure, the first sealing ring is located between the second sealing ring and the stacked structure, and the through hole is located in the dielectric layer between the first sealing ring and the second sealing ring.
Optionally, the number of the through holes is multiple, and the through holes are annularly arranged along the first sealing ring to surround the stacked structure.
Optionally, the dielectric layer between the first seal ring and the second seal ring encloses a dielectric ring, the through holes are annularly arranged along the first seal ring, and the through holes in adjacent rings are arranged in a staggered manner in the width direction of the dielectric ring.
Optionally, the stack layer includes a core storage region and a step region, a channel hole is formed in the core storage region, a dummy channel hole is formed in the step region, and the through hole is formed together with the dummy channel hole and/or the channel hole.
The semiconductor device provided by the embodiment of the invention comprises: the device comprises a substrate, a stacked structure on the substrate and a dielectric layer covering the surface of the substrate and the stacked structure; a first sealing ring and a second sealing ring which penetrate through the dielectric layer to the substrate are formed in the dielectric layer covering the surface of the substrate, the first sealing ring and the second sealing ring surround the stacked structure, and the first sealing ring is located between the second sealing ring and the stacked structure; and a through hole penetrating through the dielectric layer and exposing the substrate is formed in the dielectric layer between the first sealing ring and the second sealing ring, and a filling layer is formed in the through hole. Therefore, the through hole penetrating through the dielectric layer and exposing the substrate is formed in the dielectric layer between the first sealing ring and the second sealing ring, the dielectric layer between the first sealing ring and the second sealing ring can be supported after the filling layer is formed in the through hole, the dielectric layer between the first sealing ring and the second sealing ring is prevented from inclining, the first sealing ring and the second sealing ring with high quality are formed, the effect of the formed sealing rings is improved, and the high-quality sealing rings are favorable for improving the alignment precision of the subsequent process.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 shows a schematic flow diagram of a method of manufacturing a semiconductor device according to an embodiment of the invention;
fig. 2 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention;
fig. 3 is a schematic diagram illustrating a top view of a semiconductor device according to an embodiment of the present invention;
FIG. 4 illustrates a schematic top view of a partial structure of a semiconductor device in accordance with an embodiment of the present invention;
FIG. 5 illustrates a cross-sectional view of a partial structure of a semiconductor device in accordance with an embodiment of the present invention;
fig. 6 shows a schematic top view of a partial structure of a semiconductor device according to an embodiment of the invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described and will be readily apparent to those of ordinary skill in the art without departing from the spirit of the present invention, and therefore the present invention is not limited to the specific embodiments disclosed below.
As described in the background art, after two deep trenches are formed in a dielectric layer, the dielectric layer between the deep trenches is prone to toppling, which results in inconsistent line widths of the two deep trenches, thereby hindering metal filling of the deep trenches with smaller line widths, affecting the effect of the formed seal ring, and affecting alignment of subsequent processes.
To this end, an embodiment of the present application provides a semiconductor device, which is shown in fig. 2 to 4, where fig. 2 is a cross-sectional structural diagram of the semiconductor device, fig. 3 is a top structural diagram of the semiconductor device, and fig. 4 is a top view of a partial structure of the semiconductor device, and includes:
the structure comprises a substrate 100, a stacked structure 110 on the substrate 100 and a dielectric layer 102 covering the surface of the substrate 100 and the stacked structure 110;
forming a first seal ring 104 and a second seal ring 106 in the dielectric layer 102, wherein the first seal ring 104 and the second seal ring 106 penetrate through the dielectric layer 102 to the substrate 100, the first seal ring 104 and the second seal ring 106 surround the stacked structure 110, and the first seal ring 104 is located between the second seal ring 106 and the stacked structure 110;
a through hole 112 penetrating through the dielectric layer 102 and exposing the substrate 100 is formed in the dielectric layer 102 between the first seal ring 104 and the second seal ring 106, and a filling layer is formed in the through hole 112.
In the embodiment of the present application, the substrate 100 may be a semiconductor substrate, and for example, may be a Si substrate, a Ge substrate, a SiGe substrate, an SOI (Silicon On Insulator) or a GOI (germanium On Insulator). In other embodiments, the substrate 100 may also include other elemental or compound semiconductor substrates, such as GaAs, InP, SiC, etc., as well as stacked structures, such as Si/SiGe, etc., as well as other epitaxial structures, such as SGOI (Silicon Germanium On Insulator), etc. In this embodiment, the substrate 100 may be a silicon substrate.
A stack structure 110 is formed on the substrate 100, and the stack structure 110 may be formed by alternately stacking an insulating layer, which may be silicon oxide (SiO), and a gate electrode layer2) The gate layer may be tungsten (W). Substrate 100 surface and stacked junctionThe structure 110 is covered with a dielectric layer 102, and the dielectric layer 102 may be a single layer or a stacked structure, and may be one or more of Silicon nitride, Silicon oxide, or NDC (Nitrogen doped Silicon Carbide) dielectric materials.
The dielectric layer 102 may have a device structure and an interconnection structure electrically connected to the device structure, the device structure may include a MOS device, a sensing device, a storage device, or other passive devices other than a capacitor, the storage device may include a non-volatile memory, such as a floating gate transistor, a ferroelectric memory, a phase change memory, or the like, such as a NOR flash memory, a NAND flash memory, or the like, the device structure may be a planar device or a stereo device, the stereo device may be a FIN-FET (FIN field effect transistor), a three-dimensional memory, or the like, the sensing device may be a photosensitive device, or the like, and the other passive devices include a resistor, an inductor, or the like. The interconnection structure of the device structure may include contact plugs, vias and wire holes, and the interconnection structure may be a metal material, such as tungsten, aluminum, copper, and the like.
A first seal ring 104 and a second seal ring 106 are formed in the dielectric layer 102 covering the surface of the substrate 100 and penetrate through the dielectric layer 102 onto the substrate 100, the first seal ring 104 and the second seal ring 106 surround the stacked structure 110, and the first seal ring 104 is located between the second seal ring 106 and the stacked structure 110, as shown in fig. 2 and 3. It will be appreciated that the stacked structure 110 is positioned within the first seal ring 104 and the first seal ring 104 is positioned within the second seal ring 106, with the first seal ring 104 having a smaller ring diameter than the second seal ring 106. The inner region of the first sealing ring 104 may be a device structure region, and the outer region of the second sealing ring 106 may be a scribe line region, so as to isolate the device structure in the dielectric layer 102 from the scribe line, thereby preventing cracks generated in the process of cutting the chip by using the scribe line from extending to the device structure and affecting the performance of the device structure.
The first seal ring 104 and the second seal ring 106 may be identical or different in shape, may be circular or square, and may be rectangular or square, for example. The first sealing ring 104 and the second sealing ring 106 may be parallel to each other, for example, two annular metal frames parallel to each other, and a certain interval is provided between the two annular metal frames, and the size of the interval may be determined according to actual situations.
The first seal ring 104 and the second seal ring 106 may be formed simultaneously or separately. For example, a photoresist layer is formed on the dielectric layer 102, a pattern of the first seal ring 104 and the second seal ring 106 is formed in the photoresist layer by processes of exposure, development and the like, and then the dielectric layer 102 is etched by taking the patterned photoresist layer as a mask, so that two deep grooves are formed in the dielectric layer 102, and the interval between the deep grooves is determined according to actual conditions. The deep trench is then filled, thereby forming a first seal ring 104 and a second seal ring 106 in the dielectric layer 102, and the material filling the deep trench may be a metallic material.
However, the applicant finds that after two deep grooves are formed in the dielectric layer 102, the dielectric layer 102 between the two deep grooves 102 is prone to tilt, so that the line widths of the two deep grooves are inconsistent, the filling of the deep grooves is affected, and the effect of the sealing ring is further affected.
Accordingly, applicants formed a via 112 through dielectric layer 102 and exposing substrate 100 in dielectric layer 102 between first seal ring 104 and second seal ring 106, with a fill layer formed in via 112.
In this embodiment, the through hole 112 penetrates through the dielectric layer 102 and extends into the substrate 100, and since the through hole 112 is rooted in the substrate 100, after a filling layer is formed in the through hole 112, the through hole can support the dielectric layer 102 between the first sealing ring 104 and the second sealing ring 106, so as to stabilize the dielectric layer 102 between the first sealing ring 104 and the second sealing ring, prevent the dielectric layer 102 between the first sealing ring 104 and the second sealing ring 106 from tilting, further form the first sealing ring 104 and the second sealing ring 106 with high quality, improve the effect of the formed sealing rings, and facilitate the alignment precision of the subsequent process.
In this embodiment, the through hole 112 penetrates through the dielectric layer 102 onto the substrate 100, that is, the through hole 112 does not extend into the substrate 100, and the hardness of the filling material in the through hole 112 is greater than that of the dielectric material of the dielectric layer 102. In this way, the via 112 structure is not prone to collapse due to the hardness of the filler material being greater than the hardness of the dielectric material, and can support the dielectric layer between the first seal ring 104 and the second seal ring 106.
In this embodiment, the number of the through holes 112 may be multiple, and the through holes 112 may be arranged in a ring shape along the first sealing ring 104 to surround the stacked structure 110, as shown in fig. 3. Specifically, the through holes 112 may be annularly arranged along the outer side of the first sealing ring 104 or the inner side of the second sealing ring 106, and the plurality of through holes surround the outer side of the first sealing ring 104, so as to support any position of the dielectric layer 102 between the first sealing ring 104 and the second sealing ring 106, thereby improving the supporting effect on the dielectric layer 102, and the distances between the through holes 112 annularly arranged may be the same or different. In a specific embodiment, the annular frame formed after the through holes 112 are arranged in a ring shape may be parallel to the annular frame of the first sealing ring 104 and/or the second sealing ring 106.
In this embodiment, the dielectric layer 102 between the first seal ring 104 and the second seal ring 106 encloses a dielectric ring, the through holes 112 may be arranged in a plurality of rings along the outer side of the first seal ring 104 or the inner side of the second seal ring 106, and the through holes 112 in adjacent rings are arranged in a staggered manner in the width direction of the dielectric ring. Specifically, a ring array may be formed in the dielectric ring of the through holes 112, the ring array may include a plurality of ring structures, and the through holes 112 in adjacent ring structures are arranged in a staggered manner in the width direction of the dielectric ring, as shown in fig. 5 and fig. 6, fig. 5 is a cross-sectional view of a local structure of a semiconductor device, and fig. 6 is a top view of the local structure of the semiconductor device, and the through holes 112 arranged in a staggered manner can improve a supporting effect on the dielectric layer 102. In a specific application, the through holes 112 of each ring structure may be uniformly distributed at equal intervals, and the intervals of the through holes 112 on different ring structures may be the same, or of course, may be different.
In a specific application, the semiconductor device may be a three-dimensional memory, and the stacked structure in the first seal ring 104 may be formed by alternately stacking sacrificial layers and insulating layers. With the increase of the requirement on the number of memory cells, the number of stacked layers is continuously increased, and when two deep grooves are formed by etching the stacked layers, the dielectric layer between the deep grooves is more prone to incline due to the increase of the depth-to-width ratio, so that the line widths of the two deep grooves are inconsistent. A through hole 112 is formed in the stacking layer between the two deep grooves, a filling layer is formed in the through hole 112, the filling layer tightly connects the substrate and the stacking layer together, the stacking layer can be supported, and the stacking layer between the two deep grooves for forming the sealing ring is prevented from inclining.
As described in detail above, the through hole penetrating through the dielectric layer and exposing the substrate is formed in the dielectric layer between the first sealing ring and the second sealing ring, and the dielectric layer between the first sealing ring and the second sealing ring can be supported after the filling layer is formed in the through hole, so that the dielectric layer between the first sealing ring and the second sealing ring is prevented from being inclined, and thus the first sealing ring and the second sealing ring with high quality are formed, the effect of the formed sealing ring is improved, and the high-quality sealing ring is favorable for improving the alignment precision of the subsequent process.
An embodiment of the present application further provides a method for manufacturing a semiconductor device, which is shown in fig. 1 and includes:
in step S01, a substrate 100 is provided, a stacked structure 110 is formed on the substrate 100, and a dielectric layer 102 is formed to cover the surface of the substrate 100 and the stacked structure 110, as shown in fig. 2.
In the embodiment of the present application, the substrate 100 plays a role of supporting a device structure, and the substrate 100 may be a semiconductor substrate, for example, a Si substrate, a Ge substrate, a SiGe substrate, an SOI (Silicon On Insulator) or a GOI (germanium On Insulator) and the like.
A stack structure 110 is formed on the substrate 100, and the stack structure 110 may be formed by alternately stacking an insulating layer, which may be silicon oxide (SiO), and a gate electrode layer2) The gate layer may be tungsten (W). The dielectric layer 102 covers the surface of the substrate 100 and the stacked structure 110, and the dielectric layer 102 may be a single layer or a stacked structure, and may be a dielectric material such as Silicon nitride, Silicon oxide, or NDC (Nitrogen doped Silicon Carbide)One or more of the materials.
A device structure may be formed in the dielectric layer 102, specifically, the device structure may be formed on the substrate 100, and then a dielectric material is deposited on the substrate 100 by using a chemical vapor deposition process or the like, so as to form the dielectric layer 102 covering the device structure, where the dielectric layer 102 plays a role in protecting the device structure.
In step S02, a via 112 is formed in the dielectric layer 102 covering the surface of the substrate 100, penetrating through the dielectric layer 102 and exposing the substrate 100, and a filling layer is formed in the via 112, as shown with reference to fig. 2.
In this embodiment, the method for forming the through hole 112 may be to form a photoresist layer on the dielectric layer 102, perform a patterning process on the photoresist layer by using a photolithography process to form a through hole pattern in the photoresist layer, and then etch the dielectric layer 102 until the substrate 100 is exposed by using the patterned photoresist layer as a mask. The photoresist layer may then be removed.
In this embodiment, the through hole 112 penetrates through the dielectric layer 102 onto the substrate 100, and does not penetrate into the substrate 100 at this time, and a filling material having a hardness greater than that of the dielectric material may be filled in the through hole 112, so that the through hole 112 is not easy to collapse due to the higher hardness of the filling material.
In this embodiment, the through hole 112 may also penetrate through the dielectric layer 102 into the substrate 100, and at this time, after the dielectric layer 102 is etched to expose the substrate 100, the substrate 100 is further etched to form the through hole 112 in the substrate 100, and since a part of the through hole 112 is formed in the substrate 100, the through hole 112 can support the dielectric layer 102 after a filling layer is formed in the through hole 112. In this embodiment, the filling material of the filling layer may be the same as or different from the material of the dielectric layer 102, and may be, for example, silicon oxide. During the filling process, a dielectric material is deposited on the dielectric layer 102, and a planarization process may be performed to remove the dielectric material on the dielectric layer 102, so as to form a filling layer only in the via 112.
In step S03, a first seal ring 104 and a second seal ring 106 are formed in the dielectric layer 102 covering the surface of the substrate 100, the first seal ring 104 and the second seal ring 106 surrounding the stacked structure 110, the first seal ring 104 being located between the second seal ring 106 and the stacked structure 110, and a via hole being located in the dielectric layer 102 between the first seal ring 104 and the second seal ring 106, as shown in fig. 2.
In this embodiment, after the filling layer is formed in the through hole 112, two deep grooves may be formed on two sides of the through hole 112, specifically, a photoresist layer may be formed on the dielectric layer 102, then patterns of the first seal ring 104 and the second seal ring 106 are formed in the photoresist layer, the photoresist layer is used as a mask, and the dielectric layer 102 is etched until the surface of the substrate 100 is exposed, so as to form two deep grooves in the dielectric layer 102 on two sides of the through hole 112. Then, the deep groove is filled, and a planarization process is performed to form a filling material only in the deep groove, thereby forming the first and second seal rings 104 and 106.
In this embodiment, the number of the through holes 112 may be multiple, and the through holes 112 may be annularly arranged along the outer side of the first sealing ring 104 or the inner side of the second sealing ring 106 to surround the stacked structure 110, as shown in fig. 4.
In this embodiment, the dielectric layer 102 between the first seal ring 104 and the second seal ring 106 encloses a dielectric ring, and the through holes 112 may be arranged in a plurality of rings along the outer side of the first seal ring 104 or the inner side of the second seal ring 106. That is, the through holes 112 form a ring array in the dielectric layer 102 between the first seal ring 104 and the second seal ring 106, the ring array may include a plurality of ring structures, and the through holes 112 in adjacent ring structures are staggered in the width direction of the dielectric ring, as shown in fig. 5 and 6. The through holes 112 of each ring structure may be uniformly distributed at equal intervals, and the intervals of the through holes 112 on different ring structures may be the same, but may also be different.
In this embodiment, the first seal ring 104 is located in the second seal ring, the stacked structure 110 in the first seal ring 104 is a stacked layer in which insulating layers and sacrificial layers are alternately stacked, the insulating layer may be made of silicon oxide, and the sacrificial layer may be made of silicon nitride. The stack may include a core storage region generally in a central region of the stack and a plateau region generally around the core storage region. In a specific application, a step structure may be formed in the step region after the stacked layers are formed. A trench hole is formed in the core storage region, and the stacked layers of the core storage region may be etched by an etching technique until the surface of the substrate 100 is exposed, so as to form a trench hole, which is used to form a memory cell. A dummy channel hole is formed in the step region, and the dummy channel hole is used for forming a channel hole of a non-memory cell, and is generally a through hole penetrating through the substrate and filled with a dielectric material, and plays a role in supporting the step in a sacrificial layer replacement process.
In this embodiment, the through holes 112 may be formed in the step of forming the dummy channel holes, and the dummy channel holes and the through holes 112 may be formed simultaneously by one etching process, so that the through holes 112 may be formed in the step of forming the channel holes, thereby simplifying the process flow and reducing the manufacturing cost, and the dummy channel holes and the through holes 112 may be formed in the step of forming the channel holes, thereby further simplifying the process flow.
The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on different points from other embodiments.
The foregoing is only a preferred embodiment of the present invention, and although the present invention has been disclosed in the preferred embodiments, it is not intended to limit the present invention. Those skilled in the art can make many possible variations and modifications to the disclosed embodiments, or modify equivalent embodiments, using the methods and techniques disclosed above, without departing from the scope of the claimed invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the protection scope of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.
Claims (10)
1. A semiconductor device, comprising:
the device comprises a substrate, a stacked structure on the substrate and a dielectric layer covering the surface of the substrate and the stacked structure;
forming a first sealing ring and a second sealing ring which penetrate through the dielectric layer to the substrate in the dielectric layer covering the surface of the substrate, wherein the first sealing ring and the second sealing ring surround the stacked structure and the first sealing ring is positioned between the second sealing ring and the stacked structure;
a through hole penetrating through the dielectric layer and exposing the substrate is formed in the dielectric layer between the first sealing ring and the second sealing ring, a filling layer is formed in the through hole, and the hardness of a filling material of the filling layer is greater than that of a dielectric material of the dielectric layer.
2. The device of claim 1, wherein the via extends through the dielectric layer into the substrate to support the dielectric layer between the first seal ring and the second seal ring.
3. The device of claim 1, wherein the via penetrates the dielectric layer to the substrate.
4. The device of any of claims 1-3, wherein the number of vias is multiple, the vias being arranged in a ring along the first seal ring to surround the stacked structure.
5. The device of claim 4, wherein the dielectric layer between the first seal ring and the second seal ring encloses a dielectric ring, the through holes are arranged in a plurality of rings along the first seal ring, and the through holes in adjacent rings are arranged in a staggered manner in a width direction of the dielectric ring.
6. The device of claim 1, wherein the semiconductor device is a three-dimensional memory.
7. A method of manufacturing a semiconductor device, comprising:
providing a substrate, forming a stacked structure on the substrate and forming a dielectric layer covering the surface of the substrate and the stacked structure;
forming a through hole which penetrates through the dielectric layer and exposes the substrate in the dielectric layer covering the surface of the substrate, and forming a filling layer in the through hole; the hardness of the filling material of the filling layer is greater than that of the medium material of the medium layer;
forming a first sealing ring and a second sealing ring which penetrate through the dielectric layer to the substrate in the dielectric layer covering the surface of the substrate, wherein the first sealing ring and the second sealing ring surround the stacked structure, the first sealing ring is located between the second sealing ring and the stacked structure, and the through hole is located in the dielectric layer between the first sealing ring and the second sealing ring.
8. The manufacturing method according to claim 7, wherein the number of the through-holes is plural, and the through-holes are arranged annularly along the first seal ring so as to surround the stacked structure.
9. The manufacturing method according to claim 8, wherein the dielectric layer between the first seal ring and the second seal ring is enclosed to form a dielectric ring, the through holes are arranged in a plurality of rings along the first seal ring, and the through holes in adjacent rings are arranged in a staggered manner in the width direction of the dielectric ring.
10. The manufacturing method according to claim 7, wherein the stacked structure includes a core storage region in which a channel hole is formed and a step region in which a dummy channel hole is formed, and the via hole is formed together with the dummy channel hole and/or the channel hole.
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| CN203826393U (en) * | 2014-05-07 | 2014-09-10 | 中芯国际集成电路制造(北京)有限公司 | Sealing ring structure |
| CN105374765A (en) * | 2014-09-02 | 2016-03-02 | 中芯国际集成电路制造(上海)有限公司 | Chip sealing ring structure and manufacturing method thereof |
| CN111370368A (en) * | 2020-03-06 | 2020-07-03 | 长江存储科技有限责任公司 | Semiconductor chip sealing ring and manufacturing method thereof |
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