CN112259586B - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
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- CN112259586B CN112259586B CN202011129744.5A CN202011129744A CN112259586B CN 112259586 B CN112259586 B CN 112259586B CN 202011129744 A CN202011129744 A CN 202011129744A CN 112259586 B CN112259586 B CN 112259586B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
Abstract
The present invention relates to a display panel and a display device, the display panel includes: a substrate; the demultiplexing circuit is formed in a non-display area of the substrate and comprises a plurality of groups of thin film transistor units which are arranged at intervals along a first direction, and each group of thin film transistor units comprises at least one thin film transistor; a plurality of groups of dummy units formed in a non-display area of the substrate, each group of dummy units including at least one dummy semiconductor monomer; the dummy unit is arranged between two groups of thin film transistor units which are adjacently arranged in the first direction, the distance between the thin film transistor unit in any group and the thin film transistor unit in the other group which is most adjacent to the thin film transistor unit in any group is smaller than a preset distance, or the distance between the thin film transistor unit in any group and the dummy unit which is most adjacent to the thin film transistor unit in any group is smaller than the preset distance. The display panel effectively improves the arrangement uniformity of the circuit modules in the non-display area, and effectively eliminates the TFT characteristic difference caused by different arrangement densities of the thin film transistor units.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a display panel and a display device.
Background
In electronic devices such as mobile phones and tablet computers, users have higher and higher requirements for the frame width of display panels, and as the frame is narrower and narrower, the layout space of the demultiplexing circuit is smaller and smaller, resulting in the dense arrangement of circuit modules of the demultiplexing circuit in a limited space. The density of the circuit module arrangements is different, which causes the TFT characteristics (including parameters such as on-state current, off-state current, on-voltage, electron mobility, and on-off current ratio) of the thin film transistors in the demultiplexing circuit to be different, and finally affects the display effect of the display panel.
Disclosure of Invention
In view of the above, it is necessary to provide a display panel and a display device that improve the above problem, in order to solve the problem that the display effect of the display panel is affected by the difference in the density of the circuit blocks of the demultiplexing circuit.
According to an aspect of the present application, there is provided a display panel including:
a substrate having a display area and a non-display area surrounding the display area;
a demultiplexing circuit formed in the non-display region of the substrate, the demultiplexing circuit including a plurality of groups of thin film transistor units arranged at intervals in a first direction, each group of the thin film transistor units including at least one thin film transistor formed of polycrystalline silicon; and
a plurality of groups of dummy cells formed in the non-display area of the substrate, each group of the dummy cells including at least one dummy semiconductor monomer formed of polysilicon;
wherein any one group of the dummy cells is located between two groups of the thin film transistor cells adjacently arranged in the first direction; the distance between any group of thin film transistor units and the other group of thin film transistor units which are most adjacent to the thin film transistor units is smaller than a preset distance, or the distance between any group of thin film transistor units and the dummy units which are most adjacent to the thin film transistor units is smaller than the preset distance.
In one embodiment, the non-display area comprises a first non-display area and a second non-display area which are adjacently arranged, a first distance is reserved between two adjacent groups of thin film transistor units in the first non-display area, and a second distance is reserved between two adjacent groups of thin film transistor units in the second non-display area; the first distance is greater than the second distance;
the dummy unit is located in the first non-display area.
Therefore, the circuit modules in the non-display area are more uniformly arranged, the phenomenon of strip bright stripes is further reduced, and the display effect of the display panel is further improved.
In one embodiment, the distance between the dummy cell and the thin film transistor cell adjacent to the dummy cell is equal to the second distance.
Therefore, the circuit modules in the non-display area are more uniformly arranged, the phenomenon of strip bright stripes is further reduced, and the display effect of the display panel is further improved.
In one embodiment, the display area includes a first display area and a second display area which are adjacently arranged, the first non-display area is adjacent to and correspondingly arranged with the first display area, and the second non-display area is adjacent to and correspondingly arranged with the second display area.
Thus, the dummy unit can further reduce the area of the second display region, and the generation of band-shaped bright lines due to the small area is avoided.
In one embodiment, the length of each group of the thin film transistor units in the second direction is the same as the length of each group of the dummy units in the second direction, and the thin film transistor units and the dummy units are flush in the second direction;
wherein the second direction is perpendicular to the first direction.
In this way, the dummy unit and the thin film transistor unit are as close to each other as possible in shape, so that the uniformity requirement of the circuit module is met.
In one embodiment, the thin film transistor comprises a transistor polycrystalline silicon layer, wherein a first contact hole is formed in the transistor polycrystalline silicon layer; the dummy semiconductor single body is provided with a second contact hole.
In this way, the dummy cells have a similar configuration to the thin film transistors, thereby improving the arrangement uniformity of the circuit module.
In one embodiment, the transistor polysilicon layer and the dummy semiconductor monomer are formed at the same time on the substrate.
Therefore, the dummy unit can be formed at the same time of manufacturing the transistor polycrystalline silicon layer, so that a new processing step is not needed to be added for arranging the dummy unit, the display effect is improved, and the influence on the processing efficiency is reduced.
In one embodiment, the first contact hole and the second contact hole are formed in the transistor polysilicon layer or the dummy semiconductor single body at the same time.
Therefore, the second contact hole can be formed while the first contact hole is formed, so that a new processing step is not required to be added for opening the second contact hole, the display effect is improved, and the influence on the processing efficiency is reduced.
In one embodiment, the shape of the first contact hole is the same as the shape of the second contact hole, and a distance between two adjacent first contact holes in the second direction is equal to a distance between two adjacent second contact holes in the second direction.
In this way, the dummy cell and the thin film transistor cell are configured as close as possible to meet the uniformity requirements of the circuit module.
According to another aspect of the present application, there is provided a display device including the display panel described above.
Above-mentioned display panel and display device, through be equipped with between two adjacent great thin film transistor units apart from the great thin film transistor unit by for example the clearance between two adjacent thin film transistor units has been filled to the fictitious unit that is formed of polycrystalline silicon, thereby the area of the blank area between two adjacent thin film transistor units has been reduced, the homogeneity of arranging of the circuit module in non-display area has effectively been improved, effectively eliminate because of the different TFT characteristic differences that produce the edge effect and bring of the density of arranging of thin film transistor unit, and then alleviateed the phenomenon of banding bright line, display panel's display effect has effectively been promoted.
Drawings
Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the invention;
fig. 2 is a schematic diagram of a demultiplexing circuit of the display panel shown in fig. 1.
Description of reference numerals:
100. a display panel; 21. a display area; 212. a first display area; 214. a second display area; 23. a non-display area; 232. a first non-display area; 234. a second non-display area; 40. a demultiplexing circuit; 41. a thin film transistor unit; 4121. a transistor polysilicon layer; 4121a, a first contact hole; 4123. a source electrode; 4125. a drain electrode; 4127. a gate electrode; 43. a connecting wire; 60. a dummy cell; 61. a dummy semiconductor monomer; 612. and a second contact hole.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.
In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the invention and to simplify the description, and are not intended to indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and are not to be considered limiting of the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to implicitly indicate the number of technical features indicated.
In the present invention, the terms "mounted," "connected," "secured," and the like are to be construed broadly unless otherwise specifically indicated and limited. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
With the rapid development of the OLED display panel technology, the width of the non-display area of the display panel is narrower and narrower, so that the visible area of the display device provided with the display panel is increased, a more excellent visual effect is achieved, the use experience of a user is improved, and the development trend of the current electronic equipment is high.
As shown in fig. 1, a display device in at least one embodiment of the disclosure includes a display panel 100 for displaying an image, where the display panel 100 includes a substrate, and a driving layer group, a display layer group, and a package structure stacked on the substrate.
The substrate may be a rigid substrate made of a rigid material such as glass, or may be a flexible substrate made of a polymer flexible material such as Polyethylene Terephthalate (PET), Polyethylene Naphthalate (PEN), Polycarbonate (PC), Polyether Sulfone (PES), or a composite Film (FRP). It will be appreciated that the material forming the substrate is not limited thereto, and in other embodiments may be formed using other materials as desired.
With continued reference to fig. 1, the substrate includes a display area 21 and a non-display area 23 surrounding the display area 21.
The display area 21 includes a first display area 212 and a second display area 214, the first display area 212 may be a straight display area, and the second display area 214 may be an arc display area. Specifically, the first display area 212 is substantially rectangular, a width direction of the first display area 212 extends along a first direction (i.e., an X-axis direction in fig. 1 and 2), and a length direction of the first display area 212 extends along a second direction (i.e., a Y-axis direction in fig. 1 and 2). The two second display areas 214 are respectively located on two opposite sides of the first display area 212 in the first direction, each second display area 214 extends from one end of the first display area 212 to the other end of the first display area 212 along the second direction, and edges of two ends of each second display area 214 in the second direction are arc-shaped and tangent to an edge of the first display area 212 extending along the first direction.
The non-display area 23 is circumferentially located outside the display area 21, and the non-display area 23 located on the second direction side of the display area 21 includes one first non-display area 232 and two second non-display areas 234. The first non-display area 232 extends along the first direction, is adjacent to the first display area 212 and is disposed correspondingly in the second direction, the two second non-display areas 234 are respectively located at two opposite sides of the first non-display area 232 in the first direction, are adjacent to the two second display areas 214 and are disposed correspondingly in the second direction, and an edge of one side of the second non-display area 234 away from the second display area 214 is in a circular arc shape tangential to an edge of the second non-display area 234 extending along the first direction.
As shown in fig. 1 and 2, the driving layer group includes pixel circuits, and the pixel circuits are formed in a display region 21 of the substrate and control an operation state of each pixel in the display layer group.
Typically, each pixel in a group of display layers includes three sub-pixels (e.g., R, G, B), each controlled by a scan line (gate line) and a data line (source line). Therefore, one display panel 100 needs to be provided with a plurality of scan lines and data lines.
However, the display panel 100 is limited by space, and therefore, generally, only a small number of driver chips can be disposed in the display panel 100. On the other hand, as the resolution of the display panel 100 is improved, the number of sub-pixels included in the display panel 100 is increased. Therefore, when the space is limited, the demultiplexing circuit 40 is usually used to connect the driver chip and the pixels to reduce the number of output pins of the driver chip.
In the embodiment of the present application, the demultiplexing circuit 40 is formed in the non-display area 23 of the substrate. The demultiplexing circuit 40 includes a plurality of connection lines 43 and a plurality of sets of thin film transistor units 41, the connection lines 43 are used for connecting the thin film transistor units 41 with a driving chip, and the driving chip controls the operation of the demultiplexing circuit 40 through the connection lines 43. The plurality of sets of thin film transistor units 41 are arranged at intervals along the first direction, and each set of thin film transistor units 41 includes at least one thin film transistor.
In the research of the inventor of the present application, as the width of the non-display area 23 becomes narrower, the length of the second non-display area 234 in the first direction and the second direction becomes significantly shorter, so that the arrangement space of the second non-display area 234 is smaller than that of the first non-display area 232, and further the arrangement of the thin film transistor units 41 in the second non-display area 234 becomes denser, and therefore the arrangement density of the thin film transistor units 41 in the second non-display area 234 is greater than that of the thin film transistors in the first non-display area 232, and therefore the arrangement uniformity of the circuit modules in the non-display area 23 is lower.
Since the TFT characteristics of the TFT units 41 have a relatively large correlation with the arrangement density, the arrangement density of the TFT units 41 in the second non-display area 234 is greater than the arrangement density of the TFT units 41 in the first non-display area 232, which causes the TFT characteristics of the TFT units 41 in the first non-display area 232 and the second non-display area 234 to be different, and further causes the display panel 100 to have vertical stripe-shaped bright stripes, thereby affecting the display effect of the display panel 100.
In order to solve the above problem, as shown in fig. 2, the display panel 100 of the present application further includes a plurality of groups of dummy cells 60, the plurality of groups of dummy cells 60 are formed in the non-display region 23 of the substrate, each group of dummy cells 60 includes at least one dummy semiconductor unit 61, any group of dummy cells 60 is located between two adjacent groups of thin film transistor cells 41, a distance between any group of thin film transistor cells 41 and another group of thin film transistor cells 41 that are most adjacent thereto is smaller than a preset distance, or a distance between any group of thin film transistor cells 41 and the dummy cell 60 that is most adjacent thereto is smaller than the preset distance.
Thus, the dummy unit 60 formed by, for example, polysilicon is arranged between two adjacent groups of thin film transistor units 41 with a large distance to fill the gap between two adjacent thin film transistor units 41, thereby reducing the area of the blank area between two adjacent thin film transistor units 41, effectively improving the arrangement uniformity of the circuit module of the non-display area 23, effectively eliminating the TFT characteristic difference caused by the edge effect generated by the different arrangement densities of the thin film transistor units 41, further reducing the phenomenon of the band-shaped bright stripes, and effectively improving the display effect of the display panel 100.
Specifically, a first distance exists between two adjacent groups of thin film transistor units 41 located in the first non-display area 232, a second distance smaller than the first distance exists between two adjacent groups of thin film transistor units 41 located in the second non-display area 234, the dummy unit 60 is located in the first non-display area 232, and the distance between the dummy unit 60 and the thin film transistor unit 41 adjacent to the dummy unit is equal to the second distance, so that the circuit modules in the non-display area 23 are more uniformly arranged, the phenomenon of banding bright streaks is further reduced, and the display effect of the display panel 100 is further improved.
In some embodiments, the width of each group of dummy cells 60 in the first direction satisfies the distance requirement between the dummy cells and the thin film transistor cells 41, the length of each group of thin film transistor cells 41 in the second direction is the same as the length of each group of dummy cells 60 in the second direction, and the thin film transistor cells 41 are flush with the dummy cells 60 in the second direction, thereby satisfying the uniformity requirement of the circuit module.
Specifically, in one embodiment, each group of the tft units 41 includes two groups of tfts spaced apart in the second direction, and each group of the tfts includes two tfts spaced apart in the first direction. Each group of dummy cells 60 includes two dummy semiconductor monomers 61, the two dummy semiconductor monomers are arranged at intervals in the second direction, and each dummy semiconductor monomer 61 is located between two thin film transistors. Each dummy semiconductor unit 61 is rectangular, the length direction of the dummy semiconductor unit 61 extends along the second direction, the width direction of the dummy semiconductor unit 61 extends along the first direction, and the length of each dummy semiconductor unit 61 in the second direction is the same as the length of the adjacent thin film transistor in the first direction.
It is to be understood that the shape and arrangement of the dummy semiconductor single bodies 61 are not limited thereto, and the shape and arrangement of the dummy semiconductor single bodies 61 may be set according to the shape and arrangement of the thin film transistors, and the dummy semiconductor single bodies 61 may also be set in other regular or irregular shapes.
With continued reference to fig. 2, in some embodiments, the tft includes a transistor polysilicon layer 4121, the transistor polysilicon layer 4121 defines a plurality of first contact holes 4121a, and the gate 4127, the source 4123 and the drain 4125 are sequentially formed on the transistor polysilicon layer 4121. The gate electrode 4127 receives a scan signal from the gate line, and drives the transistor polysilicon layer 4121. Specifically, when an on signal is applied to the gate line, induced charges are generated on the surface of the polysilicon layer 4121 of the transistor under the action of the gate 4127, a low resistance channel is formed accordingly, a large current is turned on, and the source 4123 and the drain 4125 are turned on, so that data can be transmitted therebetween. The dummy semiconductor single body 61 is opened with a plurality of second contact holes 612.
In this way, the dummy semiconductor unit 61 and the thin film transistor are formed of polysilicon material and have similar configurations, thereby improving the arrangement uniformity of the circuit modules.
Specifically, in some embodiments, the transistor polysilicon layer 4121 and the dummy semiconductor single body 61 are simultaneously formed on the substrate through the same process, and the first contact hole 4121a and the second contact hole 612 are simultaneously formed on the transistor polysilicon layer 4121 and the dummy semiconductor single body 61 through the same process, respectively.
Preferably, the shape of the first contact hole 4121a is the same as that of the second contact hole 612, and a distance between two adjacent first contact holes 4121a in the second direction is equal to a distance between two adjacent second contact holes 612 in the second direction.
In this manner, the dummy semiconductor single body 61 can be formed at the same time as the transistor polysilicon layer 4121 is formed, so that it is not necessary to add a new process step for the arrangement of the dummy cell 60, and the influence on the process efficiency is reduced while the display effect is improved.
Specifically, in some embodiments, an amorphous silicon thin film may be formed on a substrate by using a PECVD (Plasma Enhanced Chemical Vapor Deposition) or other Deposition method, the transistor polysilicon layer 4121 and the dummy semiconductor monomer 61 are formed by crystallizing the amorphous silicon thin film through a Rapid Thermal Annealing (RTA) method, a Solid Phase Crystallization (SPC) method, an Excimer Laser Annealing (ELA) method, a Metal Induced Crystallization (MIC) method, a Metal Induced Lateral Crystallization (MILC) method, a Sequential Lateral Solidification (SLS) method, etc., a photoresist is coated on the transistor polysilicon layer 4121 and the dummy semiconductor monomer 61, the photoresist is exposed and developed by using a mask, and the transistor polysilicon layer 4121 and the dummy semiconductor monomer 61 are etched to form the first contact hole 4121a or the second contact hole 612. It is to be understood that the methods for forming the transistor polysilicon layer 4121 and the dummy semiconductor single bodies 61, and the first contact hole 4121a and the second contact hole 612 are not limited, and may be configured as required to meet different requirements.
In the display panel 100 and the display device, the dummy unit 60 is arranged in the first non-display area 232 with the low distribution density of the thin film transistor units 41, so that the density of the circuit modules in the first non-display area 232 is effectively improved, the difference of the TFT characteristics of the thin film transistor units 41 is improved, the uniformity and the stability of the TFT characteristics are improved, the generation of the band-shaped bright stripes is effectively reduced, and the display effect of the display panel 100 is improved. On the basis of the present application, the area of the non-display region 23 can be further reduced without causing bright stripes due to uneven arrangement of the circuit modules.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent should be subject to the appended claims.
Claims (10)
1. A display panel, comprising:
a substrate having a display area and a non-display area surrounding the display area;
a demultiplexing circuit formed in the non-display region of the substrate, the demultiplexing circuit including a plurality of groups of thin film transistor units arranged at intervals along a first direction, each group of the thin film transistor units including at least one thin film transistor; and
a plurality of groups of dummy cells formed in the non-display area of the substrate, each group of the dummy cells including at least one dummy semiconductor monomer;
wherein any one group of the dummy cells is located between two groups of the thin film transistor cells adjacently arranged in the first direction; the distance between any group of thin film transistor units and the other group of thin film transistor units which are most adjacent to the thin film transistor units is smaller than a preset distance, or the distance between any group of thin film transistor units and the dummy units which are most adjacent to the thin film transistor units is smaller than the preset distance.
2. The display panel according to claim 1, wherein the non-display region comprises a first non-display region and a second non-display region which are adjacently arranged, a first distance is provided between two adjacent groups of the thin film transistor units in the first non-display region, and a second distance is provided between two adjacent groups of the thin film transistor units in the second non-display region; the first distance is greater than the second distance;
the dummy unit is located in the first non-display area.
3. The display panel according to claim 2, wherein a distance between the dummy cell and the thin film transistor cell adjacent thereto is equal to the second distance.
4. The display panel according to claim 2, wherein the display region comprises a first display region and a second display region which are adjacently disposed, the first non-display region is adjacent to and correspondingly disposed with the first display region, and the second non-display region is adjacent to and correspondingly disposed with the second display region.
5. The display panel according to claim 1, wherein the length of each group of the thin film transistor cells in the second direction is the same as the length of each group of the dummy cells in the second direction, and the thin film transistor cells are flush with the dummy cells in the second direction;
wherein the second direction is perpendicular to the first direction.
6. The display panel according to any one of claims 1 to 5, wherein the thin film transistor comprises a transistor polysilicon layer, and the transistor polysilicon layer is provided with a first contact hole; the dummy semiconductor single body is provided with a second contact hole.
7. The display panel of claim 6, wherein the transistor polysilicon layer and the dummy semiconductor monomer are formed on the substrate at the same time.
8. The display panel according to claim 6, wherein the first contact hole and the second contact hole are formed at the same time in the transistor polysilicon layer or the dummy semiconductor single body.
9. The display panel according to claim 8, wherein the first contact holes have the same shape as the second contact holes, and a distance between two adjacent first contact holes in the second direction is equal to a distance between two adjacent second contact holes in the second direction;
wherein the second direction is perpendicular to the first direction.
10. A display device characterized by comprising the display panel according to any one of claims 1 to 9.
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| CN202011129744.5A CN112259586B (en) | 2020-10-21 | 2020-10-21 | Display panel and display device |
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| CN202011129744.5A CN112259586B (en) | 2020-10-21 | 2020-10-21 | Display panel and display device |
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