CN112259150A - EEPROM memory programming precision correction circuit and method - Google Patents
EEPROM memory programming precision correction circuit and method Download PDFInfo
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- CN112259150A CN112259150A CN202011125677.XA CN202011125677A CN112259150A CN 112259150 A CN112259150 A CN 112259150A CN 202011125677 A CN202011125677 A CN 202011125677A CN 112259150 A CN112259150 A CN 112259150A
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- 238000000034 method Methods 0.000 title claims abstract description 19
- 238000012937 correction Methods 0.000 title claims description 14
- 238000012360 testing method Methods 0.000 claims abstract description 34
- 230000008439 repair process Effects 0.000 claims abstract description 7
- 239000013078 crystal Substances 0.000 claims description 6
- 238000012545 processing Methods 0.000 claims description 4
- 230000005540 biological transmission Effects 0.000 claims description 3
- 238000009966 trimming Methods 0.000 description 10
- 238000005070 sampling Methods 0.000 description 5
- 238000007667 floating Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000013479 data entry Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000007664 blowing Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
- G11C16/3413—Circuits or methods to recover overprogrammed nonvolatile memory cells detected during program verification, usually by means of a "soft" erasing step
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/20—Initialising; Data preset; Chip identification
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/148—Details of power up or power down circuits, standby circuits or recovery circuits
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- For Increasing The Reliability Of Semiconductor Memories (AREA)
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Abstract
The invention discloses a circuit and a method for correcting programming precision of an EEPROM (electrically erasable programmable read-Only memory), comprising the following steps of: the single-polycrystal EEPROM comprises a single-polycrystal EEPROM sub-circuit, a reset sub-circuit, an operation instruction control sub-circuit, a signal input sub-circuit and a charge pump; the reset sub-circuit is used for detecting whether the EEPROM is in a chip test mode or not; when in the test mode, the reset sub-circuit reset signal is valid; the reset sub-circuit generates a reset signal to the single-polycrystal EEPROM sub-circuit, the operation instruction control sub-circuit, the signal input sub-circuit and the charge pump, and the single-polycrystal EEPROM sub-circuit, the operation instruction control sub-circuit, the signal input sub-circuit and the charge pump enter an initialization state and do not act; if no reset signal comes, when the test enable signal is at high level, the operation control command is generated by inputting different numbers of square waves to the CS chip selection end of the operation command control sub-circuit. The invention tests and repairs the EEPROM through the combination of pin multiplexing and single-polycrystal EEPROM, has low cost and can flexibly and accurately regulate the reference source voltage.
Description
Technical Field
The invention relates to the technical field of memory precision correction, in particular to a circuit and a method for correcting programming precision of an EEPROM (electrically erasable programmable read-Only memory).
Background
Electrically erasable programmable memory (EEPROM) is one of the most widely used memory devices today. It can rewrite content at any time like RAM, and can store information for a long time like other ROM, so that it can be extensively used in microcomputer, microcontroller circuit and gold card (IC card) engineering. In the design and manufacture of integrated circuits, due to design processes, packaging and the like, the practical manufacture is different from the theoretical manufacture, along with the improvement of the integration level of the integrated circuits, the high precision requirement of the integrated circuits is increasingly obvious, and precision correction is a necessary means for realizing the high-precision integrated circuits.
The traditional EEPROM precision correction method comprises the technologies of laser trimming of a resistance film, fuse blowing trimming, diode short circuit trimming and the like. But the laser trimming cost is high and the process is complex; the fuse wire is blown, the trimming error is large, and the yield is low; the diode trimming technology occupies a large chip area and is unidirectional trimming. Therefore, the invention of a correction circuit for the programming accuracy of an EEPROM memory with high reliability and high correction accuracy is a problem to be solved urgently by those skilled in the art.
Disclosure of Invention
The present invention is directed to a circuit for correcting programming accuracy of an EEPROM.
In a first aspect, the invention discloses a circuit for correcting programming precision of an EEPROM (electrically erasable programmable read-only memory), which comprises a single-polycrystal EEPROM sub-circuit, a reset sub-circuit, an operation instruction control sub-circuit, a signal input sub-circuit and a charge pump; the reset sub-circuit is electrically connected with the single-polycrystal EEPROM sub-circuit, the operation instruction control sub-circuit, the signal input sub-circuit and the charge pump respectively; the single-polycrystal EEPROM sub-circuit is electrically connected with the signal input sub-circuit, the signal input sub-circuit is electrically connected with the operation instruction control sub-circuit, the operation instruction control sub-circuit is electrically connected with the charge pump, and the charge pump is electrically connected with the single-polycrystal EEPROM sub-circuit; the operation instruction control sub-circuit is electrically connected with the single-polycrystal EEPROM sub-circuit; the reset sub-circuit is used for detecting whether the EEPROM is in a chip test mode or not; when in the test mode, the reset sub-circuit reset signal is effective; the reset sub-circuit generates a reset signal to the single-polycrystal EEPROM sub-circuit, the operation instruction control sub-circuit, the signal input sub-circuit and the charge pump, and the single-polycrystal EEPROM sub-circuit, the operation instruction control sub-circuit, the signal input sub-circuit and the charge pump enter an initialization state; do not act; if no reset signal comes, when the test enable signal is at a high level, the operation control command is generated by inputting different numbers of square waves to the CS chip selection end of the operation command control sub-circuit.
Preferably, the operation instruction control sub-circuit generates different operation control instructions through 38 decoding circuit.
Preferably, the signal input sub-circuit performs data transmission and clock control through pin multiplexing of one data line.
In a second aspect, the invention discloses a method for correcting programming accuracy of an EEPROM memory, the method comprising:
judging whether the circuit is in a test mode or not through the signal input sub-circuit;
if the single-polycrystal EEPROM is in the test mode, the reset sub-circuit generates a reset signal to the single-polycrystal EEPROM sub-circuit, the operation instruction control sub-circuit, the signal input sub-circuit and the charge pump;
controlling the single-polycrystal EEPROM sub-circuit, the operation instruction control sub-circuit, the signal input sub-circuit and the charge pump to enter an initialization state according to the reset signal;
if no reset signal comes, when the test enable signal is at high level, different numbers of square waves are input to the CS chip selection end of the signal input sub-circuit to generate an operation control instruction.
Preferably, if no reset signal arrives, when the test enable signal is at a high level, the generating the operation control command by inputting different numbers of square waves to the CS chip select terminal of the signal input sub-circuit includes:
controlling a first square wave to generate a read operation command, and reading data in the single-crystal and multi-crystal EEPROM sub-circuit;
controlling a second square wave to generate an erasing operation command, wherein the charge pump generates voltage to control the single-polycrystal EEPROM sub-circuit to erase data;
controlling a third square wave to generate a data input command, and performing data serial shift processing through pin multiplexing of the signal input sub-circuit;
and controlling a fourth square wave to generate a write operation command, wherein the operation command controls a sub-circuit to generate the write command, and the voltage generated by the charge pump is input into the single-polycrystal EEPROM sub-circuit so as to realize the adjustment and repair of the reference voltage in the single-polycrystal EEPROM sub-circuit.
The invention discloses a circuit and a method for correcting programming precision of an EEPROM (electrically erasable programmable read-Only memory), which have the following beneficial effects that: the single-polycrystal EEPROM comprises a single-polycrystal EEPROM sub-circuit, a reset sub-circuit, an operation instruction control sub-circuit, a signal input sub-circuit and a charge pump; the reset sub-circuit is used for detecting whether the EEPROM is in a chip test mode or not; when in the test mode, the reset sub-circuit reset signal is valid; the reset sub-circuit generates a reset signal to the single-polycrystal EEPROM sub-circuit, the operation instruction control sub-circuit, the signal input sub-circuit and the charge pump, and the single-polycrystal EEPROM sub-circuit, the operation instruction control sub-circuit, the signal input sub-circuit and the charge pump enter an initialization state and do not act; if no reset signal comes, when the test enable signal is at high level, the operation control command is generated by inputting different numbers of square waves to the CS chip selection end of the operation command control sub-circuit. Therefore, the invention tests and repairs the EEPROM memory by combining pin multiplexing and single-polycrystal EEPROM, and has low cost, low power consumption and high cost performance; meanwhile, the reference source voltage can be flexibly and accurately adjusted, and the trimming precision and the correction precision of the EEPROM are effectively improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the present invention will be further described with reference to the accompanying drawings and embodiments, wherein the drawings in the following description are only part of the embodiments of the present invention, and for those skilled in the art, other drawings can be obtained without inventive efforts according to the accompanying drawings:
FIG. 1 is a schematic circuit diagram of an EEPROM programming accuracy correction circuit according to a preferred embodiment of the present invention;
FIG. 2 is a circuit diagram of a single-poly EEPROM sub-circuit of the EEPROM programming accuracy correction circuit in accordance with the preferred embodiment of the present invention;
FIG. 3 is a flow chart of a method for correcting the programming accuracy of an EEPROM memory according to a preferred embodiment of the invention;
FIG. 4 is a flowchart illustrating a method for correcting the programming accuracy of an EEPROM according to another preferred embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present invention, and it is obvious that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without inventive step, are within the scope of the present invention.
Referring to fig. 1, a preferred embodiment of the present invention discloses a circuit for correcting programming accuracy of an EEPROM, which comprises a single-poly EEPROM sub-circuit 1, a reset sub-circuit 2, an operation command control sub-circuit 3, a signal input sub-circuit 4, and a charge pump 5; the reset sub-circuit 2 is electrically connected with the single-polycrystal EEPROM sub-circuit 1, the operation instruction control sub-circuit 3, the signal input sub-circuit 4 and the charge pump 5 respectively; the single-polycrystal EEPROM sub-circuit 1 is electrically connected with the signal input sub-circuit 4, the signal input sub-circuit 4 is electrically connected with the operation instruction control sub-circuit 3, the operation instruction control sub-circuit 3 is electrically connected with the charge pump 5, and the charge pump 5 is electrically connected with the single-polycrystal EEPROM sub-circuit 1; the operation instruction control sub-circuit 3 is electrically connected with the single-polycrystal EEPROM sub-circuit 1; the reset sub-circuit 2 is used for detecting whether the EEPROM is in a chip test mode; when in the test mode, the reset sub-circuit 2 resets the signal to be valid; the reset sub-circuit 2 generates a reset signal to the single-polycrystal EEPROM sub-circuit 1, the operation instruction control sub-circuit 3, the signal input sub-circuit 4 and the charge pump 5, and the single-polycrystal EEPROM sub-circuit 1, the operation instruction control sub-circuit 3, the signal input sub-circuit 4 and the charge pump 5 enter an initialization state; do not act; if no reset signal comes, when the test enable signal is at a high level, the CS chip selection terminal of the operation instruction control sub-circuit 3 is input with different numbers of square waves to generate an operation control instruction. Therefore, the invention tests and repairs the EEPROM memory by combining pin multiplexing and single-polycrystal EEPROM, and has low cost, low power consumption and high cost performance; meanwhile, the reference source voltage can be flexibly and accurately adjusted, and the trimming precision and the correction precision of the EEPROM are effectively improved.
Preferably, the operation instruction control sub-circuit 3 generates different operation control instructions through a 38-decoding circuit. For example, when the CS chip select terminal arrives at the sixth square wave, the erase operation command is generated.
Preferably, the signal input sub-circuit 4 performs data transmission and clock control through pin multiplexing of one data line. Therefore, the pin function is expanded, and the cost is saved, so that the invention has high cost performance.
Referring to fig. 3, the present invention discloses a method for correcting programming accuracy of an EEPROM, comprising:
s1, judging whether the circuit is in a test mode or not through the signal input sub-circuit 4;
s2, if in the test mode, the reset sub-circuit 2 generates a reset signal to the single-poly EEPROM sub-circuit 1, the operation instruction control sub-circuit 3, the signal input sub-circuit 4, and the charge pump 5;
s3, controlling the single-polycrystal EEPROM sub-circuit 1, the operation instruction control sub-circuit 3, the signal input sub-circuit 4 and the charge pump 5 to enter an initialization state according to the reset signal;
s4, if no reset signal arrives, when the test enable signal is at high level, the CS chip select terminal of the signal input sub-circuit 4 is input with different numbers of square waves to generate the operation control command.
Preferably, referring to fig. 4, if no reset signal arrives, when the test enable signal is at a high level, the generating the operation control command by inputting different numbers of square waves to the CS chip selection terminal of the signal input sub-circuit 4 includes:
s41, controlling the first square wave to generate a read operation command, and reading data in the single-crystal EEPROM sub-circuit 1;
s42, controlling a second square wave to generate an erasing operation command, and generating a voltage by the charge pump 5 to control the single-polycrystal EEPROM sub-circuit 1 to erase data;
s43, controlling a third square wave to generate a data input command, and performing data serial shift processing through pin multiplexing of the signal input sub-circuit 4;
and S44, controlling a fourth square wave to generate a write operation command, wherein the operation command controls the sub-circuit 3 to generate the write command, and the voltage generated by the charge pump 5 is input into the single-polycrystal EEPROM sub-circuit 1 to realize the adjustment and repair of the reference voltage in the single-polycrystal EEPROM sub-circuit 1.
Specifically, in the present embodiment, the data serial shift processing is performed by the pin multiplexing of the signal input sub-circuit 4 to realize the data write operation instruction. The specific data input process is as follows: to create a write gap, the host must pull the data line low and then release to begin inputting data. The data input period is at least 60 mu s and at most 120 mu s. At the beginning of a data entry cycle, the host first pulls the bus low by 1 μ s to indicate the beginning of the data entry cycle. If the host wants to input 0, the host continues to pull down the level for at least 60 mu s until the data input period is finished, and then releases the bus to be the high level; if the host wants to enter 1, the bus is released to high after the bus level is initially pulled down for 1 μ s until the end of the data input cycle. And the signal input sub-circuit as the slave waits for 15 mus after detecting that the bus is pulled down, then samples the bus from 15 mus to 45 mus, and is 1 if the bus is high level in the sampling period, and is 0 if the bus is low level in the sampling period. After sampling, the sampled data needs to be written into the single-poly EEPROM sub-circuit.
Referring to fig. 2, when the operation command control sub-circuit 3 generates a write operation command, in fig. 2, VD is 16V, and VCG is 0; i1 is connected with high voltage 11.4V, and N type IGFET N1 and N type IGFET N2 are opened; i3 is connected with high voltage about 15V, and P-type IGFET P1 is conducted; i2 is connected to high level, about 6.2V, and N-type IGFET N3 is conducted; and whether N-type IGFET N4 is on or off depends on data terminal D. If the bus is at high level in the sampling period of the signal input sub-circuit 4, the bus is 1, that is, when D is 1, the N-type IGFET N4 is turned off, which is equivalent to the S-terminal of the N-type IGFET N3 is floating, almost all D, S, B of the P-type IGFET P2 is 16V, and at this time, the N-type IGFET N6 bears high voltage, causing tunneling, and drawing electrons from VCG onto the floating gate to store charges, and thus, the logic is "1"; if the bus is at low level in the sampling period of the signal input sub-circuit 4, i.e. when D is equal to 0, N-type IGFET N4 is turned on, and the single-poly EEPROM sub-circuit has a current path from VD to GND, so that the voltage across D, S of P-type IGFET P2 is pulled low, and the voltage across N-type IGFET N6 is low, and therefore, no tunneling occurs, and electrons cannot be drawn to the floating gate, and the logic is "0". Therefore, the invention flexibly and accurately finishes the adjustment of the reference parameters in the EEPROM, thereby improving the stability of the crystal oscillator output frequency and the working temperature range in the EEPROM and improving the programming precision of the EEPROM.
In summary, the present invention discloses a circuit and a method for correcting programming precision of an EEPROM, wherein the circuit comprises a single-poly EEPROM sub-circuit 1, a reset sub-circuit 2, an operation instruction control sub-circuit 3, a signal input sub-circuit 4 and a charge pump 5; the reset sub-circuit 2 is used for detecting whether the EEPROM is in a chip test mode; when in the test mode, the reset sub-circuit 2 resets the signal to be valid; the reset sub-circuit 2 generates a reset signal to the single-polycrystal EEPROM sub-circuit 1, the operation instruction control sub-circuit 3, the signal input sub-circuit 4 and the charge pump 5, and the single-polycrystal EEPROM sub-circuit 1, the operation instruction control sub-circuit 3, the signal input sub-circuit 4 and the charge pump 5 enter an initialization state and do not act; if no reset signal comes, when the test enable signal is at a high level, the CS chip selection terminal of the signal input sub-circuit 4 is input with different numbers of square waves to generate an operation control command. Therefore, the invention tests and repairs the EEPROM memory by combining pin multiplexing and single-polycrystal EEPROM, and has low cost, low power consumption and high cost performance; meanwhile, the reference source voltage can be flexibly and accurately adjusted, and the trimming precision and the correction precision of the EEPROM are effectively improved.
The present invention provides a circuit and a method for correcting programming accuracy of an EEPROM memory, and the present invention is described in detail above, and the present invention is described in principle and embodiments by applying specific examples, and the description of the above embodiments is only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be a change in the specific implementation and application scope, and in summary, the content of the present specification is only an implementation of the present invention, and not a limitation to the scope of the present invention, and all equivalent structures or equivalent flow transformations made by the content of the present specification and the attached drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention. And should not be construed as limiting the invention.
Claims (5)
1. An EEPROM memory programming accuracy correction circuit, comprising: the single-polycrystal EEPROM comprises a single-polycrystal EEPROM sub-circuit, a reset sub-circuit, an operation instruction control sub-circuit, a signal input sub-circuit and a charge pump; the reset sub-circuit is electrically connected with the single-polycrystal EEPROM sub-circuit, the operation instruction control sub-circuit, the signal input sub-circuit and the charge pump respectively; the single-polycrystal EEPROM sub-circuit is electrically connected with the signal input sub-circuit, the signal input sub-circuit is electrically connected with the operation instruction control sub-circuit, the operation instruction control sub-circuit is electrically connected with the charge pump, and the charge pump is electrically connected with the single-polycrystal EEPROM sub-circuit; the operation instruction control sub-circuit is electrically connected with the single-polycrystal EEPROM sub-circuit; the reset sub-circuit is used for detecting whether the EEPROM is in a chip test mode or not; when in the test mode, the reset sub-circuit reset signal is effective; the reset sub-circuit generates a reset signal to the single-polycrystal EEPROM sub-circuit, the operation instruction control sub-circuit, the signal input sub-circuit and the charge pump, and the single-polycrystal EEPROM sub-circuit, the operation instruction control sub-circuit, the signal input sub-circuit and the charge pump enter an initialization state; do not act; if no reset signal comes, when the test enable signal is at a high level, the operation control command is generated by inputting different numbers of square waves to the CS chip selection end of the operation command control sub-circuit.
2. The EEPROM memory programming accuracy correction circuit of claim 1, wherein the operation instruction control sub-circuit generates different operation control instructions through 38 decoding circuit.
3. The circuit of claim 1, wherein said signal input sub-circuit performs data transmission and clock control through pin multiplexing of a data line.
4. A method for correcting programming accuracy of an EEPROM memory, comprising the circuit for correcting programming accuracy of an EEPROM memory as claimed in any one of claims 1 to 3, the method comprising:
judging whether the circuit is in a test mode or not through the signal input sub-circuit;
if the single-polycrystal EEPROM is in the test mode, the reset sub-circuit generates a reset signal to the single-polycrystal EEPROM sub-circuit, the operation instruction control sub-circuit, the signal input sub-circuit and the charge pump;
controlling the single-polycrystal EEPROM sub-circuit, the operation instruction control sub-circuit, the signal input sub-circuit and the charge pump to enter an initialization state according to the reset signal;
if no reset signal comes, when the test enable signal is at high level, different numbers of square waves are input to the CS chip selection end of the signal input sub-circuit to generate an operation control instruction.
5. The method as claimed in claim 4, wherein the step of generating the operation control command by inputting different numbers of square waves to the CS chip select terminal of the signal input sub-circuit when the test enable signal is at a high level if no reset signal arrives comprises:
controlling a first square wave to generate a read operation command, and reading data in the single-crystal and multi-crystal EEPROM sub-circuit;
controlling a second square wave to generate an erasing operation command, wherein the charge pump generates voltage to control the single-polycrystal EEPROM sub-circuit to erase data;
controlling a third square wave to generate a data input command, and performing data serial shift processing through pin multiplexing of the signal input sub-circuit;
and controlling a fourth square wave to generate a write operation command, wherein the operation command controls a sub-circuit to generate the write command, and the voltage generated by the charge pump is input into the single-polycrystal EEPROM sub-circuit so as to realize the adjustment and repair of the reference voltage in the single-polycrystal EEPROM sub-circuit.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023169420A1 (en) * | 2022-03-09 | 2023-09-14 | 华润微集成电路(无锡)有限公司 | Memory control system and method |
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| CN103117088A (en) * | 2011-10-27 | 2013-05-22 | 爱思开海力士有限公司 | Semiconductor device and method of operating the same |
| CN106297887A (en) * | 2016-07-27 | 2017-01-04 | 深圳市航顺芯片技术研发有限公司 | A kind of booster circuit promoting eeprom memory programming precision and method thereof |
| US20190102261A1 (en) * | 2017-09-29 | 2019-04-04 | Allegro Microsystems, Llc | Circuit and method for storing information in non-volatile memory during a loss of power event |
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2020
- 2020-10-20 CN CN202011125677.XA patent/CN112259150B/en active Active
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1292553A (en) * | 1999-09-24 | 2001-04-25 | 密克罗奇普技术公司 | Method for writing electrically-erasable programmable ROM, equipment and system |
| KR20010070100A (en) * | 1999-09-24 | 2001-07-25 | 씨. 필립 채프맨 | Method, system and apparatus for determining that a programming voltage level is sufficient for reliably programming an EEPROM |
| CN103117088A (en) * | 2011-10-27 | 2013-05-22 | 爱思开海力士有限公司 | Semiconductor device and method of operating the same |
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| US20190102261A1 (en) * | 2017-09-29 | 2019-04-04 | Allegro Microsystems, Llc | Circuit and method for storing information in non-volatile memory during a loss of power event |
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| WO2023169420A1 (en) * | 2022-03-09 | 2023-09-14 | 华润微集成电路(无锡)有限公司 | Memory control system and method |
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