CN112258502A - Method for detecting defects of metal layer in layout - Google Patents

Method for detecting defects of metal layer in layout Download PDF

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CN112258502A
CN112258502A CN202011251741.9A CN202011251741A CN112258502A CN 112258502 A CN112258502 A CN 112258502A CN 202011251741 A CN202011251741 A CN 202011251741A CN 112258502 A CN112258502 A CN 112258502A
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metal layer
layout
density
line segment
detecting
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CN112258502B (en
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朱忠华
魏芳
曹云
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00Image analysis
    • G06T7/0002Inspection of images, e.g. flaw detection
    • G06T7/0004Industrial image inspection
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2207/00Indexing scheme for image analysis or image enhancement
    • G06T2207/30Subject of image; Context of image processing
    • G06T2207/30108Industrial image inspection
    • G06T2207/30148Semiconductor; IC; Wafer

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  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

The invention relates to a method for detecting defects of a metal layer in a layout, which relates to a technology for detecting a layout of a semiconductor integrated circuit, wherein the density analysis of local patterns of the metal layer is added in the conventional layout inspection to obtain the density D of the local patterns of the metal layer, whether hot spots needing layout modification exist or hot spots needing process optimization exist is judged according to the density D of the local patterns of the metal layer, whether the layout needs modification or not is determined, process programs are optimized according to a product inspection result or the layout does not need optimization, and the defects of the metal layer are further effectively avoided.

Description

Method for detecting defects of metal layer in layout
Technical Field
The invention relates to a semiconductor integrated circuit layout detection technology, in particular to a method for detecting defects of a metal layer in a layout.
Background
As the integrated circuit fabrication process nodes continue to advance, manufacturability and reliability checks of integrated circuit designs become increasingly important. The reduction of the size of the process node and the continuous deepening of the complexity of the design graph force the manufacturer to invest huge manpower and financial resources to evaluate the manufacturability of the design layout. The layout data of the designer passes through design rule checking related to graph density after being generated, namely, the layout data of the designer completely passes through the manufacturing specification. But often produce unexpected metal defects after the cmp process. A metal layer is one of the most important levels in the integrated circuit fabrication level. Once the generated defects are shown in the schematic diagram of the metal layer polishing defects caused by the non-uniform pattern density shown in fig. 1, the reliability of the designed circuit is reduced if the defects are light, and the designed circuit is short-circuited if the defects are heavy, which seriously affects the product yield. These defective design patterns themselves are fully compliant with the design rules, but due to the differences in the process capabilities of the manufacturers, two types of situations arise: some patterns can be completely solved by adjusting the parameters of the machine through a customized method, and other patterns must be solved together through the help of a manufacturer.
Disclosure of Invention
The invention provides a method for detecting defects of a metal layer in a layout, which comprises the following steps: s1: the designer completes the layout design; s2: performing conventional inspection on the layout by adopting a layout design rule formulated by a manufacturer; s3: judging whether the layout design rule check passes, if so, entering a step S4, and if not, entering a step S1; s4: analyzing the density of the local graph of the metal layer to obtain the density D of the local graph of the metal layer, comprising the following steps: s41: searching regions of which the thickness directions of n continuous metal layers in the metal layer region are all oxides, and obtaining a specific oxide region of which the top layer area of the oxide region is larger than S, wherein n is a natural number larger than or equal to 2; s42: selecting at least one line segment of the specific oxide area, extending two ends of the line segment to obtain an extended line segment, translating the extended line segment to the side far away from the specific oxide area by W to obtain a translated line segment, and forming a density graph area to be measured by the extended line segment and the translated line segment; and S43: obtaining the metal density D of the pattern area to be measured to obtain the local pattern density D of the metal layer; s5: judging whether a hot spot needing layout changing exists according to the density D of the local graph of the metal layer, if so, entering a step S1, otherwise, entering a step S6; s6: judging whether a hot spot needing to optimize the process exists according to the local graph density D of the metal layer, if so, entering step S7, otherwise, entering step S8; s7: optimizing the process according to the product inspection result; and S8: and the layout check is passed.
Furthermore, the value of n is any value between 2 and 8.
Furthermore, S is larger than 2um2
Further, the two ends of at least one line segment of the specific oxide region extend for equal distances.
Further, the length of a line segment obtained by extending both ends of at least one line segment of the specific oxide region is equal to W.
Furthermore, the value of W is any value between 5um and 1000 um.
Furthermore, in step S5, it is determined whether D is higher than M, and when D is higher than M, a hot spot requiring layout change exists in the layout.
Further, S1 includes adding a redundant pattern in a specific oxide region or reducing the density of the pattern region to be measured and the inter-metal pattern.
Furthermore, the value of D is any value between 50% and 100%.
Further, S6 is a step of determining whether D is higher than E but lower than M, and if so, there is a hot spot that requires process optimization.
Drawings
FIG. 1 is a schematic diagram of metal layer polishing defects caused by non-uniform pattern density.
FIG. 2 is a flow chart of a local pattern density analysis of a metal layer according to an embodiment of the present invention.
Fig. 3 is a schematic diagram of a metal layer region in a layout according to an embodiment of the invention.
Fig. 4 is a schematic cross-sectional view of a region where the thickness regions corresponding to the multiple continuous metal layers in the layout are all oxide according to an embodiment of the present invention.
Fig. 5 is a schematic diagram of an expanded region for analyzing the local pattern density of the metal layer in the layout according to an embodiment of the present invention.
Detailed Description
The technical solutions in the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity, and the same reference numerals denote the same elements throughout. It will be understood that when an element or layer is referred to as being "on" …, "adjacent to …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on …," "directly adjacent to …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relationship terms such as "under …", "under …", "below", "under …", "above …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below …" and "below …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In an embodiment of the present invention, a method for detecting defects of a metal layer in a layout is provided, including: s1: the designer completes the layout design; s2: performing conventional inspection on the layout by adopting a layout design rule formulated by a manufacturer; s3: judging whether the layout design rule check passes, if so, entering a step S4, and if not, entering a step S1; s4: analyzing the density of the local graph of the metal layer to obtain the density D of the local graph of the metal layer, comprising the following steps: s41: searching regions of which the thickness directions of n continuous metal layers in the metal layer region are all oxides, and obtaining a specific oxide region of which the top layer area of the oxide region is larger than S, wherein n is a natural number larger than or equal to 2; s42: selecting at least one line segment of the specific oxide area, extending two ends of the line segment to obtain an extended line segment, translating the extended line segment to the side far away from the specific oxide area by W to obtain a translated line segment, and forming a density graph area to be measured by the extended line segment and the translated line segment; and S43: obtaining the metal density D of the pattern area to be measured to obtain the local pattern density D of the metal layer; s5: judging whether a hot spot needing layout changing exists according to the density D of the local graph of the metal layer, if so, entering a step S1, otherwise, entering a step S6; s6: judging whether a hot spot needing to optimize the process exists according to the local graph density D of the metal layer, if so, entering step S7, otherwise, entering step S8; s7: optimizing the process according to the product inspection result; s8: and the layout check is passed.
Specifically, please refer to fig. 2, which is a flow chart illustrating a density analysis of a local pattern of a metal layer according to an embodiment of the present invention. Referring to fig. 3, fig. 4 and fig. 5, in which fig. 3 is a schematic diagram of a metal layer region in a layout according to an embodiment of the present invention, and fig. 4 is a schematic cross-sectional diagram of a region where thickness regions corresponding to multiple continuous metal layers in a layout are all oxide according to an embodiment of the present invention. Fig. 5 is a schematic diagram of an expanded region for analyzing the local pattern density of the metal layer in the layout according to an embodiment of the present invention. The method for detecting the defects of the metal layer in the layout comprises the following steps:
s1: the designer completes the layout design;
s2: performing conventional inspection on the layout by adopting a layout design rule formulated by a manufacturer;
s3: judging whether the layout design rule check passes, if so, entering a step S4, and if not, entering a step S1;
s4: analyzing the density of the local graph of the metal layer to obtain the density D of the local graph of the metal layer, comprising the following steps:
s41: as shown in fig. 3 and 4, searching a region in which the thickness directions of n continuous metal layers in the metal layer region 600 are both oxide, and obtaining specific oxide regions 603 and 606 in which the top layer area of the oxide region is greater than S, where n is a natural number greater than or equal to 2;
specifically, referring to fig. 4, as shown in fig. 4, the first metal layer 301, the second metal layer 302 and the third metal layer 303 are continuous metal layers, the thickness direction of the region 603 in the first metal layer 301, the second metal layer 302 and the third metal layer 303, that is, the Y-axis direction in fig. 4, is oxide, and if the top layer area of the region 603 is greater than S, the region is selected to be a specific oxide region 603. A similar oxide region 606 is also found in fig. 3.
In an embodiment of the present invention, a value of n is any one of values between 2 and 8.
In bookIn one embodiment of the invention, the value of S is more than 2um2
S42: as shown in fig. 5, at least one line segment AB of the specific oxide region 603 is selected, two ends of the line segment AB are extended to obtain an extended line segment a 'B', the extended line segment a 'B' is translated to a side far away from the specific oxide region 603 by W to obtain a translated line segment N 'M', and the extended line segment a 'B' and the translated line segment N 'M' form a density pattern region to be measured, such as 601 and 602 in fig. 3 and 5, and density pattern regions to be measured 604 and 605 in fig. 3 obtained from an edge of the specific oxide region 606;
as shown in fig. 5, the pattern area to be measured 602 is obtained by extending and translating the line segment CD of the specific oxide area 603.
In an embodiment of the present invention, the two ends of at least one segment AB of the specific oxide region 603 extend for equal distances. In an embodiment of the present invention, the length of the extended line segment a 'B' is equal to W, that is, the formed pattern area to be measured in density is square.
In an embodiment of the present invention, the value of W is any value between 5um and 1000 um.
S43: and obtaining the metal density D of the pattern areas 601 and 602 with the density to be measured, namely obtaining the local pattern density D of the metal layer.
S5: judging whether a hot spot needing layout changing exists according to the density D of the local graph of the metal layer, if so, entering a step S1, otherwise, entering a step S6;
s6: judging whether a hot spot needing to optimize the process exists according to the local graph density D of the metal layer, if so, entering step S7, otherwise, entering step S8;
s7: optimizing the process according to the product inspection result;
s8: and the layout check is passed.
In an embodiment of the present invention, S5 specifically determines whether D is higher than M, and when D is higher than M, a hot spot that needs to be rearranged exists in the layout. More specifically, S1 further includes adding a redundant pattern in the specific oxide region 603 or reducing the density of the metal pattern in the pattern regions 601 and 602 to reduce the metal pattern defect caused by non-uniform pattern density in the layout.
In an embodiment of the present invention, the value of D is any value between 50% and 100%.
In an embodiment of the present invention, S6 specifically determines whether D is higher than E but lower than M, and if so, there is a hot spot that needs to optimize the process.
More specifically, in one embodiment of the present invention, S41 is to first obtain n continuous metal layers, then find a pure oxide region in the top layer, and project the thickness of the n continuous metal layers downward from the pure oxide region, and the pure oxide region is an oxide within the thickness of the n continuous metal layers, and is a specific oxide region if the top layer area of the oxide region is larger than S. Taking fig. 4 as an example, 301 is a first metal layer, 302 is a second metal layer, 303 is a third metal layer, that is, three continuous metal layers, all of the regions between two continuous metal layers a and b are oxides, and if the top area of the oxide region is larger than S, the oxide region can be selected as a specific oxide region. The area of the top layer is the area of the layout surface.
Therefore, the density analysis of the metal layer local graph is added to obtain the density D of the metal layer local graph, whether a hot spot needing layout changing exists or not or whether a hot spot needing process optimizing exists is judged according to the density D of the metal layer local graph to determine whether the layout needs layout changing or not, a process program is optimized according to a product inspection result or the layout does not need optimizing, and the defect of the metal layer is further effectively avoided. Based on the detection method provided by the invention, the accuracy of defect positioning is improved by 90%, the cycle time of subsequent defect analysis is saved, and the product yield of a manufacturer is improved by at least 5%.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims (10)

1. A method for detecting defects of a metal layer in a layout is characterized by comprising the following steps:
s1: the designer completes the layout design;
s2: performing conventional inspection on the layout by adopting a layout design rule formulated by a manufacturer;
s3: judging whether the layout design rule check passes, if so, entering a step S4, and if not, entering a step S1;
s4: analyzing the density of the local graph of the metal layer to obtain the density D of the local graph of the metal layer, comprising the following steps:
s41: searching regions of which the thickness directions of n continuous metal layers in the metal layer region are all oxides, and obtaining a specific oxide region of which the top layer area of the oxide region is larger than S, wherein n is a natural number larger than or equal to 2;
s42: selecting at least one line segment of the specific oxide area, extending two ends of the line segment to obtain an extended line segment, translating the extended line segment to the side far away from the specific oxide area by W to obtain a translated line segment, and forming a density graph area to be measured by the extended line segment and the translated line segment; and
s43: obtaining the metal density D of the pattern area to be measured to obtain the local pattern density D of the metal layer;
s5: judging whether a hot spot needing layout changing exists according to the density D of the local graph of the metal layer, if so, entering a step S1, otherwise, entering a step S6;
s6: judging whether a hot spot needing to optimize the process exists according to the local graph density D of the metal layer, if so, entering step S7, otherwise, entering step S8;
s7: optimizing the process according to the product inspection result; and
s8: and the layout check is passed.
2. The method for detecting the metal layer defect in the layout according to claim 1, wherein the value of n is any value between 2 and 8.
3. The method for detecting the defect of the metal layer in the layout according to claim 1, wherein the value of S is more than 2um2
4. The method for detecting defects of a metal layer in a layout according to claim 1, wherein the two ends of at least one line segment of the specific oxide region extend for equal distances.
5. The method for detecting defects of a metal layer in a layout according to claim 4, wherein the length of a line segment obtained by extending both ends of at least one line segment of the specific oxide region is equal to W.
6. The method for detecting the defects of the metal layer in the layout according to any one of claims 1 or 5, wherein the value of W is any value between 5um and 1000 um.
7. The method for detecting the defect of the metal layer in the layout according to claim 1, wherein S5 is to determine whether D is higher than M, and when D is higher than M, a hot spot needing layout change exists in the layout.
8. The method for detecting defects of a metal layer in a layout according to claim 7, wherein S1 further comprises adding a redundant pattern in a specific oxide region or reducing the density of the pattern region to be detected and the density of the inner metal pattern.
9. The method for detecting the defects of the metal layer in the layout according to claim 1, wherein the value of D is any value between 50% and 100%.
10. The method for detecting defects of a metal layer in a layout according to claim 1, wherein S6 is to determine whether D is higher than E but lower than M, and if so, there is a hot spot that needs to optimize the process.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050008945A1 (en) * 2003-03-21 2005-01-13 Brooks Cynthia B. Multi-step process for etching photomasks
CN106997401A (en) * 2016-01-22 2017-08-01 中芯国际集成电路制造(上海)有限公司 Extract method, CMP emulation modes and the system of chip layout feature
CN110705203A (en) * 2019-09-24 2020-01-17 上海华力微电子有限公司 Analysis method of layout graph density
CN110888087A (en) * 2018-08-20 2020-03-17 珠海零边界集成电路有限公司 Layout interconnection line defect inspection system and inspection method thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050008945A1 (en) * 2003-03-21 2005-01-13 Brooks Cynthia B. Multi-step process for etching photomasks
CN106997401A (en) * 2016-01-22 2017-08-01 中芯国际集成电路制造(上海)有限公司 Extract method, CMP emulation modes and the system of chip layout feature
CN110888087A (en) * 2018-08-20 2020-03-17 珠海零边界集成电路有限公司 Layout interconnection line defect inspection system and inspection method thereof
CN110705203A (en) * 2019-09-24 2020-01-17 上海华力微电子有限公司 Analysis method of layout graph density

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
潘伟伟;张波;郑勇军;史峥;严晓浪;: "一种改进的测试芯片的设计方法", 电路与系统学报, no. 02, 15 April 2013 (2013-04-15) *

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