CN112256328B - Method and device for generating random command, storage medium and electronic device - Google Patents
Method and device for generating random command, storage medium and electronic device Download PDFInfo
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- CN112256328B CN112256328B CN202011116296.5A CN202011116296A CN112256328B CN 112256328 B CN112256328 B CN 112256328B CN 202011116296 A CN202011116296 A CN 202011116296A CN 112256328 B CN112256328 B CN 112256328B
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- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
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Abstract
Provided are a method for generating a random command, a device for generating a random command, a storage medium, and an electronic device. The random instruction generation method comprises the following steps: constructing an instruction information table, wherein the instruction information table comprises format information of random instructions; extracting format information in the instruction information table, and generating constraint conditions of random instructions based on the format information; random instructions are generated based on the constraints. The method for generating the random instruction can quickly and accurately generate the constraint condition and generate the effective random instruction based on the constraint condition, thereby simplifying the creation process of the random instruction and improving the verification efficiency of the CPU.
Description
Technical Field
Embodiments of the present disclosure relate to a method of generating a random instruction, a device for generating a random instruction, a storage medium, and an electronic device.
Background
x86 generally refers to a family of Intel 8086-based, backward compatible central processor instruction set architectures. The earliest 8086 processors, introduced by Intel in 1978, were 16-bit microprocessors.
Processors were named by Intel in the early 80x86 numerical format, including Intel 8086, 80186, 80286, 80386, and 80486, and the architecture was referred to as "x86" because it ended with "86".
Disclosure of Invention
At least one embodiment of the present disclosure provides a method for generating a random instruction, including: acquiring an instruction information table, wherein the instruction information table comprises format information of the random instruction; extracting format information in the instruction information table, and generating constraint conditions of the random instruction based on the format information; generating the random instruction based on the constraint.
For example, in a generating method provided by at least one embodiment of the present disclosure, extracting format information in the instruction information table, and generating a constraint condition of the random instruction based on the format information includes: traversing the format information in the instruction information table, and storing the format information in a database; decoding a field of the format information stored in the database to convert the format information into a constraint of the random instruction.
For example, the generation method provided by at least one embodiment of the present disclosure further includes: and verifying whether a device (CPU) based on an instruction set architecture can work normally or not through the random instruction.
For example, in a generation method provided by at least one embodiment of the present disclosure, generating the random instruction based on the constraint condition includes: and selecting an instruction meeting the constraint condition from the instruction set based on the constraint condition as the random instruction.
For example, in the generation method provided by at least one embodiment of the present disclosure, the format of the constraint condition conforms to the requirements of the verification system in the instruction set architecture-based device.
For example, in a generation method provided in at least one embodiment of the present disclosure, the verification system includes a test platform and a design circuit, and the generation method of the random instruction further includes: and the test platform determines the random instruction based on the constraint condition, and inputs the random instruction as an excitation into the design circuit for verification.
For example, in a generation method provided by at least one embodiment of the present disclosure, the random instruction includes a random x86 instruction.
For example, in the generation method provided by at least one embodiment of the present disclosure, the format information of the random instruction includes a category, a group, a mnemonic, an operand size, a memory operand prefix, an instruction prefix, and the like of the random instruction.
For example, the generation method provided by at least one embodiment of the present disclosure further includes: updating the instruction information table; and updating the constraint condition of the random instruction according to the format information in the updated instruction information table so as to generate a new random instruction based on the updated constraint condition.
At least one embodiment of the present disclosure further provides a random instruction generating apparatus, including: an obtaining unit configured to obtain an instruction information table, wherein the instruction information table includes format information of the random instruction; a first generation unit configured to extract format information in the instruction information table and generate a constraint condition of the random instruction based on the format information; a second generation unit configured to generate the random instruction based on the constraint condition.
For example, at least one embodiment of the present disclosure provides a random instruction generation apparatus, where the random instruction includes a random x86 instruction.
At least one embodiment of the present disclosure further provides a random instruction generating apparatus, including: a processor; a memory; one or more computer program modules stored in the memory and configured to be executed by the processor, the one or more computer program modules comprising instructions for performing a method of generating random instructions that implements any of the embodiments of the present disclosure.
At least one embodiment of the present disclosure also provides a storage medium that non-transitory stores computer readable instructions that, when executed by a computer, can perform a method of generating random instructions provided according to any one of the embodiments of the present disclosure.
At least one embodiment of the present disclosure further provides an electronic device including the random instruction generating device provided in any embodiment of the present disclosure.
Drawings
To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure and are not limiting to the present disclosure.
Fig. 1 is a flowchart of a method for generating a random instruction according to at least one embodiment of the present disclosure;
FIG. 2 is a flow chart illustrating the generation of a constraint according to at least one embodiment of the present disclosure;
fig. 3 is a flowchart of another random instruction generation method according to at least one embodiment of the present disclosure;
fig. 4 is a schematic block diagram of a random instruction generating apparatus according to at least one embodiment of the present disclosure;
fig. 5 is a schematic block diagram of another random instruction generation apparatus provided in at least one embodiment of the present disclosure;
fig. 6 is a schematic block diagram of an electronic device according to at least one embodiment of the disclosure;
fig. 7 is a schematic structural diagram of an electronic device according to at least one embodiment of the present disclosure; and
fig. 8 is a schematic diagram of a storage medium according to at least one embodiment of the present disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.
Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
Random instructions are critical to the verification of CPU (Central Processing Unit) performance. The x86 Instruction Set Architecture (ISA) has made a profound advancement in computing. However, the complexity of the ISA is a significant challenge to the creation of random instructions, and the complexity and variety of X86 instructions makes it difficult to create efficient random instructions.
The x86 instructions include a wide variety of categories including, for example, general purpose instructions, 64-bit, 128-bit, and 256-bit multimedia instructions, x87 floating point instructions, and system instructions, among others. For the generation of random instructions during CPU performance verification, therefore, CISC (Complex Instruction Set Computing ) itself and various extensions to the x86 Instruction Set architecture have become a significant challenge.
At least one embodiment of the present disclosure provides a method for generating a random instruction, including: constructing an instruction information table, wherein the instruction information table comprises format information of random instructions; extracting format information in the instruction information table, and generating constraint conditions of random instructions based on the format information; random instructions are generated based on the constraints.
Some embodiments of the present disclosure also provide a generation device, an electronic device, and a storage medium corresponding to the random instruction.
According to the method for generating the random instruction, the constraint condition can be generated quickly and accurately, and the effective random instruction is generated based on the constraint condition, so that the generation process of the random instruction can be simplified, and the verification efficiency of a CPU (Central processing Unit) can be improved.
Embodiments of the present disclosure and examples thereof are described in detail below with reference to the accompanying drawings.
At least one embodiment of the present disclosure provides a random instruction generation method, which may be used, for example, to verify whether an instruction set architecture-based device (e.g., a CPU) is operating properly. For example, the random instruction includes a random x86 instruction, which is not limited by the embodiments of the present disclosure.
For example, the method for generating the random instruction may be implemented in a form of software, hardware, firmware, or any combination thereof, and is loaded and executed by a processor in a device such as a mobile phone, a digital camera, a tablet computer, a notebook computer, a desktop computer, a network server, and the like, so as to simplify generation of the random instruction and improve verification efficiency of the CPU.
For example, the method for generating the random instruction is applicable to a computing apparatus, and the computing apparatus includes any electronic device with a computing function, such as a mobile phone, a digital camera, a notebook computer, a tablet computer, a desktop computer, a web server, and the like, and can load and execute the method for generating the random instruction, which is not limited in this respect. For example, the computing device may include a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a Digital Signal Processor (DSP), and other forms of Processing units, storage units, and the like having data Processing capability and/or instruction execution capability, and the computing device may further have an operating system, an application programming interface (OpenGL), a Metal, and the like installed thereon, and implement the method for generating random instructions provided by the embodiments of the present disclosure by running codes or instructions.
Fig. 1 is a flowchart of a method for generating a random instruction according to at least one embodiment of the present disclosure. The method for generating random instructions according to at least one embodiment of the present disclosure is described in detail below with reference to fig. 1. For example, in some examples, as shown in fig. 1, the random instruction generation method includes steps S110 to S130.
Step S110: and acquiring an instruction information table.
Step S120: and extracting format information in the instruction information table, and generating constraint conditions of the random instruction based on the format information.
Step S130: random instructions are generated based on the constraints.
For step S110, for example, the instruction information table includes format information of the random instruction, or encoding information. For example, the instruction information table is shown in table 1, and includes, for example, a category, a group, a mnemonic, an operand size, a memory operand prefix, an instruction prefix, and the like of a random instruction, and may also include more or less format information, which is not limited in this respect by the embodiments of the present disclosure.
TABLE 1
For example, the category of the random instruction may include a multimedia category, a floating point category, a system category, and the like in addition to the general category shown in table 1, and the group of the random instruction may include comparison, logic, and the like in addition to the operation (for example, including addition, subtraction, multiplication, division, and the like) shown in table 1, which is not limited by the embodiment of the present disclosure. For example, the operand size of the random instruction is 16, 32, or 64 according to different mnemonics, which may be the case, and the embodiments of the present disclosure are not limited thereto. The specific meaning of the format information in the instruction information table can refer to the explanation in the field, and is not described herein again.
It should be noted that the format information is not limited to the information in the instruction information table, and the specific content of the format information may also be updated according to different requirements, which is not limited in this embodiment of the disclosure.
For example, the instruction information table may be a manually constructed electronic table or a table automatically generated based on specific requirements, which is not limited by the embodiments of the present disclosure.
For step S120, for example, by running the script program to read the format information in the instruction information table, and automatically generate the constraint condition of the random instruction based on the format information, instead of manually adding the constraint, the generation efficiency of the constraint condition of the random instruction can be improved, the generation process of the random instruction is simplified, and the verification efficiency of the CPU is improved.
Fig. 2 is a flowchart of generating a constraint according to at least one embodiment of the present disclosure. That is, fig. 2 is a flowchart of at least one example of step S120 in fig. 1. As shown in fig. 2, the generation process of the constraint condition includes step S121 and step S122.
Step S121: and traversing the format information in the instruction information table, and storing the format information in a database.
For example, by running a script program to traverse all information in the instruction information table and storing the traversed information in a database, the script program may adopt a routine program in the art, and will not be described herein again.
Step S122: the fields of the format information stored in the database are decoded to convert the format information into constraints of the random instruction.
For example, the information stored in the database is also in the form of a field in the instruction information table (for example, in the form of a word that can be recognized by the user in table 1 above), and in this step S122, the field of the format information stored in the database is decoded and converted into a language format that can be recognized by the verification system, so that the format information in the instruction information table is converted into a constraint condition that can be read by the verification system and used for generating a random instruction. For example, the specific decoding method may adopt a decoding method in the art, and is not described herein again.
For example, some of the constraints of the random instructions generated according to Table 1 are as follows:
(instr_prefix inside{LOCK})&&
(operand_imm[0]<＝((1<<8)-1))&&
(num_operand＝＝2))||
((instruction_type＝＝INST_TYPE_2OP_REG_IMM)&&
(operand_dst_reg inside{REGS_32BIT_MODE})&&
(operand_imm[0]<＝((1<<32)-1))&&
(num_operand＝＝2))||
((instruction_type＝＝INST_TYPE_2OP_REG_REG)&&
(operand_dst_reg inside{REGS_16BIT_MODE})&&
(operand_scr_reg[0]inside{REGS_16BIT_MODE})&&
(num_operand＝＝2))
that is, the format information in table 1 is converted into the language format that can be recognized by the verification system, thereby generating the constraint condition of the random command.
With respect to step S130, for example, an instruction meeting the constraint condition is selected from an instruction set (e.g., the instruction set) based on the constraint condition readable by the verification system as a random instruction, so as to verify whether the device (e.g., CPU) based on the instruction set architecture can normally operate through the random instruction, for example, to verify whether the CPU can perform a corresponding operation according to the random instruction. For example, the instruction set based architecture may be an X86 architecture or an ARM architecture, and embodiments of the present disclosure are not limited in this respect.
For example, the instruction set architecture includes a verification system in the device. For example, the verification system is a Verilog system. For example, the format of the constraints conforms to the requirements of a verification System (System Verilog) in an instruction set architecture-based device, i.e., a language format that can be recognized by the verification System as described above.
For example, in some examples, a verification system includes a test platform and a design circuit. For example, the test platform is used to input random instructions as stimuli into the design circuit to verify whether the design circuit is capable of executing the random instructions.
For example, in this case, the random instruction generation method further includes: the test platform determines a random instruction based on the constraint condition, and inputs the random instruction as an excitation into the design circuit for verification. For example, the test platform selects an instruction satisfying the constraint condition from the instruction set as a random instruction, and inputs the random instruction into a design circuit in the verification system for verification.
According to the method for generating the random instruction provided by the embodiment of the disclosure, the constraint condition can be generated quickly and accurately by processing the spreadsheet, and the effective random instruction is generated based on the constraint condition, so that the generation process of the random instruction can be simplified, and the verification efficiency of the CPU can be improved.
Fig. 3 is a flowchart of another random instruction generation method according to at least one embodiment of the present disclosure. For example, based on the example shown in fig. 1, the schematic diagram of the random instruction generation method shown in fig. 3 further includes step S140 and step S150.
Step S140: updating the instruction information table;
step S150: and updating the constraint conditions of the random instruction according to the format information in the updated instruction information table so as to generate a new random instruction based on the updated constraint conditions.
For step S140, for example, the format information in the instruction information table is updated according to different requirements. For example, the information in table 1 above is updated. For example, the categories in table 1 are changed from general categories to floating-point categories, and the specific update information may be determined according to actual situations, which is not limited by the embodiment of the present disclosure.
With respect to step S150, for example, the format information in the updated instruction information table is extracted to generate a random instruction satisfying a new constraint based on the updated format information.
For example, in this example, the instruction information table is updated to generate random instructions satisfying different constraint conditions, so that the constraint conditions can be generated quickly and accurately, effective random instructions are generated based on the constraint conditions, the workload of generating the random instructions is reduced, the effective random instructions are favorably input into the verification system for verification, the generation of invalid random instructions for invalid verification is avoided, the complexity of the ISA, the complexity of the CISC and the influence of various extensions of the instruction set on the generation of the random instructions are reduced, and the verification efficiency of the CPU is improved.
It should be noted that, in the embodiments of the present disclosure, the execution order of the steps of the random instruction generation method is not limited, and although the execution process of the steps is described in a specific order above, this does not constitute a limitation to the embodiments of the present disclosure. The steps in the random instruction generation method may be executed in series or in parallel, which may depend on actual requirements. The random instruction generation method may further include more or fewer steps, for example, some preprocessing steps may be added to achieve a faster instruction generation effect, or some intermediate process data may be stored and used for subsequent processing and calculation, so as to omit some similar steps.
Fig. 4 is a schematic block diagram of a random instruction generation apparatus according to at least one embodiment of the present disclosure. For example, in the example shown in fig. 4, the random instruction generation apparatus 100 includes an acquisition unit 110, a first generation unit 120, and a second generation unit 130. For example, these units may be implemented by a hardware (e.g., circuit) module, a software module, or any combination of the two, and the following embodiments are the same and will not be described again. These units may be implemented, for example, by a Central Processing Unit (CPU), image processor (GPU), tensor Processor (TPU), field Programmable Gate Array (FPGA) or other form of processing unit having data processing and/or instruction execution capabilities and corresponding computer instructions.
The generation unit 110 is configured to acquire an instruction information table. For example, the instruction information table includes format information of the random instruction. For example, the generating unit 110 may implement the step S110, and a specific implementation method thereof may refer to the related description of the step S110, which is not described herein again.
The first generation unit 120 is configured to extract format information in the instruction information table and generate a constraint condition of the random instruction based on the format information. For example, the first generating unit 120 may implement step S120, and the specific implementation method may refer to the related description of step S120, which is not described herein again.
The second generation unit 130 is configured to generate random instructions based on the constraints. For example, the second generating unit 130 may implement step S130, and the specific implementation method thereof may refer to the related description of step S130, which is not described herein again.
It should be noted that, in the embodiment of the present disclosure, the random instruction generating apparatus 100 may include more or less circuits or units, and the connection relationship between the respective circuits or units is not limited and may be determined according to actual requirements. The specific configuration of each circuit is not limited, and may be configured by an analog device, a digital chip, or other suitable configurations according to the circuit principle.
Fig. 5 is a schematic block diagram of another random instruction generation apparatus according to at least one embodiment of the present disclosure. For example, as shown in FIG. 5, the random instruction generating apparatus 200 includes a processor 210, a memory 220, and one or more computer program modules 221.
For example, the processor 210 and the memory 220 are connected by a bus system 230. For example, one or more computer program modules 221 are stored in memory 220. For example, one or more computer program modules 221 include instructions for performing the method of generating random instructions provided by any of the embodiments of the present disclosure. For example, instructions in one or more computer program modules 221 may be executed by processor 210. For example, the bus system 230 may be a conventional serial, parallel communication bus, etc., and embodiments of the present disclosure are not limited in this respect.
For example, the processor 210 may be a Central Processing Unit (CPU), a Digital Signal Processor (DSP), an image processor (GPU) or other form of processing unit having data processing capability and/or instruction execution capability, may be a general purpose processor or a special purpose processor, and may control other components in the random instruction generating apparatus 200 to perform desired functions.
Memory 220 may include one or more computer program products that may include various forms of computer-readable storage media, such as volatile memory and/or non-volatile memory. The volatile memory may include, for example, random Access Memory (RAM), cache memory (cache), and/or the like. The non-volatile memory may include, for example, read Only Memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on a computer-readable storage medium and executed by processor 210 to implement the functions of the embodiments of the disclosure (implemented by processor 210) and/or other desired functions, such as a method of generating random instructions, etc. Various applications and various data, such as instruction information tables, constraints, and various data used and/or generated by the applications, may also be stored in the computer-readable storage medium.
It should be noted that, for clarity and conciseness, not all the constituent elements of the random instruction generating apparatus 200 are shown in the embodiments of the present disclosure. In order to implement the necessary functions of the random instruction generating apparatus 200, those skilled in the art may provide and arrange other components not shown according to specific needs, and the embodiment of the present disclosure is not limited thereto.
For technical effects of the random instruction generation apparatus 100 and the random instruction generation apparatus 200 in different embodiments, reference may be made to technical effects of the random instruction generation method provided in the embodiments of the present disclosure, and details are not described here.
At least one embodiment of the present disclosure further provides an electronic device. Fig. 6 is a schematic block diagram of an electronic device according to at least one embodiment of the present disclosure. As shown in fig. 6, the electronic device 1 includes a random instruction generating device 100/200 provided in any embodiment of the present disclosure.
For example, the electronic apparatus may be any electronic device with a computing function, for example, a mobile phone, a digital camera, a notebook computer, a tablet computer, a desktop computer, a network server, and the like, and may load and execute the method for generating the random instruction, which is not limited in this respect.
It should be noted that, for clarity and conciseness, not all the constituent elements of the electronic device 1 are shown in the embodiments of the present disclosure. To realize the necessary functions of the electronic device 1, those skilled in the art may provide and arrange other components not shown according to specific needs, and the embodiment of the present disclosure is not limited thereto.
Regarding the technical effects of the electronic device 1 in the above embodiments, reference may be made to the technical effects of the method for generating the random command provided in the embodiments of the present disclosure, and details are not described here.
The random instruction generating apparatus 100 and the random instruction generating apparatus 200 may be used for various appropriate electronic devices (e.g., terminal devices or servers). Fig. 7 is a schematic structural diagram of an electronic device according to at least one embodiment of the present disclosure. The terminal device in the embodiments of the present disclosure may include, but is not limited to, a mobile terminal such as a mobile phone, a digital camera, a notebook computer, a digital broadcast receiver, a PDA (personal digital assistant), a PAD (tablet computer), a PMP (portable multimedia player), a vehicle terminal (e.g., a car navigation terminal), and the like, and a fixed terminal such as a digital TV, a desktop computer, and the like. The electronic device shown in fig. 7 is only an example, and should not bring any limitation to the functions and the scope of use of the embodiments of the present disclosure.
For example, as shown in fig. 7, in some examples, electronic device 300 includes a processing device (e.g., central processing unit, graphics processor, etc.) 301 that may perform various appropriate actions and processes in accordance with a program stored in a Read Only Memory (ROM) 302 or a program loaded from a storage device 308 into a Random Access Memory (RAM) 303. In the RAM303, various programs and data necessary for the operation of the computer system, for example, the script program of the above-described read instruction information table, are also stored. The processing device 301, the ROM302, and the RAM303 are connected to each other via a bus 304. An input/output (I/O) interface 305 is also connected to bus 304.
For example, input devices 306 including, for example, a touch screen, touch pad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, etc.; an output device 307 including a display such as a Liquid Crystal Display (LCD), speaker, vibrator, etc.; storage devices 308 including, for example, magnetic tape, hard disk, etc.; and a communication device 309 including a network interface card such as a LAN card, modem, or the like. The communication means 309 may allow the electronic apparatus 300 to perform wireless or wired communication with other apparatuses to exchange data, performing communication processing via a network such as the internet. A drive 310 is also connected to the I/O interface 305 as needed. A removable medium 311 such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, or the like is mounted on the drive 310 as necessary, so that a computer program read out therefrom is mounted into the storage device 309 as necessary. While fig. 7 illustrates an electronic device 300 that includes various means, it is to be understood that not all illustrated means are required to be implemented or included. More or fewer devices may be alternatively implemented or included.
For example, the electronic device 300 may further include a peripheral interface (not shown in the figure) and the like. The peripheral interface may be various types of interfaces, such as a USB interface, a lightning (lighting) interface, and the like. The communication device 309 may communicate with networks such as the internet, intranets, and/or wireless networks such as cellular telephone networks, wireless Local Area Networks (LANs), and/or Metropolitan Area Networks (MANs) and other devices via wireless communication. The wireless communication may use any of a number of communication standards, protocols, and technologies, including, but not limited to, global system for mobile communications (GSM), enhanced Data GSM Environment (EDGE), wideband code division multiple access (W-CDMA), code Division Multiple Access (CDMA), time Division Multiple Access (TDMA), bluetooth, wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and/or IEEE 802.11n standards), voice over internet protocol (VoIP), wi-MAX, protocols for email, instant messaging, and/or Short Message Service (SMS), or any other suitable communication protocol.
For example, the electronic device may be any device such as a mobile phone, a tablet computer, a notebook computer, an electronic book, a game machine, a television, a digital photo frame, and a navigator, and may also be any combination of electronic devices and hardware, which is not limited in this respect in the embodiments of the disclosure.
For example, the processes described above with reference to the flowcharts may be implemented as computer software programs, according to embodiments of the present disclosure. For example, embodiments of the present disclosure include a computer program product comprising a computer program carried on a non-transitory computer readable medium, the computer program containing program code for performing the method illustrated by the flow chart. In such an embodiment, the computer program may be downloaded and installed from a network via the communication means 309, or installed from the storage means 308, or installed from the ROM 302. When executed by the processing device 301, performs the above-described random instruction generation function defined in the method of the embodiment of the present disclosure.
It should be noted that the computer readable medium in the present disclosure can be a computer readable signal medium or a computer readable storage medium or any combination of the two. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples of the computer readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In embodiments of the disclosure, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. In embodiments of the present disclosure, however, a computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take many forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: electrical wires, optical cables, RF (radio frequency), etc., or any suitable combination of the foregoing.
In some embodiments, the clients, servers may communicate using any currently known or future developed network Protocol, such as HTTP (HyperText Transfer Protocol), and may interconnect with any form or medium of digital data communication (e.g., a communications network). Examples of communication networks include a local area network ("LAN"), a wide area network ("WAN"), the Internet (e.g., the Internet), and peer-to-peer networks (e.g., ad hoc peer-to-peer networks), as well as any currently known or future developed network.
The computer readable medium may be embodied in the electronic device; or may exist separately without being assembled into the electronic device.
The computer readable medium carries one or more programs which, when executed by the electronic device, cause the electronic device to: acquiring at least two internet protocol addresses; sending a node evaluation request comprising the at least two internet protocol addresses to node evaluation equipment, wherein the node evaluation equipment selects the internet protocol addresses from the at least two internet protocol addresses and returns the internet protocol addresses; receiving an internet protocol address returned by the node evaluation equipment; the acquired internet protocol address indicates an edge node in the content distribution network.
Alternatively, the computer readable medium carries one or more programs which, when executed by the electronic device, cause the electronic device to: receiving a node evaluation request comprising at least two internet protocol addresses; selecting an internet protocol address from the at least two internet protocol addresses; returning the selected internet protocol address; the received internet protocol address indicates an edge node in the content distribution network.
Computer program code for carrying out operations for the present disclosure may be written in any combination of one or more programming languages, including but not limited to an object oriented programming language such as Java, smalltalk, C + +, and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet service provider).
The functions described herein above may be performed, at least in part, by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), systems on a chip (SOCs), complex Programmable Logic Devices (CPLDs), and the like.
In various embodiments of the disclosure, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
At least one embodiment of the present disclosure also provides a storage medium. Fig. 8 is a schematic diagram of a storage medium according to at least one embodiment of the present disclosure. For example, as shown in fig. 8, the storage medium 400 stores non-transitory computer readable instructions 401, which can perform the random instruction generation method provided by any embodiment of the present disclosure when the non-transitory computer readable instructions are executed by a computer (including a processor).
For example, the storage medium can be any combination of one or more computer-readable storage media, such as one containing computer-readable program code that extracts format information in an instruction information table and generates constraints for the random instructions based on the format information, and another containing computer-readable program code that generates the random instructions based on the constraints. For example, when the program code is read by a computer, the computer may execute the program code stored in the computer storage medium to perform a method of generating random instructions such as provided by any of the embodiments of the present disclosure.
For example, the storage medium may include a memory card of a smart phone, a storage component of a tablet computer, a hard disk of a personal computer, a Random Access Memory (RAM), a Read Only Memory (ROM), an Erasable Programmable Read Only Memory (EPROM), a portable compact disc read only memory (CD-ROM), a flash memory, or any combination of the above, as well as other suitable storage media.
The following points need to be explained:
(1) The drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to the common design.
(2) Without conflict, embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments.
The above description is intended to be exemplary of the present disclosure, and not to limit the scope of the present disclosure, which is defined by the claims appended hereto.
Claims (12)
1. A method of generating random instructions, comprising:
acquiring an instruction information table, wherein the instruction information table comprises format information of the random instruction;
extracting format information in the instruction information table, and generating constraint conditions of the random instruction based on the format information;
generating the random instruction based on the constraint condition,
extracting format information in the instruction information table, and generating constraint conditions of the random instruction based on the format information, wherein the constraint conditions comprise:
traversing format information in the instruction information table, and storing the format information in a database;
decoding a field of the format information stored in the database to convert the format information into a constraint of the random instruction,
wherein generating the random instruction based on the constraint condition comprises:
and selecting an instruction meeting the constraint condition from an instruction set based on the constraint condition as the random instruction.
2. The generation method of claim 1, further comprising:
and verifying whether the device based on the instruction set architecture can work normally or not through the random instruction.
3. The generation method of claim 2, wherein the format of the constraint conforms to requirements of a validation system in the instruction set architecture based device.
4. The generation method of claim 3, wherein the verification system comprises a test platform and a design circuit,
the method for generating the random instruction further comprises the following steps:
and the test platform determines the random instruction based on the constraint condition, and inputs the random instruction as an excitation into the design circuit for verification.
5. The generation method of any of claims 1-4, wherein the random instruction comprises a random x86 instruction.
6. The generation method according to any one of claims 1 to 4, wherein the format information of the random instruction includes a category, a group, a mnemonic, an operand size, a memory operand prefix, an instruction prefix, and the like of the random instruction.
7. The generation method according to any one of claims 1 to 4, further comprising:
updating the instruction information table;
and updating the constraint condition of the random instruction according to the format information in the updated instruction information table so as to generate a new random instruction based on the updated constraint condition.
8. A random instruction generating apparatus comprising:
an obtaining unit configured to obtain an instruction information table, wherein the instruction information table includes format information of the random instruction;
a first generation unit configured to extract format information in the instruction information table and generate a constraint condition of the random instruction based on the format information;
a second generation unit configured to generate the random instruction based on the constraint condition,
extracting format information in the instruction information table, and generating constraint conditions of the random instruction based on the format information, wherein the constraint conditions comprise:
traversing format information in the instruction information table, and storing the format information in a database;
decoding a field of the format information stored in the database to convert the format information into a constraint of the random instruction,
wherein generating the random instruction based on the constraint condition comprises:
and selecting an instruction meeting the constraint condition from an instruction set based on the constraint condition as the random instruction.
9. The random instruction generating apparatus of claim 8, wherein the random instruction comprises a random x86 instruction.
10. A random instruction generating apparatus comprising:
a processor;
a memory;
one or more computer program modules stored in the memory and configured to be executed by the processor, the one or more computer program modules comprising instructions for performing a method of generating random instructions according to any one of claims 1 to 7.
11. A storage medium storing, non-transitory, computer-readable instructions that when executed by a computer perform a method of generating random instructions according to any one of claims 1 to 7.
12. An electronic device comprising the random instruction generating device of claim 10.
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| CN100562879C (en) * | 2008-05-16 | 2009-11-25 | 浙江大学 | A kind of dynamic simulation platform method that is used for embedded processor function verification |
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| CN102455971B (en) * | 2010-10-28 | 2014-09-03 | 无锡江南计算技术研究所 | Application-level random instruction testing method, system and device |
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