CN112242850B - Method for automatically coding common code pattern - Google Patents
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
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Abstract
The invention discloses a method for automatically coding a common code pattern, which comprises the following steps: firstly, inputting an automatic coding mode, selecting the following modes PRBS, CRC, SCR, DSCR, MOD, GFMUTI, and then inputting related parameters according to specific conditions; PRBS mode and MOD mode directly input parameters; in CRC mode, SCR mode and DSCR mode, firstly selecting A or B, and then inputting parameters according to the modes; the GFMUTI mode firstly selects a mode A, a mode B or a mode C, and then parameters are input; and finally, automatically encoding according to the input parameters and outputting codes. The invention can automatically generate various codes corresponding to different conditions, and can automatically generate various bit widths and codes corresponding to different conditions; the coding time can be greatly saved, and the method is convenient, efficient and quick.
Description
Technical Field
The invention belongs to the technical field of automatic coding, and particularly relates to a method for automatically coding a common code pattern.
Background
The processing of data streams in communication systems is often represented in binary form, and the processing of codes is also bit-processed. Therefore, the bit width of the input and output data is different for the same encoding mode, and the encoding mode is also different.
Existing patterns include prbs patterns, crc check codes, modulo, scrambling, descrambling, and Galois field multiplication. Thus, the data bit width may be different for practical situations, possibly due to the different traffic clock frequencies. For the condition that the input and output bit widths are different, the same code pattern needs to be recoded, and the repeated work is performed, so that the labor is consumed.
Disclosure of Invention
The invention aims to provide a method for automatically coding a common code pattern, which solves the problems of time consumption and labor consumption in recoding under different conditions in the background technology.
The related operations of various prbs code types, crc check code types, modulo circuits, scrambling, descrambling and Galois field are basically related to polynomial operations, the input and output in the actual codes are usually parallel, and serial-parallel conversion is completed through a serial circuit, so that parallel data output is obtained.
The Prbs pattern is relatively simple and only correlates with the output data bit width, and for automatic encoding only two parameters are needed, the output bit width output_width and the Prbs pattern formula, the PRBS pattern principle is shown in FIG. 1.
Crc check code generation, and crc check code coding generation mainly comprises two cases, wherein the first is the crc check code for directly obtaining complete data; at this time, the automatic coding needs to input parameters including bit width input_width and crc check polynomials of input data; in the second case, the crc check code is obtained for the continuous data stream, and the input parameter is the input data bit width_width, and the crc check polynomial is needed; the two cases have the same input parameters, but the code output is different, the code automatically generated in the first case comprises a data input and a check output, the code automatically generated in the second case comprises a data output and a check code input, and the check code output is shown in the schematic diagram of the crc8 in fig. 2, and the crc polynomial is x8+x2+x1+1.
Scrambling can be generally divided into two modes in a communication system, and codes can be automatically generated only by inputting data bit width by parameters; the first mode is that the input data participate in the scrambling of the coding, and the other mode is that the input data do not participate in the scrambling of the coding; the scrambling principle of the first input data participating in the encoding is shown in fig. 3, and the scrambling of the second input data not participating in the encoding is shown in fig. 4.
Descrambling corresponds to scrambling, but the coding modes are different; there are two cases as well, the first input data participates in the descrambling of the code, the descrambling principle is shown in fig. 5; the second type of input data does not participate in the unscrambling schematic diagram, and is identical to the corresponding scrambling principle.
The polynomial modulus operation is carried out, and binary numbers and modulus polynomial parameters are input to obtain modulus binary numbers; taking x8+ x2+ x1+1 as an example, the serial operation circuit is shown in fig. 6.
Galois field multiplication includes inputting two binary numbers for multiplication, inputting a binary number for multiplication with a polynomial, and obtaining binary representation results; the first two binary galois fields are multiplied; the binary multiplication firstly obtains a product according to a multiplication rule, and then takes a module for a generator polynomial; second, the binary number is multiplied by a polynomial, which is first converted to a binary number in the Galois field and then processed as in the first case.
The invention provides a method for automatically coding a common code pattern, which comprises the following steps:
the mode of automatic coding is first entered, the following modes are selected PRBS, CRC, SCR, DSCR, MOD, GFMUTI, and then relevant parameters are entered according to the specific circumstances:
parameters are input in PRBS mode: the input data bit width is input_width, and the prbs code pattern polynomial is only needed.
In CRC mode, A or B is selected first; mode a: inputting parameters: inputting a data bit width input_width, and inputting a crc check polynomial; mode B: inputting parameters: the input data bit width input_width is input, and the crc check polynomial is input.
In the SCR mode, firstly selecting a mode A or a mode B; mode a: inputting parameters: inputting a data bit width input_width, and inputting a scrambling polynomial; mode B: inputting parameters: the input data bit width is input_width, and the scrambling polynomial is input.
Selecting a mode A or B in a DSCR mode; mode a: inputting parameters: inputting a data bit width input_width, and inputting a scrambling polynomial; mode B: inputting parameters: the input data bit width is input_width, and the scrambling polynomial is input.
MOD mode; inputting parameters: the input data bit width input_width is input to the modulo polynomial.
The GFMUTI mode first selects either mode a or B or C; mode a: inputting bit width of two binary numbers, input_width1, input_width2 and Galois field primitive polynomial; mode B: inputting a binary bit width input_width, a polynomial F1 and a primitive polynomial formula; mode C: the polynomials F1 and F2 and the primitive polynomial formula are input.
And automatically encoding according to the input parameters, and outputting codes.
Further: the input parameters are expressed in decimal system.
Further: the formula refers to a code generating polynomial, which is used for coding, for example, there are a plurality of generating polynomials for crc, the generating polynomial for crc4 is x4+x3+1, the generating polynomial for crc8 is x8+x2+x1+1, or x8+x5+x4+1, and the polynomial F represents the same formula, and if an error is input, the relevant error is prompted, and the return is returned.
Compared with the prior art, the invention has the beneficial effects that: the technical method of the invention can automatically generate various codes corresponding to different conditions, and can automatically generate codes with various bit widths and various codes under different conditions. The coding time can be greatly saved, and the method is convenient, efficient and quick.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate the invention and together with the embodiments of the invention, and do not limit the invention. In the drawings:
FIG. 1 is a schematic diagram of PRBS patterns.
Fig. 2 is a schematic diagram of the crc 8.
Fig. 3 is a schematic diagram of a first way of scrambling.
Fig. 4 is a schematic diagram of a second way of scrambling.
Fig. 5 is a schematic diagram of a first way of descrambling.
Fig. 6 is a circuit diagram of a modulus taking circuit.
Fig. 7 is an automatic encoding flow chart of the present invention.
Detailed Description
The technical scheme of the patent is further described in detail below with reference to the specific embodiments.
Referring to fig. 7, a method for automatically encoding a common code pattern includes the following steps:
the mode of automatic coding is first entered, the following modes are selected PRBS, CRC, SCR, DSCR, MOD, GFMUTI, and then relevant parameters are entered according to the specific circumstances:
parameters are input in PRBS mode: the input data bit width is input_width, and the prbs pattern polynomial.
In CRC mode, A or B is selected first; mode a: inputting parameters: inputting a data bit width input_width, and inputting a crc check polynomial; mode B: inputting parameters: the input data bit width input_width is input, and the crc check polynomial is input.
In the SCR mode, firstly selecting a mode A or a mode B; mode a: inputting parameters: inputting a data bit width input_width, and inputting a scrambling polynomial; mode B: inputting parameters: the input data bit width is input_width, and the scrambling polynomial is input.
Selecting a mode A or B in a DSCR mode; mode a: inputting parameters: inputting a data bit width input_width, and inputting a scrambling polynomial; mode B: inputting parameters: the input data bit width is input_width, and the scrambling polynomial is input.
MOD mode; inputting parameters: the input data bit width input_width is input to the modulo polynomial.
The GFMUTI mode first selects either mode a or B or C; mode a: inputting bit width of two binary numbers, input_width1, input_width2 and Galois field primitive polynomial; mode B: inputting a binary bit width input_width, a polynomial F and a primitive polynomial formula; mode C: the polynomials F1, F2 are input, primitive polynomials formula.
And automatically encoding according to the input parameters, and outputting codes.
The automatic coding mode adopts perl to realize automatic coding.
The input parameters are expressed in decimal system.
The formula refers to a coded generator polynomial that is used for coding, for example, there are many generator polynomials for crc, the generator polynomial for crc4 is x4+x3+1, and the generator polynomial for crc8 is x8+x2+x1+1, or x8+x5+x4+1.
Polynomial F represents the same formula, and if an error is entered, the relevant error is prompted and exit is returned.
The invention can automatically code various conditions, can automatically code according to different coding modes, different code patterns and different bit widths, saves time, and is efficient and convenient.
The foregoing is a description of embodiments of the invention, which are specific and detailed, but are not to be construed as limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention.
Claims (3)
1. A method for automatically encoding a common code pattern, comprising the steps of:
firstly, inputting an automatic coding mode, selecting the following modes PRBS, CRC, SCR, DSCR, MOD, GFMUTI, and then inputting related parameters according to specific conditions;
parameters are input in PRBS mode: input data bit width_width, prbs code pattern polynomial;
in CRC mode, A or B is selected first; mode a: inputting parameters: inputting a data bit width input_width, and inputting a crc check polynomial; mode B: inputting parameters: inputting a data bit width input_width, and inputting a crc check polynomial;
in the SCR mode, firstly selecting a mode A or a mode B; mode a: inputting parameters: inputting a data bit width input_width, and inputting a scrambling polynomial; mode B: inputting parameters: inputting a data bit width input_width, and inputting a scrambling polynomial;
selecting a mode A or B in a DSCR mode; mode a: inputting parameters: inputting a data bit width input_width, and inputting a scrambling polynomial; mode B: inputting parameters: inputting a data bit width input_width, and inputting a scrambling polynomial;
MOD mode; inputting parameters: inputting a data bit width input_width, and inputting a modular polynomial;
the GFMUTI mode first selects either mode a or B or C; mode a: inputting bit width of two binary numbers, input_width1, input_width2 and Galois field primitive polynomial; mode B: inputting a binary bit width input_width, a polynomial F and a primitive polynomial formula; mode C: inputting polynomials F1 and F2 and primitive polynomials formula;
automatically encoding according to the input parameters and outputting codes;
mode A in the CRC mode is a CRC check code for directly solving the complete data; mode B is to calculate the crc check code for the continuous data stream; the mode A and the mode B have the same input parameters, but different codes are output by encoding, the code automatically generated by the mode A comprises a data input and a check output, and the mode B comprises a data output and a check code input and a check code output;
the mode A of the SCR mode is scrambling of the input data participating in encoding; mode B is the scrambling of input data not participating in encoding;
the DSCR mode corresponds to the SCR mode, and mode A input data in the DSCR mode participates in descrambling of the code; the schematic diagram of the mode B input data in DSCR mode not participating in descrambling is exactly the same as the corresponding scrambling principle.
2. The method for automatically encoding a common pattern according to claim 1, wherein said input_width is represented by decimal.
3. The method of automatic coding of a common pattern according to claim 1, wherein pattern a in the GFMUTI mode represents multiplication of two binary galois fields; the binary multiplication firstly obtains a product according to a multiplication rule, and then takes a module for a generator polynomial; pattern B in GFMUTI mode represents the multiplication of a binary number with a polynomial that is first converted to a binary number in the galois field and then processed as in pattern a.
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| WO2010135942A1 (en) * | 2009-05-25 | 2010-12-02 | 中兴通讯股份有限公司 | Method and device for fast cyclic redundancy check coding |
| CN101908894A (en) * | 2009-06-08 | 2010-12-08 | 中兴通讯股份有限公司 | Code realizing system and method in multi-code mode |
| CN202261656U (en) * | 2011-12-20 | 2012-05-30 | 大连大学 | Automatic switchover encoding device |
| CN102820892A (en) * | 2012-06-20 | 2012-12-12 | 记忆科技(深圳)有限公司 | Circuit for parallel BCH (broadcast channel) coding, encoder and method |
| CN106933560A (en) * | 2015-12-30 | 2017-07-07 | 远光软件股份有限公司 | A kind of automatic coding and device |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010135942A1 (en) * | 2009-05-25 | 2010-12-02 | 中兴通讯股份有限公司 | Method and device for fast cyclic redundancy check coding |
| CN101908894A (en) * | 2009-06-08 | 2010-12-08 | 中兴通讯股份有限公司 | Code realizing system and method in multi-code mode |
| CN202261656U (en) * | 2011-12-20 | 2012-05-30 | 大连大学 | Automatic switchover encoding device |
| CN102820892A (en) * | 2012-06-20 | 2012-12-12 | 记忆科技(深圳)有限公司 | Circuit for parallel BCH (broadcast channel) coding, encoder and method |
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