CN112242839A

CN112242839A - Output buffer and method for operating a multi-modal output buffer connected between a host device and a receiving device

Info

Publication number: CN112242839A
Application number: CN202010684685.1A
Authority: CN
Inventors: A·A·坎普; R·潘迪
Original assignee: Semiconductor Components Industries LLC
Current assignee: Semiconductor Components Industries LLC
Priority date: 2019-07-19
Filing date: 2020-07-16
Publication date: 2021-01-19

Abstract

The invention provides an output buffer and a method for operating a multi-modal output buffer connected between a host device and a receiving device. The present invention relates to an output buffer and a method for operating a multi-modal output buffer connected between a host device and a receiving device. The output buffer is configured to execute in a DP mode and an HDMI mode, and to satisfy certain compliance conditions in an HDMI compliance test mode. The output buffer comprises a plurality of transistors and resistors arranged to operate in DP mode and HDMI mode. The plurality of transistors and resistors are arranged to reduce leakage current during the HDMI compliance test mode.

Description

Output buffer and method for operating a multi-modal output buffer connected between a host device and a receiving device

Cross Reference to Related Applications

This application is based on and claims the benefit of indian provisional application No. 201911029159 filed 2019, 7/19, the contents of which are incorporated herein by reference.

Technical Field

The present invention relates to an output buffer and a method for operating a multi-modal output buffer connected between a host device and a receiving device.

Background

Many electrical systems utilize an interface to transfer data between a host device and a receiving device. In many cases, the interface may be configured for multi-protocol applications, such as Displayport (DP), USB, and/or HDMI (high definition multimedia interface). In the case of AC-coupled applications (e.g., DP, USB), the linearity of the interface (the degree to which the output follows the input) is a performance metric. In the case of a DC-coupled application (e.g., HDMI), the amount of leakage current when the host is off and the receiving device is on may be used to determine whether the interface meets certain compliance specifications (e.g., "V |)_OFFCompliance test "where the leakage current must be less than 200 uA). Conventional interfaces may use external and/or internal diodes to satisfy V_OFFCompliance testing, however, the use of diodes increases cost and reduces the linear performance of the interface in DP mode. Therefore, the conventional multi-protocol interface cannot maintain linearity over a wide output range and cannot satisfy V_OFFCompliance testing.

Disclosure of Invention

Various implementations of the present technology may provide methods and apparatus for an output buffer. The output buffer is configured to execute in a DP mode and an HDMI mode, and to satisfy certain compliance conditions in an HDMI compliance test mode. The output buffer comprises a plurality of transistors and resistors arranged to operate in DP mode and HDMI mode. The plurality of transistors and resistors are arranged to reduce leakage current during the HDMI compliance test mode.

The technical problem solved by the invention is that the conventional multi-protocol interface uses external and/or internal diodes to satisfy V_OFFCompliance testing, which increases cost and reduces the linear performance of the interface in DP mode.

According to one aspect, an output buffer comprises: an output pad; a plurality of transistors, wherein each transistor includes a source terminal, a drain terminal, a gate terminal, and a body terminal, the plurality of transistors comprising: a first transistor connected in parallel with the second transistor; wherein the first transistor and the second transistor are connected to a supply voltage and a bulk potential; and wherein the first resistor is connected to the body potential and to the source terminal of the first transistor; a third transistor connected between the first transistor and the second transistor; wherein the third transistor is also connected to a body potential and is responsive to the first control signal; and a fourth transistor that: connected in series with a second resistor; and connected to the output pad; wherein the second resistor is connected between the gate terminal of the first transistor and the supply voltage.

In one embodiment, a body terminal of the fourth transistor is connected to a body potential.

In one implementation, each of the first transistor, the second transistor, the third transistor, and the fourth transistor includes a p-channel transistor.

In one embodiment, the output buffer further comprises a fifth transistor from the plurality of transistors, the fifth transistor connected in series with the second resistor and responsive to the second control signal, wherein the fifth transistor comprises an n-channel transistor.

In one embodiment, the output buffer further includes a termination resistor directly connected between the output pad and the first transistor.

In one embodiment, the output buffer further includes a sixth transistor connected in parallel with the third transistor and connected to the bulk potential.

According to another aspect, a method for operating a multimodal output buffer connected between a host device and a receiving device includes: operating an output buffer in a first mode, comprising: turning on a first plurality of transistors, wherein the first plurality of transistors includes: a first p-channel transistor connected to a supply voltage, a body potential and to an output pad via a termination resistor; and a first n-channel transistor connected to the gate terminal of the first p-channel transistor; and turning off a second plurality of transistors, wherein the second plurality of transistors includes: a second p-channel transistor connected between the gate terminal of the first p-channel transistor and the output pad; and a third p-channel transistor connected to the drain terminal of the first p-channel transistor and to the bulk potential; operating the output buffer in a second mode, comprising: turning on the third p-channel transistor; and turning off the first p-channel transistor, the first n-channel transistor, and the second p-channel transistor; and operating the output buffer in a test mode, comprising: turning on the third p-channel transistor and the second p-channel transistor; and turning off the first p-channel transistor and the first n-channel transistor.

In one embodiment, operating the output buffer in the test mode further comprises turning off the host device when the receiving device is turned on.

In one embodiment, the method further comprises preventing leakage across the output pad during the test mode by providing: a first resistor in series with a second p-channel transistor; and a second resistor connected to the body potential and to the source terminal of the first p-channel transistor.

In one embodiment, the first mode is a displayport mode and the second mode is a high definition multimedia interface mode.

The technical effect achieved by the present invention is to provide a multimodal interface with an output buffer that can maintain linearity and satisfy V over a wide output range_OFFCompliance testing is performed without significantly increasing the cost of the circuit.

Drawings

The present technology may be more fully understood with reference to the detailed description when considered in conjunction with the following exemplary figures. In the following drawings, like elements and steps in the various drawings are referred to by like reference numerals throughout.

FIG. 1 is a block diagram of a system in accordance with an exemplary embodiment of the present technique;

FIG. 2 is a block diagram of an interaction device, in accordance with exemplary embodiments of the present technique;

FIG. 3 is a circuit diagram of a differential output buffer in accordance with embodiments of the present technique;

FIG. 4 is an alternative simplified circuit diagram of a differential output buffer in accordance with the present technique;

FIG. 5 is a simplified circuit diagram of a differential output buffer showing a port mode in accordance with an embodiment of the present technique;

FIG. 6 is a simplified circuit diagram of a differential output buffer for HDMI mode in accordance with embodiments of the present technique; and is

Fig. 7 is a simplified circuit diagram of a differential output buffer during an HDMI compliance test mode in accordance with an embodiment of the present technology.

Detailed Description

The present techniques may be described in terms of functional block components and various processing steps. Such functional blocks may be realized by any number of components configured to perform the specified functions and achieve the various results. For example, the present technology may employ various transistors, resistive elements, capacitors, and the like, which may perform various functions. Further, the present techniques may be implemented in connection with any number of electronic systems (such as automotive, aerospace, "smart devices," portable devices, and consumer electronics), and the systems described are merely exemplary applications of the present techniques.

The methods and apparatus for an output buffer in accordance with various aspects of the present technique may operate in conjunction with any suitable communication system. For example, and referring to fig. 1, an exemplary system 100 may include a host device 105 (i.e., a source device), interface circuitry 110, and a receiving device 115 (e.g., a computer monitor or display screen). In various applications, the system 100 may be powered by a battery (not shown).

According to an example embodiment, the host device 105 and the interface circuit 110 may be connected by transmission lines (such as the first transmission line 120 and the second transmission line 125) and coupling capacitors (such as the coupling capacitors C1, C2). Further, the interface circuit 110 and the receiving device 115 may be connected by transmission lines (such as the third transmission line 130 and the fourth transmission line 135) and coupling capacitors (such as the coupling capacitors C3, C4). Thus, the host device 105 and the reception device 115 are connected to each other via the interface circuit 110.

Transmission lines

120, 125, 130, 135 may include any suitable communication lines, buses, links, wires, cables, etc. for transmitting data.

The interface circuit 110 may provide high speed communication (data transfer) at various voltages across the channel, such as at high and low voltages. In one embodiment, interface circuitry 110 may be configured to perform data rates of 5Gbps (gigabits per second), 8.1Gbps, and 10Gbps at 1.8 volts and 3.3 volts. In other embodiments, the interface circuit 110 may be configured to perform at any desired supply voltage level and at any data rate. In addition, interface circuit 110 is capable of operating in accordance with the USB 3.1 SuperSpeed Plus protocol, for example, to perform related transmission and reception compliance tests at 10 Gbps. According to an example embodiment, the interface circuit 110 may be implemented as a linear signal repeater for multi-protocol applications, such as USB, HDMI (high definition multimedia interface), and/or DisplayPort.

In various embodiments, the interface circuit 110 may be configured as a unidirectional channel or a bidirectional channel. For example, the interface circuitry 110 may transmit data in one direction (e.g., from the host device 105 to the receive device 115), or may transmit data in two directions (e.g., from the host device 105 to the receive device 115 and from the receive device 115 to the host device 105). The interface circuit 110 may have any desired architecture, such as a differential architecture or a single-ended architecture.

In an exemplary embodiment, and referring to fig. 1 and 2, the interface circuit 110 may include a pair of input pads, such as a first input pad 220 and a second input pad 225. Further, the output terminals of the interface circuit 110 may include a pair of output pads, such as a third output pad 230 and a fourth output pad 235. The pair of input pads may be used to connect the host device 105 to the interface circuit 110, and the pair of output pads may be used to connect the interface circuit 110 to the receiving device 115. For example, the pair of

input pads

220, 225 may be connected to the first transmission line 120 and the second transmission line 125, respectively, and the pair of

output pads

230, 235 may be connected to the third transmission line 130 and the fourth transmission line 135, respectively.

The interface circuit 110 may be configured to regenerate signals to improve the quality of input signals transmitted from the host device 105 to the receiving device 115. The interface circuit 110 may also be configured to adjust and correct for known channel loss and restore signal integrity. For example, the interface circuit 110 may include a receiver 200 connected to an output buffer 205.

Receiver 200 may be configured to amplify, compensate for channel loss, and/or apply a desired gain to an input signal, such as an input signal from host device 105. According to an example embodiment, the input terminals of the receiver 200 may be connected to the pair of

input pads

220, 225, and the output terminals of the receiver 200 may be connected to the pair of

output pads

230, 235 via the output buffer 205.

Receiver 200 may include any circuitry and/or system suitable for providing a desired signaling and/or operating specification. For example, receiver 200 may include any number of circuits and/or devices that operate in conjunction with one another to adjust the gain of an input signal, equalize the input signal, and drive the input signal.

According to an example embodiment, the receiver 200 may be configured to perform a gain function and equalize an input signal. For example, the receiver 200 may include a gain circuit 240, an equalizer circuit 245, and a pre-driver circuit 250 connected in series with each other. In one embodiment, equalizer circuit 245 may follow gain circuit 240 and predriver circuit 250 may follow equalizer circuit 245. Thus, the gain circuit 240 may be directly connected to the pair of

input pads

220, 225, and the predriver circuit 250 may be directly connected to the output buffer 205.

In one embodiment, gain circuit 240 may include an amplifier having an adjustable gain, equalizer circuit 245 may include a continuous-time linear equalizer, and predriver circuit 250 may include a second equalizer.

The output buffer 205 may be configured to provide a final power amplification stage to drive a load (e.g., the receiving device 115). According to an example embodiment, the input terminal of the output buffer 205 may be directly connected to the output terminal of the receiver 200. Further, the output terminals of the output buffer 205 may be directly connected to the pair of

output pads

230, 235.

According to one embodiment, and referring to fig. 3, the output buffer 205 may be configured to execute in a Displayport (DP) mode and a High Definition Multimedia Interface (HDMI) mode, and to satisfy certain compliance conditions in the HDMI compliance testing mode. According to an example embodiment, the output buffer 205 may have a differential architecture.

The output buffer 205 may include a plurality of transistors and resistors arranged to operate in DP mode and HDMI mode, as well as to reduce leakage current during HDMI compliance test mode. For example, the output buffer 205 may include a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, and a seventh transistor M7. The output buffer 205 may further include a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4. The second resistor R2 and the third resistor R3 may be referred to as termination resistors.

The first transistor M1 may include a p-channel transistor including a source terminal, a gate terminal, a drain terminal, and a bulk terminal. The source terminal of the first transistor M1 may be connected to a supply voltage V_DD(e.g., 3.3V), and the drain terminal may be connected to the first output pad 230 via a second resistor R2. The bulk terminal may be connected to a bulk potential B. In an exemplary embodiment, the first resistor R1 may be connected to the body potential B and the source terminal of the first transistor M1.

Similarly, the second transistor M2 may mirror the first transistor in both type and arrangement, with a third resistor R3 connected between the second output pad 235 and the terminal of the second transistor M2.

The seventh transistor M7 may include a p-channel transistor including a source terminal, a gate terminal, a drain terminal, and a bulk terminal. The seventh transistor M7 may be connected between the first transistor M1 and the second transistor M2, wherein a source terminal and a drain terminal of the seventh transistor M7 are connected to drain terminals of the first transistor M1 and the second transistor M2. A gate terminal of the seventh transistor M7 may be configured to receive the first control signal C1, wherein the first control signal C1 may be used to turn on/off the seventh transistor M7 based on a desired operating mode. The body terminal of the seventh transistor M7 may be connected to the body potential B together with the first transistor M1 and the second transistor M2.

The third transistor M3 may include a p-channel transistor including a source terminal, a gate terminal, a drain terminal, and a bulk terminal. The source terminal of the third transistor M3 may be connected to the gate terminal of the first transistor M1, the drain terminal may be connected to the first output pad 230, and the gate terminal may be connected to the supply voltage V_DDAnd the bulk terminal may be connected to the bulk potential B.

Similarly, the fourth transistor M4 may mirror the third transistor M3 in both type and arrangement with respect to the second transistor M2.

According to various embodiments, the third transistor M3 and the fourth transistor M4 may be implemented using Bipolar Junction Transistors (BJTs), metal-oxide-silicon (MOS) transistors, or a series combination of passive components and active transistors.

The fifth transistor M5 may include an n-channel transistor including a source terminal, a gate terminal, and a drain terminal. A drain terminal of the fifth transistor M5 may be connected to the gate terminal of the first transistor M1, the source terminal of the third transistor. The drain terminal may also be connected to the supply voltage V via a fourth resistor R4_DD. In other words, the first transistor M1, the third transistor M3, the fifth transistor M5, and the fourth resistor R4 may be connected to each other at a common node. A gate terminal of the fifth transistor M5 may be configured to receive the second control signal C2, wherein the second control signal C2 may be used to turn on/off the fifth transistor M5 based on a desired operating mode.

Similarly, the sixth transistor M6 may mirror the fifth transistor M5 in both type and arrangement with respect to the second transistor M2 and the fourth transistor M4. In addition, the sixth transistor M6 may be controlled according to the second control signal C2.

According to various embodiments, the resistors R1, R4, and R5 may be implemented as resistors in series with active transistors (e.g., BJTs, MOS, or combinations thereof).

The output buffer 205 may further comprise a first input transistor 300 for receiving a first input signal IN from the receiver 200, and a second input transistor 305 for receiving a second input signal INb from the receiver 200. The first input transistor may be connected at a first terminal to the second resistor R2, and the second input transistor 305 may be connected at a first terminal to the third resistor R3. Both the first input transistor 300 and the second input transistor 305 may also be connected to a current source 310 via respective second terminals. The first input transistor 300 and the second input transistor 305 may comprise bipolar junction transistors or any other suitable transistor type.

According to another embodiment, and referring to fig. 4, the output buffer 205 may be configured to provide programmability by changing the resistance at the

output pads

230, 235. For example, the output buffer 205 may further include one or more transistors connected in parallel with the seventh transistor M7, such as an eighth transistor M8. The eighth transistor M8 may have the same type and arrangement as the seventh transistor M7. For example, the eighth transistor M8 may include a p-channel transistor, and may be connected to the first and second transistors M1 and M2 and the bulk potential. The eighth transistor M8 may be controlled according to a third control signal C4, where the third control signal C3 may be used to turn on/off the eighth transistor M8 based on the resistance at the

output pads

230, 235. A resistor may be connected in series with the eighth transistor M8 to provide a resistance different from that of the seventh resistor M7.

In operation, and referring to fig. 1 and 5-7, the output buffer 205 may operate in one of three modes according to the first control signal C1 and the second control signal C2: DP mode, HDMI mode, and HDMI compliance test mode.

During DP mode, interface circuit 110 may AC couple with host device 105 and receiving device 115 to transmit audio and/or video data from host device 105 to receiving device 115. The system 100 may selectively activate the output buffer 205 to execute in DP mode. For example, the system 100 may assert the second control signal C2 to turn on the fifth transistor M5 and the sixth transistor M6, thereby turning on the first transistor M1 and the second transistor M2. The first control signal C1 is deasserted to turn off the seventh transistor M7. The third transistor M3 and the fourth transistor M4 are also turned off during the DP modeOff because their respective gates are connected to the supply voltage V_DD。

During HDMI mode, the interface circuit 110 may DC couple with the host device 105 and the sink device 115 to transmit audio and/or video data from the host device 105 to the sink device 115. During HDMI mode, the host device 105 may be off, while the sink device 115 may be on. To preserve battery life, it may be desirable to prevent or otherwise reduce leakage current in the output buffer 205 during HDMI mode.

The system 100 may selectively activate the output buffer 205 to execute in HDMI mode. For example, the system 100 may assert the first control signal C1 to turn on the seventh transistor M7 and deassert the second control signal C2 to turn off the fifth transistor M5 and the sixth transistor M6. Accordingly, the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 are also turned off during the HDMI mode.

In other embodiments, the third control signal C3 may be asserted to turn on the eighth transistor M8, thereby changing the resistance at the

output pads

230, 235.

During the HDMI compliance test mode, the interface circuit 110 may be DC coupled to the host device 105 and the sink device 115 with a supply voltage V_DDCan be set at zero volts to 3.3V (i.e., V)_DD0V to 3.3V), the first control signal C1 is asserted to turn on the seventh transistor M7, and the second control signal C2 is de-asserted to turn off the fifth transistor M5 and the sixth transistor M6. Therefore, the first transistor M1 and the second transistor M2 are also turned off. Supply voltage V_DDMay be set according to system specifications, desired operating specifications, etc.

In the foregoing description, the technology has been described with reference to specific exemplary embodiments. The particular embodiments shown and described are illustrative of the technology and its best mode and are not intended to otherwise limit the scope of the technology in any way. Indeed, for the sake of brevity, conventional manufacturing, connecting, fabrication, and other functional aspects of the methods and systems may not be described in detail. Furthermore, the connecting lines shown in the various figures are intended to represent example functional relationships and/or steps between the various elements. There may be many alternative or additional functional relationships or physical connections in a practical system.

The described techniques have been described with reference to specific exemplary embodiments. However, various modifications and changes may be made without departing from the scope of the present technology. The specification and figures are to be regarded in an illustrative rather than a restrictive manner, and all such modifications are intended to be included within the scope of present technology. Accordingly, the scope of the described technology should be determined by the general embodiments described and their legal equivalents, rather than by merely the specific examples described above. For example, the steps recited in any method or process embodiment may be performed in any order, unless explicitly stated otherwise, and are not limited to the exact order provided in the specific examples. Additionally, the components and/or elements recited in any apparatus embodiment may be assembled or otherwise operationally configured in a variety of permutations to produce substantially the same result as the present technique and are therefore not limited to the specific configuration set forth in the specific example.

Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, any benefit, advantage, solution to problem or any element that may cause any particular benefit, advantage, or solution to occur or to become more pronounced are not to be construed as a critical, required, or essential feature or element.

The terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, composition, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, composition, or apparatus. Other combinations and/or modifications of the above-described structures, arrangements, applications, proportions, elements, materials or components used in the practice of the present technology, in addition to those not specifically recited, may be varied or otherwise particularly adapted to specific environments, manufacturing specifications, design parameters or other operating requirements without departing from the general principles thereof.

The present technology has been described above in connection with exemplary embodiments. However, changes and modifications may be made to the exemplary embodiments without departing from the scope of the present techniques. These and other changes or modifications are intended to be included within the scope of the present technology, as set forth in the following claims.

According to a first aspect, an output buffer comprises: an output pad; a plurality of transistors, wherein each transistor includes a source terminal, a drain terminal, a gate terminal, and a body terminal, the plurality of transistors comprising: a first transistor connected in parallel with the second transistor; wherein the first transistor and the second transistor are connected to a supply voltage and a bulk potential; and wherein the first resistor is connected to the body potential and to the source terminal of the first transistor; a third transistor connected between the first transistor and the second transistor; wherein the third transistor is also connected to a body potential and is responsive to the first control signal; and a fourth transistor that: connected in series with a second resistor; and connected to the output pad; wherein the second resistor is connected between the gate terminal of the first transistor and the supply voltage.

In one embodiment, the output buffer further includes a fifth transistor from the plurality of transistors, the fifth transistor connected in series with the second resistor and responsive to the second control signal.

In one embodiment, the fifth transistor includes an n-channel transistor.

According to a second aspect, a method for operating a multimodal output buffer connected between a host device and a receiving device comprises: operating an output buffer in a first mode, comprising: turning on a first plurality of transistors, wherein the first plurality of transistors includes: a first p-channel transistor connected to a supply voltage, a body potential, and an output pad via a termination resistor; and a first n-channel transistor connected to the gate terminal of the first p-channel transistor; and turning off a second plurality of transistors, wherein the second plurality of transistors includes: a second p-channel transistor connected between the gate terminal of the first p-channel transistor and the output pad; and a third p-channel transistor connected to the drain terminal of the first p-channel transistor and the bulk potential; operating the output buffer in a second mode, comprising: turning on the third p-channel transistor; and turning off the first p-channel transistor, the first n-channel transistor, and the second p-channel transistor; and operating the output buffer in a test mode, comprising: turning on the third p-channel transistor and the second p-channel transistor; and turning off the first p-channel transistor and the first n-channel transistor.

In one embodiment, the method further includes measuring a voltage at the output pad during the test mode.

In one embodiment, the method further comprises preventing leakage across the output pad during the test mode by providing a first resistor in series with a second p-channel transistor.

In one embodiment, the method further comprises preventing leakage current across the output pad during the test mode by providing a second resistor connected to a body potential and a source terminal of the first p-channel transistor.

According to a third aspect, a system comprises: a host device connected to a receiving device via an interface, wherein the interface is configured to operate in a first mode and a second mode and comprises: a receiver connected in series with an output buffer, wherein the output buffer is connected to a receiving device via an output pad and comprises: a plurality of transistors, wherein each transistor includes a gate terminal, a drain terminal, a source terminal, and a body terminal; and wherein at least a first and a second p-channel transistor from the plurality of transistors are connected to a common bulk potential via respective bulk terminals; a first resistor connected to a body terminal of the first p-channel transistor and a source terminal of the first p-channel transistor; a third p-channel transistor from the plurality of transistors, the third p-channel transistor connected to the output pad and to the gate terminal of the first p-channel transistor; a second resistor connected to: a source terminal of a third p-channel transistor; and a gate terminal of the first p-channel transistor.

In one embodiment, the first p-channel transistor and the second p-channel transistor are connected to a supply voltage via respective source terminals.

In one embodiment, a gate terminal of the second p-channel transistor is configured to receive the first control signal.

In one embodiment, the system further includes a first n-channel transistor configured to operate according to a second control signal and connected in series with a second resistor.

In one embodiment, the system further includes a termination resistor directly connected between the output pad and the first p-channel transistor.

In one embodiment, a body terminal of the third p-channel transistor is connected to a body potential.

In one embodiment, the system further comprises a fourth p-channel transistor connected in series with the resistor and in parallel with the second p-channel transistor and connected to a common body potential.

Claims

1. An output buffer, comprising:

an output pad;

a plurality of transistors, wherein each transistor includes a source terminal, a drain terminal, a gate terminal, and a body terminal, the plurality of transistors comprising:

a first transistor connected in parallel with the second transistor; wherein the first transistor and the second transistor are connected to a supply voltage and a bulk potential; and is

Wherein a first resistor is connected to the body potential and the source terminal of the first transistor;

a third transistor connected between the first transistor and the second transistor; wherein the third transistor is also connected to the bulk potential and is responsive to a first control signal; and

a fourth transistor that:

connected in series with a second resistor; and is

Connected to the output pad;

wherein the second resistor is connected between the gate terminal of the first transistor and the supply voltage.

2. The output buffer of claim 1, wherein the bulk terminal of the fourth transistor is connected to the bulk potential.

3. The output buffer of claim 1, wherein each of the first transistor, the second transistor, the third transistor, and the fourth transistor comprises a p-channel transistor.

4. The output buffer of claim 1, further characterized by comprising a fifth transistor from the plurality of transistors, the fifth transistor connected in series with the second resistor and responsive to a second control signal, wherein the fifth transistor comprises an n-channel transistor.

5. The output buffer of claim 1, further characterized by comprising a termination resistor directly connected between the output pad and the first transistor.

6. The output buffer of claim 1, further characterized by comprising a sixth transistor connected in parallel with the third transistor and connected to the bulk potential.

7. A method for operating a multimodal output buffer connected between a host device and a receiving device, the method comprising:

operating the output buffer in a first mode, comprising:

turning on a first plurality of transistors, wherein the first plurality of transistors comprises:

a first p-channel transistor connected to a supply voltage, a body potential, and to an output pad via a termination resistor; and

a first n-channel transistor connected to a gate terminal of the first p-channel transistor; and

turning off a second plurality of transistors, wherein the second plurality of transistors comprises:

a second p-channel transistor connected between the gate terminal of the first p-channel transistor and the output pad; and

a third p-channel transistor connected to the drain terminal of the first p-channel transistor and the bulk potential;

operating the output buffer in a second mode, comprising:

turning on the third p-channel transistor; and

turning off the first p-channel transistor, the first n-channel transistor, and the second p-channel transistor; and

operating the output buffer in a test mode, comprising:

turning on the third p-channel transistor and the second p-channel transistor; and

turning off the first p-channel transistor and the first n-channel transistor.

8. The method of claim 7, wherein operating the output buffer in the test mode further comprises: turning off the host device when the receiving device is turned on.

9. The method of claim 7, further characterized by comprising preventing leakage across the output pad during the test mode by providing:

a first resistor in series with the second p-channel transistor; and

a second resistor connected to the body potential and a source terminal of the first p-channel transistor.

10. The method of claim 7, wherein the first mode is a displayport mode and the second mode is a high definition multimedia interface mode.