CN112241375B - Memory allocation method and device and terminal equipment - Google Patents
Memory allocation method and device and terminal equipment Download PDFInfo
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Abstract
The embodiment of the invention discloses a memory allocation method, a memory allocation device and terminal equipment, which are applied to the technical field of communication and can solve the problem that the memory space in a memory is not reasonably utilized and the memory space is wasted in the prior art. The method comprises the following steps: dividing R carriers into K carrier groups according to the number of soft bits corresponding to the maximum transmission block in the allocated R carriers, and determining to divide a memory into K storage areas corresponding to the K carrier groups; determining to divide each storage area of the K storage areas into M sub-storage areas according to the total available space of the memory; wherein R and K are integers greater than or equal to 2, and M is an integer greater than or equal to 1.
Description
Technical Field
The embodiment of the invention relates to the technical field of communication, in particular to a memory allocation method, a memory allocation device and terminal equipment.
Background
Hybrid automatic repeat request (hybrid automatic repeat request, HARQ) retransmission mechanism with soft combining in the modem chip of the terminal device is a key technology for improving the demodulation performance of the terminal. By using HARQ retransmission with soft combining, the terminal device stores the data which is received from the base station and cannot be decoded correctly in the HARQ buffer memory, and performs soft combining and decoding with the data received by retransmission, and the combined data has more reliable decoding performance compared with the data of single transmission. The data volume needed to be stored for realizing the HARQ retransmission and soft combining mechanism is related to the number of carriers, the number of HARQ processes and the size of a transmission block which are distributed to the terminal equipment by the base station, and the size of each soft bit. At present, an HARQ memory on a terminal device chip allocates a buffer memory area for each carrier, firstly divides the memory into different areas according to the difference of the maximum transmission block size supported by each carrier, and then allocates sub-blocks for each area according to the maximum HARQ process number supported by each carrier, wherein the number of the sub-blocks is the maximum HARQ process number or the maximum transmission block number supported by the corresponding carrier.
However, at present, according to the maximum number of HARQ processes supported by each carrier, an HARQ memory is allocated, and on the one hand, under the condition that the memory space of the HARQ memory is limited, the memory area cannot be allocated for each carrier; on the other hand, most of the HARQ memories are in idle state in most of the time, so that the existing memory partitioning method does not reasonably utilize the storage space of the memories, and the storage space is wasted.
Disclosure of Invention
The embodiment of the invention provides a memory allocation method, a memory allocation device and terminal equipment, which are used for solving the problem that the memory is wasted because the memory space in the memory is not reasonably utilized in the prior art.
In order to solve the technical problems, the embodiment of the invention is realized as follows:
in a first aspect, there is provided a method of allocating memory, the method comprising: dividing R carriers into K carrier groups according to the number of soft bits corresponding to the maximum transmission block in the allocated R carriers, and determining to divide a memory into K storage areas corresponding to the K carrier groups;
determining to divide each storage area of the K storage areas into M sub-storage areas according to the total available space of the memory;
Wherein R and K are integers greater than or equal to 2, and M is an integer greater than or equal to 1.
In a second aspect, there is provided an apparatus for allocating memory, the apparatus comprising: the processing module is used for dividing the R carriers into K carrier groups according to the number of soft bits corresponding to the maximum transmission block in the allocated R carriers, and determining to divide a memory into K storage areas corresponding to the K carrier groups;
determining to divide each storage area of the K storage areas into M sub-storage areas according to the total available space of the memory;
wherein R and K are integers greater than or equal to 2, and M is an integer greater than or equal to 1.
In a third aspect, there is provided a terminal device, the processor, the memory and a computer program stored on the memory and executable on the processor, the computer program implementing the memory allocation method as in the first aspect when being executed by the processor.
In a fourth aspect, a computer-readable storage medium is provided, on which a computer program is stored, which computer program, when being executed by a processor, implements the method of allocating a transmission memory as in the first aspect.
In the embodiment of the invention, R carriers are divided into K carrier groups according to the number of soft bits corresponding to the maximum transmission block of the allocated R carriers, and a memory is determined to be divided into K memory areas corresponding to the K carrier groups; determining to divide each storage area of the K storage areas into M sub-storage areas according to the total available space of the memory; wherein R and K are integers greater than or equal to 2, and M is an integer greater than or equal to 1. According to the scheme, K storage areas can be divided for K carrier groups in R carriers according to the soft bit number corresponding to the maximum transmission block of the carriers, each storage area in the K storage areas is divided into the designated M sub-storage areas based on the total available space of the memory, compared with the storage area allocated for the carriers according to the maximum HARQ process number, the storage area can be allocated for each carrier, and the situation that a large number of storage areas are free due to the fact that more storage areas are allocated for a certain carrier is avoided, therefore the storage space in the memory is reasonably utilized, and the waste of the storage space is avoided.
Drawings
Fig. 1 is a schematic diagram of one possible allocation of HARQ buffer memory according to an embodiment of the present invention;
FIG. 2 is a graph showing the performance of various compression ratios provided by embodiments of the present invention in the case of initial transmission and retransmission;
fig. 3 is a schematic diagram of a probability curve that when the BLER is 10%, the number of HARQ processes supported by each carrier is 16, and the number of HARQ processes occupying the HARQ buffer is greater than N;
FIG. 4 is a schematic diagram showing a method for allocating memory according to an embodiment of the present invention;
FIG. 5 is a second schematic diagram of a memory allocation method according to an embodiment of the present invention;
fig. 6 is a second schematic diagram of allocation of a possible HARQ buffer according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a memory allocation device according to an embodiment of the present invention;
fig. 8 is a schematic hardware structure of a terminal device according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that, in the embodiments of the present invention, words such as "exemplary" or "such as" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "e.g." in an embodiment should not be taken as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion.
First, the related technical content of the embodiment of the present invention will be described:
the memory in the embodiment of the present invention may be a buffer memory, and optionally, the buffer memory may be an HARQ buffer memory.
For terminal equipment in a New Radio (NR) system, and terminal equipment in a long term evolution (long term evolution, LTE) system, a HARQ retransmission mechanism with soft combining in a modem chip of the terminal equipment is a key technology for improving demodulation performance of the terminal equipment. By using HARQ retransmission with soft combining, the terminal device can store the data received from the base station in the multicarrier mobile communication network, which cannot be decoded correctly, in the HARQ buffer memory, and soft combine and decode the data received by the retransmission, so that the combined data has more reliable decoding performance than the data transmitted once.
When implementing the HARQ retransmission and soft combining mechanism, the data amount stored in the HARQ buffer memory is related to the number of carriers allocated to the terminal device by the network, the number of HARQ processes allocated to the terminal device, the size of a transport block allocated to the terminal device (i.e., the number of soft bits supported by the transport block), and the size of each soft bit (i.e., the number of bits supported by the soft bits).
One possible HARQ buffer allocation method is to semi-statically allocate a buffer memory area to each carrier. When the number of carriers allocated to the terminal device by the network changes the configuration of the carriers, the following steps are adopted to partition:
step 1: the memory is divided into different regions according to the difference in the maximum transport block size supported by each carrier.
Step 2: and allocating a sub-storage area for each area according to the maximum HARQ process number and the maximum transmission block number supported by each carrier.
The number of the sub-storage areas is the maximum HARQ process number or the maximum transmission block number supported by the corresponding carrier, and the size of the sub-storage areas is the maximum transmission block size supported by each process of the corresponding carrier.
In the embodiment of the invention, the memory allocation method can be applied to various systems. Alternatively, the method can be applied to an LTE system, an NR system or an LTE-NR dual connection system.
For the scenario applied in the LTE-NR dual connectivity system, the HARQ buffer memory will be partitioned as follows:
1. because the maximum transport block sizes supported by all the LTE carriers are the same, all the LTE carriers are divided into a storage area;
2. because of the difference in carrier bandwidths of different NRs, the maximum transport block sizes supported by the carriers will also be different, NR carriers with the same maximum transport block size will be divided into one region, and NR carriers of different maximum transport block sizes will be divided into different regions.
Illustratively, assuming that there are N NR carriers of different maximum transport block sizes, the NR carriers will correspond to N storage areas Di, where i=0, 1, …, N-1.
Table 1 shows a HARQ partition parameter obtained according to one possible HARQ buffer memory allocation method described above.
TABLE 1
Fig. 1 is a schematic diagram of the allocation of the HARQ buffer after the allocation according to the above possible allocation method of the HARQ buffer.
The above-mentioned HARQ memory allocation method has the problems:
1) Allocating HARQ buffers according to the maximum number of HARQ processes supported per carrier may take up a very large memory space. Under the condition that the on-chip HARQ storage space is limited, the maximum HARQ process number cannot be allocated for each carrier, and most of the HARQ buffer storage area cannot be occupied in most of the time, so that the storage space is wasted.
For example, fig. 2 is a probability curve that when the Block error rate (BLER) is 10% (i.e., pre=1 in fig. 2), the number of HARQ processes supported by each carrier is 16 (i.e., nharq=16 in fig. 2), and the number of HARQ processes occupying the HARQ buffer is greater than N (prob (# buffered proc > N), it can be seen from fig. 2 that when the number of carriers is 8, the total number of HARQ processes is 128, but the probability that the number of HARQ processes occupying the HARQ buffer is greater than 24 is not more than one thousandth, so that it is not necessary to allocate HARQ memory space for each carrier by the maximum number of HARQ processes, for example, if only 24 HARQ processes are allocated to a total of 8 carriers, and all processes of 8 carriers share the 24 HARQ processes, where nCC represents the number of carriers, for example, ncc=8 represents 8 carriers.
2) The number of bits contained in the soft bits of all the transmission blocks is the same, that is, all the soft bits adopt the same compression ratio, so that the LTE main carrier and the NR main carrier can transmit signaling information, and compared with the auxiliary carrier, the LTE main carrier has higher requirements on the reliability of data, and if the same compression ratio is adopted for the main carrier, certain performance influence is caused on the data transmission reliability of the main carrier.
Fig. 3 is a graph showing performance curves for different compression ratios in the case of initial transmission and retransmission. In fig. 3, the abscissa indicates the signal-to-noise ratio (SNR), and the ordinate indicates the block error rate (BLER), it can be seen that 3-bit vector compression (i.e., the compression ratio is 3, denoted as no comp in fig. 3) and no bit compression (denoted as no comp in fig. 3) approach each other during the first retransmission and the second retransmission, and that 2-bit vector compression (i.e., the compression ratio is 2, denoted as 2-bit SQ in fig. 3) causes a performance degradation of about 0.5dB, and 1.1-bit vector compression (i.e., the compression ratio is 1.1, denoted as 1.1-bit SQ in fig. 3) causes a performance loss exceeding 1 dB. Wherein initTX in fig. 3 represents an initial transmission, 1st reTx represents a primary transmission, and 2nd reTx represents a secondary retransmission.
As shown in fig. 4, an embodiment of the present invention provides a method for allocating a memory, including:
401. and dividing the R carriers into K carrier groups according to the soft bit number corresponding to the maximum transmission block in the allocated R carriers.
In the embodiment of the invention, the carriers with the same soft bit number corresponding to the maximum transmission block can be divided into the same carrier group, and the carriers with different soft bit numbers corresponding to the maximum transmission block can be divided into different carrier groups.
For example, taking application in an LTE-NR dual connectivity system as an example, it is assumed that carriers allocated by a base station to a terminal device include 1 LTE primary carrier, 3 LTE secondary carriers, 1 NR primary carrier, and 2 NR secondary carriers, and soft bits supported by the 1 LTE primary carrier and the 3 LTE secondary carriers are all E, the number of soft bits supported by the 1 NR primary carrier is a, and the number of soft bits supported by the 2 NR secondary carriers is B, C, D. If the carriers are divided according to the number of soft bits corresponding to the maximum transport block, it may be determined that 1 LTE primary carrier and 3 LTE secondary carriers are divided in carrier group 1,1 NR primary carrier is divided in carrier group 2,1 NR primary carrier is divided in carrier group 3, a first secondary carrier of 2 NR secondary carriers is divided in carrier group 4, and a second secondary carrier of 2 NR secondary carriers is divided in carrier group 5. So that 7 carriers can be divided into 5 carrier groups.
Alternatively, the R carriers may be divided into K carrier groups according to the number of soft bits corresponding to the maximum transport block of the allocated R carriers and carrier types of the R carriers.
Optionally, dividing the R carriers into K carrier groups according to the number of soft bits corresponding to the maximum transport block in the allocated R carriers and carrier types of the R carriers, including:
Determining the number of soft bits corresponding to the maximum transmission block of each carrier;
and dividing the carriers which have the same soft bit number and belong to the same carrier type into the same carrier group to obtain K carrier groups.
Alternatively, for an LTE-NR dual connectivity system, the carrier types may include: LTE primary carrier, LTE secondary carrier, NR primary carrier and NR secondary carrier.
Optionally, for the LTE system, the carrier types may include: LTE primary carrier, LTE secondary carrier.
Optionally, for the LTE system, the carrier types may include: an NR primary carrier and an NR secondary carrier.
For example, in the LTE-NR dual connectivity system, it is assumed that carriers allocated by a base station to a terminal device include 1 LTE primary carrier, 3 LTE secondary carriers, 1 NR primary carrier, and 2 NR secondary carriers, and soft bits supported by the 1 LTE primary carrier and the 3 LTE secondary carriers are all E, the number of soft bits supported by the 1 NR primary carrier is a, and the number of soft bits supported by the 2 NR secondary carriers is B, C, D. If the carriers are divided according to the number of soft bits corresponding to the maximum transport block and the carrier type, it may be determined that 1 LTE primary carrier is divided in carrier group 1, 3 LTE secondary carriers are divided in carrier group 2,1 NR primary carrier is divided in carrier group 3,1 NR primary carrier is divided in carrier group 4, a first secondary carrier of 2 NR secondary carriers is divided in carrier group 5, and a second secondary carrier of 2 NR secondary carriers is divided in carrier group 6. So that 7 carriers can be divided into 6 carrier groups.
402. It is determined to divide the memory into K memory areas corresponding to K carrier groups.
In the embodiment of the present invention, a corresponding storage area may be allocated to each carrier group of the K carrier groups.
403. Dividing each of the K memory areas into M sub-memory areas is determined based on the total available space of the memory.
Wherein R and K are integers greater than or equal to 2, and M is an integer greater than or equal to 1.
Optionally, the method for determining that each storage area of the K storage areas is divided into M sub-storage areas according to the total available space of the memory includes:
403a, determining the total available space of the memory.
403b, calculating the bit number of the sub-storage area in each storage area according to the number of soft bits supported by the maximum transport block of the carrier corresponding to each storage area and the bit number corresponding to each soft bit.
403c, according to the total available space of the memory, combining the bit number of the sub-memory areas in each memory area, and calculating to obtain the number M of the sub-memory areas in each memory area.
Optionally, according to the total available space of the memory, the number M of sub-memory areas in each memory area is calculated by combining the number of bits in the sub-memory areas in each memory area, including:
According to the total available space of the memory, the number M of the sub-memory areas of each memory area is calculated by combining the following formula I;
the first formula is:m represents the number of sub-storage areas of each storage area, K represents the number of storage areas, T represents the total available space of the storage, S i Indicating the number of bits included in the i-th sub-storage area.
403d, determining to divide each of the K memory areas into M sub-memory areas.
Alternatively, after determining the number M of sub-memory areas in each memory area, it may be determined to divide the memory area into M sub-memory areas.
In the embodiment of the invention, the total available space of the storage area can be divided into N storage areas, and each storage area comprises M sub-storage areas.
In the embodiment of the invention, R carriers are divided into K carrier groups according to the number of soft bits corresponding to the maximum transmission block of the allocated R carriers, and a memory is determined to be divided into K storage areas corresponding to the K carrier groups; determining to divide each storage area of the K storage areas into M sub-storage areas according to the total available space of the memory; wherein R and K are integers greater than or equal to 2, and M is an integer greater than or equal to 1. According to the scheme, K storage areas can be divided for K carrier groups in R carriers according to the soft bit number corresponding to the maximum transmission block of the carriers, each storage area in the K storage areas is divided into the designated M sub-storage areas based on the total available space of the memory, compared with the storage area allocated for the carriers according to the maximum HARQ process number, the storage area can be allocated for each carrier, and the situation that a large number of storage areas are free due to the fact that more storage areas are allocated for a certain carrier is avoided, therefore the storage space in the memory is reasonably utilized, and the waste of the storage space is avoided.
In general, since the total available space of the memory is relatively limited, there is generally no way to allocate a memory area for each carrier when allocating a memory area for the carrier according to the maximum number of HARQ processes, it is impossible to allocate a memory area for each carrier, and it is possible that all the allocated memory areas are not occupied for the carriers allocated to the memory areas. In order to solve the problem in the existing memory partition, in the embodiment of the present invention, a certain memory area is allocated for each carrier, and in the case that the total available space of the memory is insufficient to allocate the memory area for each carrier when the memory is partitioned by the maximum HARQ process number, it may be preferentially ensured that each carrier is allocated to the memory area. Furthermore, in the embodiment of the invention, after the storage area is allocated for each carrier, the rest storage space is allocated to the carrier with higher priority, so that the storage space of the carrier with higher priority can be further ensured to be more sufficient, and the effect of reasonably allocating the storage space of the memory is achieved.
As shown in fig. 5, an embodiment of the present invention further provides a method for allocating a memory, where the method includes:
501. and determining the soft bit number corresponding to the maximum transmission block in the allocated R carriers.
Alternatively, R carriers allocated by the base station to the terminal device may be determined first, and the number of soft bits corresponding to the maximum transport block of each carrier in the R carriers, that is, the maximum transport block size of each carrier in the R carriers may be determined.
502. And dividing the carriers which have the same soft bit number and belong to the same carrier type into the same carrier group to obtain K carrier groups.
For example, in the LTE-NR dual connectivity system, it is assumed that carriers allocated by a base station to a terminal device include 1 LTE primary carrier, 3 LTE secondary carriers, 1 NR primary carrier, and 2 NR secondary carriers, and soft bits supported by the 1 LTE primary carrier and the 3 LTE secondary carriers are all E, the number of soft bits supported by the 1 NR primary carrier is a, and the number of soft bits supported by the 2 NR secondary carriers is B, C, D. If the carriers are divided according to the number of soft bits corresponding to the maximum transport block and the carrier type, it may be determined that 1 LTE primary carrier is divided in carrier group 1, 3 LTE secondary carriers are divided in carrier group 2,1 NR primary carrier is divided in carrier group 3,1 NR primary carrier is divided in carrier group 4, a first secondary carrier of 2 NR secondary carriers is divided in carrier group 5, and a second secondary carrier of 2 NR secondary carriers is divided in carrier group 6, so that 7 carriers may be divided into 6 carrier groups.
503. It is determined to divide the memory into K memory areas corresponding to K carrier groups.
For example, in the above example, 7 carriers are divided into 6 carrier groups, and then one memory area may be divided into the memory for each carrier group of the 6 carrier groups, that is, the memory is divided into 6 memory areas.
504. Each of the K memory areas is divided into M sub-memory areas according to the total available space of the memory.
According to the memory allocation method in the embodiment of the invention, a certain number of sub-memory areas are allocated according to the available total size (i.e. total available space) of the available HARQ buffer memory on the chip, namely a certain number of HARQ processes are allocated, so that the number of HARQ processes of each carrier wave can be reduced to reduce the HARQ memory space.
According to the above steps, for the scenario of LTE-NR dual connectivity, the HARQ buffer memory will be divided into the following areas:
dividing a storage area corresponding to a carrier group of an LTE main carrier;
dividing a storage area corresponding to the carrier group of the LTE auxiliary carrier;
dividing a storage area corresponding to a carrier group of an NR main carrier;
the NR secondary carrier is divided into N storage areas Di, i=0, 1, …, N-1 having different maximum transport block sizes, corresponding to the carrier group of the NR primary carrier.
Table 2 illustrates one possible HARQ memory partition parameter provided by an embodiment of the present invention.
TABLE 2
As shown in fig. 6, an embodiment of the present invention provides an allocation schematic diagram for allocating HARQ buffer memory according to the partition parameters of the HARQ memory shown in table 2.
Optionally, in the embodiment of the present invention, after dividing each storage area of the K storage areas into M sub-storage areas according to the total available space of the memory, the target data may also be stored in the target storage area when the target data is received through the target carrier. The target storage area is a storage area corresponding to the carrier group where the target carrier is located in the K storage areas.
In the embodiment of the invention, R carriers are divided into K carrier groups according to the number of soft bits corresponding to the maximum transmission block of the allocated R carriers, and a memory is determined to be divided into K storage areas corresponding to the K carrier groups; determining to divide each storage area of the K storage areas into M sub-storage areas according to the total available space of the memory; wherein R and K are integers greater than or equal to 2, and M is an integer greater than or equal to 1. According to the scheme, K storage areas can be divided for K carrier groups in R carriers according to the soft bit number corresponding to the maximum transmission block of the carriers, each storage area in the K storage areas is divided into the designated M sub-storage areas based on the total available space of the memory, compared with the storage area allocated for the carriers according to the maximum HARQ process number, the storage area can be allocated for each carrier, and the situation that a large number of storage areas are free due to the fact that more storage areas are allocated for a certain carrier is avoided, therefore the storage space in the memory is reasonably utilized, and the waste of the storage space is avoided.
505. A priority of each of the K carrier groups is determined.
506. And if the memory has the residual available space, distributing the residual available space according to the priority of each carrier group in the K carrier groups.
After the total available space of the memory is allocated according to the above-described methods 505 to 504, there may be a remaining available space, which may be allocated to a carrier group having a higher priority.
Alternatively, the remaining available space may be allocated as at least one sub-storage area to a target carrier group having a higher priority than a preset priority among the K carrier groups.
For example, for the scenario of LTE-NR dual connectivity, the priority of the LTE carrier may be set higher than the priority of the NR carrier, and the priority of the primary carrier may be set higher than the priority of the secondary carrier, based on the requirements of different carriers for reliability.
For example, the LTE primary carrier priority is 3, the LTE secondary carrier priority is 2, the nr primary carrier priority is 1, and the nr secondary carrier priority is 0.
If there is still remaining available space in the memory, the remaining available space may be allocated to a carrier group where the LTE primary carrier with priority 3 is located (i.e., a target carrier group), so as to ensure that the LTE primary carrier has enough memory space.
In the embodiment of the invention, the residual available space exists for the memory, and the residual available space can be allocated to the target carrier group with the priority higher than the preset priority, so that the sufficient memory space of the carrier with the higher priority can be preferentially ensured.
507. And configuring a corresponding bit compression ratio for each carrier group according to the priority of each carrier group in the K carrier groups.
Optionally, in the LTE-NR dual-connectivity scenario, the embodiment of the present invention may distinguish between the primary carrier and the secondary carrier of LTE and NR, and may use different compression ratios for the LTE primary carrier, the NR primary carrier, and the secondary carrier of LTE and NR.
In the embodiment of the invention, for the carrier group with higher priority, the required reliability performance is higher, so that a smaller compression ratio can be adopted.
Optionally, in the LTE-NR dual-connectivity scenario, the reliability required by the LTE primary carrier is highest, and a relatively low compression ratio may be used for the LTE primary carrier to ensure LTE primary carrier performance. The reliability of the NR main carrier is inferior to that of the LTE main carrier, and a moderate compression ratio can be adopted to ensure the performance of the NR main carrier. The LTE and NR secondary carriers are typically data transmissions, and the highest compression ratio may be employed to reduce HARQ memory space.
In the embodiment of the invention, different compression ratios can be allocated to the carrier groups with different priorities, so that smaller compression ratios can be adopted for the carrier groups with high priorities, and the reliability of the carrier groups with high priorities is ensured.
As shown in fig. 7, an embodiment of the present invention provides a memory allocation apparatus, including:
a processing module 701, configured to divide R carriers into K carrier groups according to the number of soft bits corresponding to the maximum transmission block in the allocated R carriers, and determine to divide the memory into K storage areas corresponding to the K carrier groups;
determining to divide each storage area of the K storage areas into M sub-storage areas according to the total available space of the memory;
wherein R and K are integers greater than or equal to 2, and M is an integer greater than or equal to 1.
Optionally, the processing module 701 is further configured to, after determining that each of the K memory areas is divided into M sub-memory areas, allocate the remaining available space according to the priority of each of the K carrier groups if there is the remaining available space in the memory.
Optionally, the processing module 701 is specifically configured to allocate the remaining available space as at least one sub-storage area to a target carrier group with a priority higher than a preset priority among the K carrier groups.
Optionally, the processing module 701 is specifically configured to divide R carriers into K carrier groups according to the number of soft bits corresponding to the maximum transport block of the allocated R carriers and carrier types of the R carriers.
Optionally, the processing module 701 is specifically configured to determine the number of soft bits corresponding to the maximum transport block of each carrier;
and dividing the carriers which have the same soft bit number and belong to the same carrier type into the same carrier group to obtain K carrier groups.
Optionally, the processing module 701 is specifically configured to determine a total available space of the memory;
calculating the bit number of the sub-storage area of each storage area according to the number of soft bits supported by the maximum transmission block of the carrier corresponding to each storage area and the bit number corresponding to each soft bit;
according to the total available space of the memory, combining the bit number of the sub-memory areas in each memory area, and calculating to obtain the number M of the sub-memory areas in each memory area;
it is determined that each of the K memory areas is divided into M sub-memory areas.
Optionally, the processing module 701 is specifically configured to calculate, according to the total available space of the memory, the number M of sub-storage areas of each storage area in combination with the following formula one;
the first formula is: M represents the number of sub-memory areas of each memory area, K represents the number of memory areas, T represents the total available space of the memory, S i Indicating the number of bits included in the i-th sub-storage area.
Optionally, the processing module 701 is further configured to determine, after determining that the memory is divided into K storage areas corresponding to K carrier groups, a priority of each carrier group in the K carrier groups; and configuring a corresponding bit compression ratio for each carrier group according to the priority of each carrier group in the K carrier groups.
Optionally, the processing module 701 is further configured to store the target data in the target storage area when the target data is received through the target carrier after dividing each storage area of the K storage areas into M sub-storage areas according to the total available space of the memory; the target storage area is a storage area corresponding to the carrier group where the target carrier is located in the K storage areas.
Optionally, in the embodiment of the present invention, the allocation device of the memory may be a functional module or a functional entity (for example, a processor) in the terminal device, and may also be the terminal device.
Optionally, the embodiment of the present invention further provides a terminal device, where the terminal device includes the memory allocation device, and the memory allocation device may be a processor.
The embodiment of the invention also provides a terminal device, which can include a processor, a memory and a computer program stored in the memory and capable of running on the processor, wherein the computer program can realize each process executed by the terminal device in the method embodiment and can achieve the same technical effect when being executed by the processor, and the repetition is avoided, and the description is omitted here.
Fig. 8 is a schematic hardware structure of a terminal device according to an embodiment of the present invention. The terminal device may include: radio Frequency (RF) circuitry 810, memory 820, input unit 830, display unit 840, sensor 850, audio circuitry 860, wireless fidelity (wireless fidelity, wiFi) module 870, processor 880, and power supply 890. Wherein the radio frequency circuit 810 includes a receiver 811 and a transmitter 812. Those skilled in the art will appreciate that the handset configuration shown in fig. 8 is not limiting of the handset and may include more or fewer components than shown, or may combine certain components, or may be arranged in a different arrangement of components.
The RF circuit 810 may be used for receiving and transmitting signals during a message or a call, and in particular, after receiving downlink information of a base station, it is processed by the processor 880; in addition, the data of the design uplink is sent to the base station. Typically, the RF circuitry 810 includes, but is not limited to, an antenna, at least one amplifier, a transceiver, a coupler, a low noise amplifier (low noise amplifier, LNA), a duplexer, and the like. In addition, the RF circuitry 810 may also communicate with networks and other devices via wireless communications. The wireless communications may use any communication standard or protocol including, but not limited to, global system for mobile communications (global system of mobile communication, GSM), general packet radio service (general packet radio service, GPRS), code division multiple access (code division multiple access, CDMA), wideband code division multiple access (wideband code division multiple access, WCDMA), long term evolution (long term evolution, LTE), email, short message service (short messaging service, SMS), and the like.
The memory 820 may be used to store software programs and modules, and the processor 880 performs various functional applications and data processing of the cellular phone by executing the software programs and modules stored in the memory 820. The memory 820 may mainly include a storage program area that may store an operating system, application programs required for at least one function (such as a sound playing function, an image playing function, etc.), and a storage data area; the storage data area may store data (such as audio data, phonebook, etc.) created according to the use of the handset, etc. In addition, memory 820 may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other volatile solid-state storage device.
The input unit 830 may be used to receive input numeric or character information and to generate key signal inputs related to user settings and function controls of the handset. In particular, the input unit 830 may include a touch panel 831 and other input devices 832. The touch panel 831, also referred to as a touch screen, may collect touch operations thereon or thereabout by a user (e.g., operations of the user on the touch panel 831 or thereabout using any suitable object or accessory such as a finger, stylus, etc.), and actuate the corresponding connection device according to a predetermined program. Alternatively, the touch panel 831 may include two portions of a touch detection device and a touch controller. The touch detection device detects the touch azimuth of a user, detects a signal brought by touch operation and transmits the signal to the touch controller; the touch controller receives touch information from the touch detection device and converts it into touch point coordinates, which are then sent to the processor 880 and can receive commands from the processor 880 and execute them. In addition, the touch panel 831 may be implemented in various types of resistive, capacitive, infrared, surface acoustic wave, and the like. The input unit 830 may include other input devices 832 in addition to the touch panel 831. In particular, other input devices 832 may include, but are not limited to, one or more of a physical keyboard, function keys (e.g., volume control keys, switch keys, etc.), a trackball, mouse, joystick, etc.
The display unit 840 may be used to display information input by a user or information provided to the user and various menus of the mobile phone. The display unit 840 may include a display panel 841, and optionally, the display panel 841 may be configured in the form of a liquid crystal display (liquid crystal display, LCD), an organic light-Emitting diode (OLED), or the like. Further, the touch panel 831 may overlay the display panel 841, and when the touch panel 831 detects a touch operation thereon or thereabout, the touch operation is transferred to the processor 880 to determine the type of touch event, and the processor 880 then provides a corresponding visual output on the display panel 841 according to the type of touch event. Although in fig. 8, the touch panel 831 and the display panel 841 are implemented as two separate components to implement the input and input functions of the mobile phone, in some embodiments, the touch panel 831 and the display panel 841 may be integrated to implement the input and output functions of the mobile phone.
The handset may also include at least one sensor 850, such as a light sensor, motion sensor, and other sensors. Specifically, the light sensor may include an ambient light sensor and a proximity sensor, wherein the ambient light sensor may adjust the brightness of the display panel 841 according to the brightness of ambient light, and the proximity sensor may turn off the display panel 841 and/or the backlight when the mobile phone moves to the ear. As one of the motion sensors, the accelerometer sensor can detect the acceleration in all directions (generally three axes), and can detect the gravity and direction when stationary, and can be used for applications of recognizing the gesture of a mobile phone (such as horizontal and vertical screen switching, related games, magnetometer gesture calibration), vibration recognition related functions (such as pedometer and knocking), and the like; other sensors such as gyroscopes, barometers, hygrometers, thermometers, infrared sensors, etc. that may also be configured with the handset are not described in detail herein.
Audio circuitry 860, speaker 861, microphone 862 may provide an audio interface between the user and the handset. The audio circuit 860 may transmit the received electrical signal converted from audio data to the speaker 861, and the electrical signal is converted into a sound signal by the speaker 861 to be output; on the other hand, microphone 862 converts the collected sound signals into electrical signals, which are received by audio circuit 860 and converted into audio data, which are processed by audio data output processor 880 for transmission to, for example, another cell phone via RF circuit 810, or which are output to memory 820 for further processing.
WiFi belongs to a short-distance wireless transmission technology, and a mobile phone can help a user to send and receive emails, browse webpages, access streaming media and the like through a WiFi module 870, so that wireless broadband Internet access is provided for the user. Although fig. 8 shows a WiFi module 870, it is understood that it does not belong to the necessary constitution of the handset, and can be omitted entirely as needed within the scope of not changing the essence of the invention.
The processor 880 is a control center of the mobile phone, connects various parts of the entire mobile phone using various interfaces and lines, and performs various functions of the mobile phone and processes data by running or executing software programs and/or modules stored in the memory 820 and calling data stored in the memory 820, thereby performing overall monitoring of the mobile phone. In the alternative, processor 880 may include one or more processing units; preferably, the processor 880 may integrate an application processor that primarily handles operating systems, user interfaces, applications, etc., with a modem processor that primarily handles wireless communications. It will be appreciated that the modem processor described above may not be integrated into the processor 880.
The handset further includes a power supply 890 (e.g., a battery) for powering the various components, which may be logically connected to the processor 880 through a power management system, as well as performing functions such as managing charge, discharge, and power consumption by the power management system. Although not shown, the mobile phone may further include a camera, a bluetooth module, etc., which will not be described herein.
In the embodiment of the present invention, the processor 880 is configured to divide R carriers into K carrier groups according to the number of soft bits corresponding to the maximum transport block in the allocated R carriers, and determine to divide the memory into K storage areas corresponding to the K carrier groups;
determining to divide each storage area of the K storage areas into M sub-storage areas according to the total available space of the memory;
wherein R and K are integers greater than or equal to 2, and M is an integer greater than or equal to 1.
Optionally, the processor 880 is further configured to allocate the remaining available space according to the priority of each of the K carrier groups if there is remaining available space in the memory after determining to divide each of the K memory areas into M sub-memory areas.
Optionally, the processor 880 is specifically configured to allocate the remaining available space as at least one sub-storage area to a target carrier group with a priority higher than a preset priority among the K carrier groups.
Optionally, the processor 880 is specifically configured to divide the R carriers into K carrier groups according to the number of soft bits corresponding to the maximum transport block of the allocated R carriers and carrier types of the R carriers.
Optionally, the processor 880 is specifically configured to determine the number of soft bits corresponding to the maximum transport block of each carrier;
and dividing the carriers which have the same soft bit number and belong to the same carrier type into the same carrier group to obtain K carrier groups.
Optionally, the processor 880 is specifically configured to determine the total available space of the memory;
calculating the bit number of the sub-storage area of each storage area according to the number of soft bits supported by the maximum transmission block of the carrier corresponding to each storage area and the bit number corresponding to each soft bit;
according to the total available space of the memory, combining the bit number of the sub-memory areas in each memory area, and calculating to obtain the number M of the sub-memory areas in each memory area;
it is determined that each of the K memory areas is divided into M sub-memory areas.
Optionally, the processor 880 is specifically configured to calculate, according to the total available space of the memory, the number M of sub-storage areas of each storage area in combination with the following formula one;
the first formula is:m represents the number of sub-memory areas of each memory area, K represents the number of memory areas, T represents the total available space of the memory, S i Indicating the number of bits included in the i-th sub-storage area.
Optionally, the processor 880 is further configured to determine, after determining that the memory is divided into K storage areas corresponding to the K carrier groups, a priority of each carrier group of the K carrier groups; and configuring a corresponding bit compression ratio for each carrier group according to the priority of each carrier group in the K carrier groups.
Optionally, the processor 880 is further configured to divide each of the K storage areas into M sub-storage areas according to a total available space of the memory, and when receiving the target data through the target carrier, store the target data in the target storage area, where the target storage area is a storage area corresponding to a carrier group where the target carrier is located in the K storage areas.
The embodiment of the invention provides a computer readable storage medium, which is characterized in that the computer readable storage medium stores a computer program, and when the computer program is executed by a processor, the computer program realizes each process executed by a terminal device in the embodiment of the method, and can achieve the same technical effect, so that repetition is avoided, and no redundant description is provided herein.
The computer readable storage medium may be a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, an optical disk, or the like.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
From the above description of the embodiments, it will be clear to those skilled in the art that the above-described embodiment method may be implemented by means of software plus a necessary general hardware platform, but of course may also be implemented by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a storage medium (e.g. ROM/RAM, magnetic disk, optical disk) comprising several instructions for causing a terminal device (which may be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to perform the method of the embodiments of the present invention.
The embodiments of the present invention have been described above with reference to the accompanying drawings, but the present invention is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those having ordinary skill in the art without departing from the spirit of the present invention and the scope of the claims, which are to be protected by the present invention.
Claims (13)
1. A method for allocating memory, comprising:
dividing R carriers into K carrier groups according to the number of soft bits corresponding to the maximum transmission block in the allocated R carriers, and determining to divide a memory into K storage areas corresponding to the K carrier groups;
dividing each storage area of the K storage areas into M sub-storage areas according to the total available space of the storage, wherein M is determined according to the ratio of the total available space of the storage areas to the total bit number corresponding to the K storage areas;
wherein R and K are integers greater than or equal to 2, and M is an integer greater than or equal to 1.
2. The method of claim 1, wherein the determining after dividing each of the K memory areas into M sub-memory areas further comprises:
And if the memory has the residual available space, distributing the residual available space according to the priority of each carrier group in the K carrier groups.
3. The method of claim 2, wherein said allocating the remaining available space according to the priorities of the K carrier groups comprises:
and using the residual available space as at least one sub-storage area, and distributing the residual available space to a target carrier group with a higher priority than a preset priority in the K carrier groups.
4. The method according to claim 1, wherein the dividing the R carriers into K carrier groups according to the number of soft bits corresponding to the largest transport block among the allocated R carriers includes:
and dividing the R carriers into K carrier groups according to the soft bit number corresponding to the maximum transmission block of the R carriers and the carrier types of the R carriers.
5. The method of claim 4, wherein the dividing the R carriers into K carrier groups according to the number of soft bits corresponding to the largest transport block in the allocated R carriers and carrier types of the R carriers comprises:
determining the number of soft bits corresponding to the maximum transmission block of each carrier;
And dividing the carriers which have the same soft bit number and belong to the same carrier type into the same carrier group to obtain the K carrier groups.
6. The method of claim 4, wherein the carrier type comprises at least one of:
NR primary carrier, NR secondary carrier, LTE primary carrier and LTE secondary carrier.
7. The method of claim 1, wherein determining to divide each of the K memory areas into M sub-memory areas based on a total available space of the memory comprises:
determining the total available space of the memory;
calculating the bit number of the sub-storage area of each storage area according to the number of soft bits supported by the maximum transmission block of the carrier corresponding to each storage area and the bit number corresponding to each soft bit;
according to the total available space of the memory, combining the bit number of the sub-memory areas in each memory area to calculate the number M of the sub-memory areas in each memory area;
it is determined that each of the K memory areas is divided into M sub-memory areas.
8. The method of claim 7, wherein the calculating the number M of sub-banks of each bank according to the total available space of the memory and the number of bits of the sub-banks of each bank includes:
According to the total available space of the memory, the number M of the sub-memory areas of each memory area is calculated by combining the following formula I;
the first formula is:m represents the number of sub-storage areas of each storage area, K represents the number of storage areas, T represents the total available space of the storage, S i Indicating the number of bits included in the i-th sub-storage area.
9. The method of any of claims 1 to 8, wherein after determining to divide the memory into K memory areas corresponding to the K carrier groups, further comprising:
determining the priority of each carrier group in the K carrier groups;
and configuring a corresponding bit compression ratio for each carrier group according to the priority of each carrier group in the K carrier groups.
10. The method according to any one of claims 1 to 8, wherein after dividing each of the K storage areas into M sub-storage areas according to a total available space of the memory, further comprising:
storing target data in a target storage area when the target data is received through a target carrier;
the target storage areas are storage areas corresponding to the carrier groups where the target carriers are located in the K storage areas.
11. A memory allocation device, comprising:
the processing module is used for dividing the R carriers into K carrier groups according to the number of soft bits corresponding to the maximum transmission block in the allocated R carriers, and determining to divide a memory into K storage areas corresponding to the K carrier groups;
dividing each storage area in the K storage areas into M sub-storage areas according to the total available space of the storage, wherein M is determined according to the ratio of the total available space of the storage areas to the total bit number corresponding to the K storage areas;
wherein R and K are integers greater than or equal to 2, and M is an integer greater than or equal to 1.
12. A terminal device, comprising: a processor, a memory and a computer program stored on the memory and executable on the processor, which when executed by the processor implements the memory allocation method according to any one of claims 1 to 10.
13. A computer-readable storage medium, comprising: the computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements a memory allocation method according to any of claims 1 to 10.
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