CN112240909A - Bridge inhaul cable broken wire sound signal acquisition system and method - Google Patents

Abstract

The invention discloses a system and a method for acquiring a broken wire sound signal of a bridge inhaul cable, wherein the system comprises a sampling module, a processing module and a checking module; the sampling module is used for amplifying and filtering the received initial broken wire sound signal by adopting an amplifying circuit and a filtering circuit, and then sending the digital broken wire sound signal obtained by the analog-to-digital conversion circuit to the processing module; the processing module stores the digital broken filament sound signals by adopting an FIFO memory, and the digital broken filament sound signals are sent to an upper computer through the gigabit Ethernet module by the FIFO memory; the checking module comprises a module for checking when the gigabit Ethernet module transmits the digital broken-wire sound signal by adopting a cyclic redundancy check code. The system is suitable for an acoustic signal data acquisition system of the bridge inhaul cable, ensures the completeness and accuracy of the broken wire acoustic signal, and realizes the health monitoring of the bridge inhaul cable.

Description

Bridge inhaul cable broken wire sound signal acquisition system and method

Technical Field

The invention relates to the technical field of bridge inhaul cables, in particular to a system and a method for acquiring a broken wire sound signal of a bridge inhaul cable.

Background

The statements in this section merely provide background information related to the present disclosure and may not necessarily constitute prior art.

The stay cable is a key stressed component of a cable system bridge such as a cable-stayed bridge, a tied arch bridge and a suspension bridge, and is corroded, broken and the like due to the environmental corrosion and aging effect, so that the safety detection of the bridge stay cable is needed.

The method comprises the steps of collecting a broken wire signal of a bridge cable, and realizing health monitoring of broken wire of the bridge cable by analyzing the broken wire sound signal, wherein the current system for collecting the broken wire sound signal of the bridge cable is mainly divided into a general acoustic emission collection system and a special acoustic emission collection system, the general acoustic emission collection system has wide application range and complete functions, but has higher cost, and can reach the use standard after parameters in the system are corrected; the special acoustic emission acquisition system is specially designed for a specific material or a specific field according to the characteristics of acoustic emission signals generated in the test field, and the compatibility and the universality of acoustic signal acquisition cannot be realized.

Disclosure of Invention

In order to solve the problems, the invention provides a system and a method for acquiring a broken wire sound signal of a bridge inhaul cable.

In order to achieve the purpose, the invention adopts the following technical scheme:

in a first aspect, the present invention provides a bridge cable wire breakage acoustic signal acquisition system, including: the device comprises a sampling module, a processing module and a checking module;

the sampling module is used for amplifying and filtering the received initial broken wire sound signal by adopting an amplifying circuit and a filtering circuit, and then sending the digital broken wire sound signal obtained by the analog-to-digital conversion circuit to the processing module;

the processing module stores the digital broken filament sound signals by adopting an FIFO memory, and the digital broken filament sound signals are sent to an upper computer through the gigabit Ethernet module by the FIFO memory;

the check module adopts cyclic redundancy check codes to check the gigabit Ethernet module when transmitting digital broken-wire sound signals.

In a second aspect, the invention provides a bridge cable wire breakage sound signal acquisition method, which comprises the following steps:

after the received initial filament breaking sound signal is subjected to amplification processing and filtering processing by adopting an amplifying circuit and a filtering circuit, a digital filament breaking sound signal is obtained by an analog-to-digital conversion circuit;

storing the digital broken filament sound signals by adopting an FIFO memory, and sending the digital broken filament sound signals to an upper computer through a gigabit Ethernet module by the FIFO memory;

and verifying the digital broken-wire sound signal transmitted by the gigabit Ethernet module by adopting a cyclic redundancy check code.

Compared with the prior art, the invention has the beneficial effects that:

the invention carries out early conditioning treatment on the broken wire sound signal, and amplifies the broken wire sound signal by 15 times through amplification and filtering to reach the ADC input acquisition range; the noise signal with high filtering frequency is filtered by a low-pass filter with the cut-off frequency of 700KHz, so that the noise interference is avoided.

The invention has high sampling precision on the broken wire acoustic signal, high sampling frequency, stable transmission and high transmission rate by using gigabit Ethernet for transmission; when the gigabit Ethernet is used for transmitting the disconnected voice signals, the cyclic redundancy check code CRC is adopted to check the data loss or data errors possibly occurring in the transmission process, the CRC check error rate is low, and the reliability of the Ethernet transmission channel is ensured.

According to the invention, a PCB layout is adopted, an FPGA is taken as a core element, a broken wire sound signal flows to a front-end conditioning circuit through a sensor, then flows to an ADC, flows to the FPGA through analog-to-digital conversion, and a decoupling capacitor and a filter capacitor are arranged around a power supply and a chip, so that the anti-interference capability is improved; and mutual interference is reduced by the zero ohm resistor or the magnetic bead isolation mode part and the data part.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the invention and together with the description serve to explain the invention and not to limit the invention.

Fig. 1 is a structural diagram of a bridge cable wire breakage sound signal acquisition system provided in embodiment 1 of the present invention;

fig. 2 is a schematic diagram of an amplifying circuit provided in embodiment 1 of the present invention;

fig. 3 is a schematic diagram of an enlarged simulation result provided in embodiment 1 of the present invention;

fig. 4 is a schematic diagram of a low-pass filter provided in embodiment 1 of the present invention;

fig. 5 is a schematic diagram of simulation results of a low-pass filter provided in embodiment 1 of the present invention;

fig. 6 is a schematic diagram of an ADC hardware circuit provided in embodiment 1 of the present invention;

fig. 7 is a schematic diagram of the connection between the ADC and the FPGA pins according to embodiment 1 of the present invention;

FIGS. 8(a) -8(b) are timing diagrams of the ADS1675 according to embodiment 1 of the present invention;

fig. 9 is a schematic diagram of an ADS1675 programming architecture provided in embodiment 1 of the present invention;

fig. 10 is a schematic diagram of configuration of an active parallel mode of an FPGA according to embodiment 1 of the present invention;

FIG. 11 is a schematic diagram of a FIFO configuration according to embodiment 1 of the present invention;

fig. 12 is a connection diagram of a PHY chip, an FPGA, and a network transformer according to embodiment 1 of the present invention;

fig. 13 is a schematic circuit diagram of a hardware circuit of RTL8211EG according to embodiment 1 of the present invention;

fig. 14 is a schematic diagram of an ipsec sending module state machine according to embodiment 1 of the present invention;

fig. 15 is a schematic layout diagram of a PCB provided in embodiment 1 of the present invention;

fig. 16 is a schematic diagram of a power supply design conversion relationship provided in embodiment 1 of the present invention;

fig. 17 is a schematic diagram of a signal source sending a 100KHz signal according to embodiment 1 of the present invention;

fig. 18 is a schematic diagram illustrating a processing result of ethernet transmission verification data according to embodiment 1 of the present invention;

fig. 19(a) -19(b) are schematic diagrams of experimental verification results provided in example 1 of the present invention.

Fig. 19(c) is a partially enlarged schematic view of the lead-cut signal waveform of fig. 19(a) in embodiment 1 of the present invention.

Fig. 19(d) is a schematic diagram of a waveform signal obtained by using the system m2p.59xx-x4 in embodiment 1 of the present invention.

The specific implementation mode is as follows:

the invention is further described with reference to the following figures and examples.

It is to be understood that the following detailed description is exemplary and is intended to provide further explanation of the invention as claimed. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.

It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of exemplary embodiments according to the invention. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise, and it should be understood that the terms "comprises" and "comprising", and any variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

The embodiments and features of the embodiments of the present invention may be combined with each other without conflict.

Example 1

As shown in fig. 1, the present embodiment provides a system for acquiring a broken wire acoustic signal of a bridge cable, which includes a sampling module, a processing module and a checking module;

the sampling module is used for amplifying and filtering the received initial broken wire sound signal by adopting an amplifying circuit and a filtering circuit, and then sending the digital broken wire sound signal obtained by the analog-to-digital conversion circuit to the processing module;

the processing module stores the digital broken filament sound signals by adopting an FIFO memory, and the digital broken filament sound signals are sent to an upper computer through the gigabit Ethernet module by the FIFO memory;

the checking module comprises the step of checking the gigabit Ethernet module when transmitting the digital wire breaking sound signal by adopting a cyclic redundancy check code.

The sampling module comprises a sensor, an amplifying circuit, a filter circuit and an ADC (analog-to-digital converter) circuit;

in this embodiment, the initial break acoustic signal is collected by a resonant sensor, which is located at the sound source; because the broken wire signal of the bridge inhaul cable is weak and the frequency range is 43 KHz-500 KHz, the resonant sensor is sensitive to the signal under the central frequency and the frequency response range is narrow; therefore, the present embodiment selects SR40M narrow band sensor, SR150M middle band sensor and WG500 wide band sensor with center frequencies of 40KHz, 150KHz and 500KHz respectively to ensure effective acoustic signal acquisition.

Because the broken wire acoustic signal of the bridge inhaul cable is within 100mV, and the ADC input voltage range of the analog-to-digital converter is-3V- +3V, the acoustic signal is amplified by the amplifying circuit in the embodiment, so that 15 times of amplification is realized, and the ADC input acquisition range is reached;

in the embodiment, a low noise amplifier ADA4896-2 of Adenono (ADI) company is adopted, the unit gain of the ADA4896-2 is stable, the noise is low, the rail-to-rail output is realized, the spurious-free dynamic range is-80 dB, a bridge broken wire acoustic emission signal is within 1MHz, and the bandwidth of a chip is 230MHz to meet the requirement; as shown in fig. 2, the two operational amplifiers are connected in parallel with the capacitors through resistors R1 and R2 to form negative feedback, and are connected to the negative input terminals of the two capacitors through a resistor R3, so that the circuit:

the gain G of the amplifier circuit is:

simulation was performed by using circuit simulation software Multisim, and as a result of the simulation, when the input signal was 96mV, the output signal was 1.47V, which amplified the input signal by 15 times, as shown in fig. 3.

Because the frequency range of the broken wire acoustic signal of the bridge inhaul cable is 43 KHz-500 KHz, the embodiment carries out filtering processing by a low-pass filter, the cut-off frequency is 700KHz, and noise interference is avoided; a second-order butterworth low-pass filter is used for the amplifier THS4503 in the filter circuit to filter the noise signal with a large frequency, and the low-pass filter is shown in fig. 4:

the network transfer function of the second order butterworth low pass filter is:

in the formula, w_rIs-3 dB bandwidth angular frequency, δ is the filter design coefficient;

from formulas (3) and (4):

wherein, R1 ═ 1k Ω, R2 ═ 1k Ω, C1 ═ 2nF, and C2 ═ 1 nF.

In this embodiment, the bridge cable wire breakage signal is less than 700KHz, the-3 dB bandwidth is set to 700KHz, the value of the resistance and capacitance in the low-pass filter circuit is determined through Multisim simulation, and the simulation result is shown in fig. 5, which shows that the-3 dB bandwidth of the simulation result is 700 KHz.

In the ADC analog-to-digital conversion circuit, an ADS1675 with 24-bit resolution and 4Msps sampling rate is selected as a data acquisition chip, signals are amplified and filtered and then input into the ADS1675, and are output into an FPGA after ADC analog-to-digital conversion, and an ADC hardware circuit is shown in FIG. 6.

ADS1675 needs to provide 5V analog power supply voltage and 3V digital power supply voltage, the power is 575mW, bipolar + -3V input voltage range, the device has complete specification in industrial temperature range, and is packaged by TQFP-64; ADS1675 is controlled by I/O pin, without internal register to be programmed; the START pin can directly control conversion, the START pin is controlled to START analog-to-digital conversion, and data are differentially output through the DOUT pin; when not in use, the PDWN pin can be used for turning off the power supply of all device circuits; the pins connected to the FPGA are shown in fig. 7, and the specific functions of the pins are shown in table 1:

TABLE 1 ADS1675 Pin function

ADS1675 controls the START and the end of sampling through a START pin, the timing sequence is shown in FIGS. 8(a) -8(b), VHDL language is compiled into two processes, ADS1675 defaults to a low-speed mode after being powered on, the CLK clock process is responsible for the configuration from low speed to high speed, when the SCLK clock is multiplied by three times the CLK clock, the START level is high and DRDY pulse occurs, which indicates that the high-speed acquisition mode is configured, and the SCLK process is switched; the method is responsible for data acquisition in an SCLK clock process, and only one positive pulse is needed to be given to a START pin in the SCLK process to START A/D conversion. On the rising edge of the DRDY signal, the analog signal begins to sample, at which time DOUT begins to send out data serially.

Programming architecture as shown in fig. 9, the ADC configuration process is as follows.

Init: initializing a state; PDWN is powered on at 1, DRATE [2:0] ═ 010 is configured to the sampling frequency of 500KHz, FPATA is set to 0 and is set to a wide-frequency filter, delay is carried out, and if the delay time is reached, a Lowspeed configuration Lowspeed state is carried out.

Lowspeed: acquiring a state in a low-speed mode; after the Init state configuration, START jumps to latch the configuration and determine the Decode _1 state.

Decide _ 1: judging whether the low-speed mode is configured with a successful state; if DRDY pulse occurs, the configuration is successful, the clock rate of SCLK in the low-speed mode is equal to the clock rate of CLK, power-on is carried out through PDWN ═ 1, DRATE [2:0] ═ 101 is configured to the sampling frequency of 4MHz, FPATH ═ 0 is set to a broadband filter, time delay is carried out, and if the time delay is reached, a high-speed configuration high state is carried out.

Highsped: acquiring a state in a high-speed mode; the transition is made again through START to latch the configuration, determining the Decode _2 state.

Decide _ 2: judging whether the high-speed mode is configured with a successful state; if a Drdy pulse occurs, the high mode SCLK clock rate is three times the CLK rate, indicating successful configuration, entering the Data state.

Data: a data acquisition state; START is always set to 1, and 24-bit data output is performed according to SCLK pulses.

The processing module adopts an FPGA processing module, utilizes a master-slave configuration mode of FPGA, adopts a two-channel synchronous ADC + FPGA + gigabit Ethernet processing mode in the embodiment, selects a Spartan-6 series XC6SLX150 as a core control chip, and selects a sampling frequency greater than 2 times of a signal acquisition frequency according to Shannon sampling theorem, namely selects an ADS1675 with 24-bit resolution and 4Msps sampling rate as a data acquisition chip; in order to realize that all the acoustic signal data are output to the upper computer and realize high-speed communication, the embodiment adopts a gigabit ethernet transmission mode.

The configuration of the Spartan-6 series chip is loaded into an FPGA internal memory in a form of bit stream through program data generated by ISE software, the Spartan-6FPGA is provided with a pin special for configuration, and the pin function is shown in Table 2; the XC6SLX150 can be configured by actively loading data from an external nonvolatile memory or passively loading data by external microprocessing and the like, the FPGA is actively configured by a chip XCF32PVOG48 special for Xilinx corporation, and the XCF32PVOG48 is a chip XC6SLX150 special for configuration.

TABLE 2 specific functions of FPGA configuration pins

The state of M [1:0] pin determines the configuration mode of FPGA, in JAPG configuration mode, xx state of M [1:0] pin shows that JAPG mode can be used as long as FPGA is powered on, software code of board card is easy to debug, and the configuration mode is shown in Table 3.

TABLE 3 arrangement

In the embodiment, an active parallel mode is adopted to realize FPGA configuration, a parallel data mode has the characteristic of high success rate of program downloading, TDI, TDO, TCK, and TMS boundary scan pins are reserved, data are loaded to an SRAM inside an FPGA from an XCF32PVOG48 chip after power on, and an active parallel mode circuit is shown in fig. 10.

The processing module comprises an ADC data storage module, the ADC data storage module is used for storing ADC data and sending the data to the gigabit Ethernet Ipsend module after the data storage is full; because the bit width of the ADC data is 24 bits, the sampling rate is 4Mbps, and the Ethernet transmission speed is 125MHz, the ADC data cannot be directly transmitted to the Ethernet, and a memory is required to be used for clock synchronization;

in this embodiment, FIFO (First Input First output) refers to a First-in First-out memory, and ADC data is stored in FIFO according to an acquisition sequence; in order to guarantee the effective bandwidth of the ethernet frame, the depth of the FIFO is set to 1024, when the ADC data is full, the FIFO will send a full signal to instruct the ip send module to start sending the ethernet frame, and then the FIFO performs data output according to the read signal of the module to send the ADC data to the ethernet, as shown in fig. 11, the bit width of the ADC data is 24 bits for the convenience of the upper computer to analyze the data, so that 8 bits (5A) are added to the ADC data to represent each ADC data, and thus each ADC data is 32 bits.

In the embodiment, the ADC has the sampling precision of 4MSPS, the sampling precision of 24 bits, the data volume transmitted per second is 96Mbps, the data volume transmitted per second by two channels is 192Mbps, and in order to transmit data to an upper computer for signal analysis, a gigabit Ethernet is selected for data transmission;

in the embodiment, a highly integrated network of Ri Yi (Realtek) company is selected to receive an RTL8211EG Ethernet PHY chip, the PHY chip conforms to the standards of 10Base-T, 100Base-TX and 1000Base-T, the transmission of 10M/S, 100M/S and 1000M/S data can be realized, data can be transmitted through five types of twisted pairs and three types of twisted pairs, and GMII, RGMII and MII interfaces are supported; in addition, the QFN package with 64 pins is adopted, the power consumption is 0.5nW, half-duplex and full-duplex work is supported, the power-down mode is supported, the E _ COL is connected with a 10K resistor in series and grounded, the embodiment is configured into a GMII interface, and the transmission clock is 125 MHz;

when the Ethernet data needs to be sent, the FPGA firstly sends the data to an RTL8211EG Ethernet PHY chip for data coding, the data is loaded on a network cable through a network transformer HR911130A, namely a network cable interface RJ-45, and the data is transmitted to a receiver through a network; data sent by a far end through a network are loaded and transmitted to a network transformer through a network cable, the data are output to an RTL8211EG Ethernet PHY chip by the network transformer to be decoded to obtain actual data, and then the data are transmitted to an FPGA chip; the connection between the PHY chip and the FPGA and the network transformer is shown in fig. 12, the connection between the RTL8211EG hardware circuit is shown in fig. 13, and the specific functions of the pins connected to the FPGA are shown in table 4:

TABLE 4 RTL8211EG Pin specific Functions

The gigabit ethernet module includes an ethernet group packet transmitting module (ipsed), a CRC generating module (CRC), and an ADC Data storage module (ADC _ Data _ Memory).

The ip send module implements the framing and sending functions of the UDP packet, and the state transition of the state machine is as shown in fig. 14, where the state machine is divided into 8 states:

idle state: sending an idle state of a state machine; at this time, the data is completely emptied and the initial value is restored.

The start state: starting a transmission state; when the idle state counts to the Ethernet minimum frame gap 10 and the ADC data storage module is full of data, the Ethernet sending state machine jumps to the start state and starts sending the Ethernet frame.

make state: calculating the state of a UDP frame header; and after the sending state machine is in a start state, the next clock enters a make state, frame numbers are added at the positions of the frame headers in order to ensure the accuracy of the Ethernet frames, and meanwhile, the UDP frame header check codes are recalculated.

send55 state: the Ethernet sends the preamble and frame guide code (55_55_55_55_55_55_ D5) state of the Ethernet, enters the Ethernet frame sending state, sets the effective signal (tx _ en) of the Ethernet sending data to 1, and calculates the Ethernet check code.

sendmac state: sending the state of the Ethernet mac address; when the sending state machine is in send55 state and i is equal to 7, that is, after the sending of the preamble and the frame preamble is completed, the sending state machine enters into this state for sending the preset mac address.

sendreader state: sending the frame head state of an Ethernet UDP frame; and when the sending state machine is in a sendmac state and i is 13, namely after the mac address is sent, entering the state for sending the preset and calculated UDP frame headers.

senddata state: sending an Ethernet UDP data state; and when the sending state machine is in a sendreader state and i is equal to 6, namely after the sending of the frame header of the Ethernet UDP frame is finished, the sending state is entered for sending the ADC data, and when the senddata state is finished, the calculation of the Ethernet check code is stopped.

sendcrc state: and sending an Ethernet frame check code state, when the sending state machine is in a senddata state and i is data _ length, namely after the data to be sent is finished, entering the state for sending the Ethernet frame check code, when i is 4, stopping sending, setting an effective signal (tx _ en) of the Ethernet sending data to 0, returning the sending state machine to an idle state, and waiting for sending the Ethernet frame next time.

The checking module adopts a CRC checking mode; in order to ensure the reliability of an Ethernet transmission channel, a certain error detection and correction mode is adopted, a Cyclic Redundancy Check (CRC) -32 check code in the CRC used by the Ethernet is used as the last 4 bytes of an Ethernet frame for transmission, and the generated expression is as follows:

in the FPGA, the CRC implementation mode is divided into a serial mode and a parallel mode, each clock in the serial mode only processes one bit, and the implementation mode is simple and occupies less resources; however, this method is slow and not suitable for processing gigabit ethernet data. The parallel mode is that one clock processes a plurality of bits, each clock of the gigabit Ethernet has 8 bits, and the 8 bits are matched with the GMII interface protocol of the gigabit Ethernet, so the parallel mode is used in the CRC check code generation and check of the gigabit Ethernet.

The addition in the calculation of the CRC check code is modulo-2 addition, that is, 0+0 equals 0, 0+1 equals 1, and 1+1 equals 0, so the CRC generation expression can be realized by a simple exclusive-or operation and a shift register. The serial mode is that after 1bit data is input into each clock, the CRC value of the current bit can be realized by generating an expression and carrying out XOR and shift calculation, namely, the calculated CRC value is only related to the current input bit and the current CRC. The parallel operation can be regarded as a plurality of serial simultaneous inputs, the generated CRC is substituted, the parallel operation can be input in 8 bits, and the expression of the CRC-32 part is as follows:

the CRC calculation process of the FPGA is simple, CRC calculation needs to be carried out on the MAC address, the UDP header and frame data in the Ethernet frame, the flag signal of the Ethernet check code is already set to 1 when the state in the Ipsend module is converted, CRC calculation is carried out when the signal is set to 1, and after calculation is finished, the CRC result is restored to the initial value FFFFFF.

In this embodiment, the system further comprises a PCB design: the PCB realizes the electrical interconnection among all elements, determines the reliability and stability of the whole acoustic emission acquisition system, and adopts the Allegro software of Cadence company; the PCB layout is as shown in FIG. 15, the layout is carried out around taking the FPGA as a core element, the elements are uniformly, neatly and compactly arranged in the PCB, the signal flowing direction in the PCB is from left to right, the signal flows to a front-end conditioning circuit through a sensor, then flows to an ADC (analog-to-digital converter), and flows to the FPGA through analog-to-digital conversion, and a decoupling capacitor and a filter capacitor are arranged around a power supply and a chip, so that the anti-interference capability is improved;

in addition, the embodiment is a high-speed acquisition system, the high-frequency noise of the digital signal is very large, if the analog signal and the digital signal are mixed, the noise is transmitted to the analog part, the broken line in fig. 15 shows that the analog ground and the digital ground are divided, the left part of the broken line is the analog signal, the right part of the broken line is the digital signal, and the middle of the broken line is connected through a zero ohm resistor or a magnetic bead, so that the noise interference is reduced.

In this embodiment, the system further includes a power supply circuit, which ensures that the power of the power supply is greater than the total power consumption of the device, so that the system operates stably. The embodiment is divided into a digital power supply and an analog power supply, wherein the digital power supply mainly supplies power to digital devices such as an ADC (analog to digital converter), an FPGA (field programmable gate array) and a communication module; the analog power supply mainly supplies power to an amplifier, a filter and the like, as shown in fig. 16; the embodiment adopts two types of power supply chips, namely a linear voltage regulator (LDO) and a direct current-to-direct current voltage (DC/DC); the LDO power supply chip has good stability, fast load response and small output ripple, and can only be used in voltage reduction application; the DC/DC power supply chip has high efficiency and wide input voltage range. Therefore, an external 12V power supply is converted into digital power supplies of 3.3V, 1.2V and 1.8V and +6V and-6V of an analog power supply through a DC/DC power supply chip, and then the +6V and the-6V are converted into digital +5V and +3V and analog +5V, -5V and +2.5V through an LDO power supply chip.

In this embodiment, the bridge cable broken wire acquisition system mainly comprises an ADC data acquisition software design, a gigabit ethernet communication module, a CRC check module, an ADC data storage module, and an application of an internal IP core of an FPGA, that is, implemented in the FPGA by using a VHDL language, an asynchronous FIFO is implemented by adding the internal IP core of the FPGA, and clock distribution is implemented by an internal PLL core of the FPGA; all program files and functions are shown in table 5:

TABLE 5 Collection of System program files and implementation of functions

In order to verify the performance of ADC data acquisition, the ideal value output and the actual value output of the ADC are compared, and the values are the same or approximate, which indicates that the ADC data acquisition accuracy is high. According to the ADS1675 data manual, when the output of 24 bits of the chip is analog input 0V to +3V, the 16-system representation is converted into digital output 0x000000 to 0x7FFFFF, and the 10-system representation is converted into digital output 0 to 8388607. The conversion relation between the analog output voltage and the ideal value digital output voltage is as follows:

wherein, V_outIs an ideal value data output, V_inThe method is characterized in that the method is used for simulating input voltage, namely ADC input, direct current signal testing is shown in a table 6, a signal source input refers to voltage emitted by a signal generator, the voltage when an ADC input refers to signal enters an ADC is measured by a universal meter, an actual value and an ideal value are both expressed by 10 systems, the ideal value is obtained through calculation, the ADC output value is converted into a value obtained by 10 systems through Chipscope, the error is determined by dividing the absolute value of the ideal value minus the ADC output value by the ideal value, the maximum of the actual value and the ideal value in million-level numbers is not more than 1000, the error is lower than 0.02%, and the precision is very high.

TABLE 5-1 ADC DC TEST METER

After testing the direct current performance, verifying the effectiveness of a hardware circuit by using a signal source to send alternating current sinusoidal signals with frequencies of 100KHz, 200KHz and 300KHz respectively, burning ADC program software into a PCB board card through ISE software, opening Chipscope software to collect signals to obtain correct sinusoidal waveforms, and obtaining a collection result obtained by sending 100KHz sinusoidal waves by the signal source as a standard sinusoidal wave as shown in FIG. 17, so that the designed hardware circuit is effective; when 200KHz and 300KHz sine waves are input into the signal source, the input 100KHz acquisition waveforms are the same, and the hardware circuit is verified to be effective and the ADC data acquisition is accurate.

The verification of the transmission correctness of the Ethernet requires the support of Wireshark software and NetAssist software, the Wireshark is network packet analysis software, can capture network packets and display the most detailed network packet data as far as possible; NetAssist is network serial port debugging software, can be used for the communication among the serial ports of the network, carry on the control, debugging of the serial port, the tool supports udp and tpc agreement, only need input corresponding host computer and IP address monitored, offer the function of multilink and analytic of multidata format for users;

downloading all programs of ADC and Ethernet into a board card, inputting 100KHz sine wave signals through a signal source, when Wireshark software is opened to see a transmitted UDP protocol packet, indicating that the PCB board card and a PC end are successfully linked, opening NetAssist software to receive data, and introducing the obtained data into Matlab for data processing; the data received by NetAssist software is stored in txt, at the moment, MATLAB is used for reading the txt according to characters, each data in the txt is 16-system data, each 8 data is data of one ADC, 2000 data are read in the MATLAB for analysis, and the 2000 data are data acquired by each ADC, and are 16-system data; then, converting the 16-system ADC acquisition data into 10-system data, wherein the upper 8 bits of each ADC data are 0x5A, so that 5A needs to be subtracted in data analysis; fig. 18 shows the acquisition result obtained by Matlab when the signal source sends 100KHz sine wave, i.e. standard sine wave, so that ethernet transmission is effective; when 200KHz and 300KHz sine waves are input into the signal source, the Matlab processing result is the same as the input 100KHz sine wave, and the Ethernet transmission is verified to be accurate and effective.

In order to verify the overall performance of the integrated system, in the embodiment, an acoustic emission signal is generated through lead breaking experiment simulation, an acoustic emission sensor is fixed on a flat steel plate by using an adhesive tape, a pencil and the plane of the steel plate are arranged at an included angle of 30 degrees to be broken, the broken position of the pencil is 5 cm away from the sensor, the acoustic emission signal acquired by the sensor is processed by a front-end circuit, ADC (analog-to-digital converter) and gigabit Ethernet, data is transmitted to an upper computer and the upper computer to be processed in MATLAB in a waveform mode, and the obtained waveform and a result obtained under the same experiment condition and M2P.59xx-x4 are compared and analyzed;

by breaking the pencil lead, processing the acquired 16-system data through MATLAB, wherein the high 8 bits of each ADC data is 0x5A, so that 5A needs to be reduced in data analysis, and then converting the 16-system ADC acquired data into 10-system data, as shown in FIG. 19(a), two high-amplitude signals can be obviously seen, as shown in FIG. 19(b), lead breaking signal acquisition data is carried out by using a German Spectrum digitizer M2P.59xx-x4, and the data are processed through an MATLAB program carried by the company, wherein the waveforms of the acquisition processing results of FIG. 19(a) and FIG. 19(b) are consistent, and the two high-amplitude signals displayed in the diagram are acoustic emission signals generated by breaking the pencil lead, which shows that the system can correctly acquire the signals and can distinguish the lead breaking signals;

the local amplification of the waveform of the broken lead signal acquired in the step (a) in the step (19) is shown in the step (c) in the step (19), the waveform of the broken lead signal acquired in the step (d) in the step (19) is shown in the step (c), the waveform signal processed by software carried by the system is compared to find that the acquired waveforms are consistent, so that the system can accurately acquire the signal and can distinguish the broken lead signal, and in the future practical application of the bridge, when the bridge cable is broken, the performance of the system is feasible, and the acoustic emission signal of the broken bridge cable can be accurately detected;

example 2

The embodiment provides a bridge inhaul cable broken wire sound signal acquisition method, which comprises the following steps:

after the received initial filament breaking sound signal is subjected to amplification processing and filtering processing by adopting an amplifying circuit and a filtering circuit, a digital filament breaking sound signal is obtained by an analog-to-digital conversion circuit;

storing the digital broken filament sound signals by adopting an FIFO memory, and sending the digital broken filament sound signals to an upper computer through a gigabit Ethernet module by the FIFO memory;

and verifying the digital broken-wire sound signal transmitted by the gigabit Ethernet module by adopting a cyclic redundancy check code.

The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes will occur to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Although the embodiments of the present invention have been described with reference to the accompanying drawings, it is not intended to limit the scope of the present invention, and it should be understood by those skilled in the art that various modifications and variations can be made without inventive efforts by those skilled in the art based on the technical solution of the present invention.

Claims (10)

1. The utility model provides a bridge cable broken wire acoustic signal collection system which characterized in that includes: the device comprises a sampling module, a processing module and a checking module;

the sampling module is used for amplifying and filtering the received initial broken wire sound signal by adopting an amplifying circuit and a filtering circuit, and then sending the digital broken wire sound signal obtained by the analog-to-digital conversion circuit to the processing module;

the processing module stores the digital broken filament sound signals by adopting an FIFO memory, and the digital broken filament sound signals are sent to an upper computer through the gigabit Ethernet module by the FIFO memory;

the check module adopts cyclic redundancy check codes to check the gigabit Ethernet module when transmitting digital broken-wire sound signals.

2. The system for acquiring the acoustic signal of the broken wire of the bridge cable according to claim 1, wherein the amplifying circuit adopts two operational amplifiers, a negative feedback is constructed in the operational amplifier by connecting a resistor and a capacitor in parallel, and the negative input ends of the two capacitors are connected through a third resistor.

3. The system for acquiring the acoustic signal of the broken wire of the bridge cable according to claim 1, wherein the FIFO memory sequentially stores the digital acoustic signal of the broken wire, and drives the gigabit Ethernet module to send the digital acoustic signal of the broken wire after the data is fully stored.

4. The system for collecting the sound signal of the wire breakage of the bridge cable according to claim 1, wherein the gigabit Ethernet module sends the digital wire breakage sound signal to the Ethernet chip for data coding, and the digital wire breakage sound signal is loaded onto a network cable through a network transformer and then sent to an upper computer.

5. The system for acquiring the acoustic signal of the broken wire of the bridge cable according to claim 4, wherein the acoustic signal data of the broken wire sent by the upper computer is loaded and transmitted to the network transformer through a network cable, and the network transformer outputs the data to the Ethernet chip for decoding to obtain the acoustic signal data of the original broken wire, thereby realizing the synchronous transmission of two channels.

6. The system for acquiring the sound signal of the broken wire of the bridge cable according to claim 1, wherein the CRC check code generation and the CRC check in the check module use a parallel mode, and the addition during the calculation of the CRC check code adopts modulo 2 addition.

7. The system for collecting the acoustic signal of the wire breakage of the bridge cable according to claim 1, further comprising a PCB module for isolating the analog wire breakage acoustic signal and the digital wire breakage acoustic signal, wherein the analog wire breakage acoustic signal and the digital wire breakage acoustic signal are connected through a zero ohm resistor or a magnetic bead.

8. The system for collecting the acoustic signal of the wire breaking of the bridge cable according to claim 1, wherein the initial wire breaking acoustic signal is collected by a resonant sensor, and the resonant sensor adopts a SR40M narrow band sensor, a SR150M medium band sensor and a WG500 wide band sensor with center frequencies of 40KHz, 150KHz and 500KHz respectively.

9. The system for acquiring the acoustic signal of the broken wire of the bridge cable according to claim 1, wherein the filter circuit adopts a second-order Butterworth low-pass filter.

10. A bridge inhaul cable broken wire sound signal acquisition method is characterized by comprising the following steps:

after the received initial filament breaking sound signal is subjected to amplification processing and filtering processing by adopting an amplifying circuit and a filtering circuit, a digital filament breaking sound signal is obtained by an analog-to-digital conversion circuit;

storing the digital broken filament sound signals by adopting an FIFO memory, and sending the digital broken filament sound signals to an upper computer through a gigabit Ethernet module by the FIFO memory;

and verifying the digital broken-wire sound signal transmitted by the gigabit Ethernet module by adopting a cyclic redundancy check code.

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