CN112235864A - Timing drift resistant time synchronization method and related product - Google Patents

Timing drift resistant time synchronization method and related product Download PDF

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CN112235864A
CN112235864A CN202011107980.7A CN202011107980A CN112235864A CN 112235864 A CN112235864 A CN 112235864A CN 202011107980 A CN202011107980 A CN 202011107980A CN 112235864 A CN112235864 A CN 112235864A
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nfft
time domain
frequency domain
length
nodes
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CN112235864B (en
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胡磊
桂竟晶
谭舒
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Unisoc Chongqing Technology Co Ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
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Abstract

The embodiment of the application provides a time synchronization method for resisting timing drift and a related product, wherein the method comprises the following steps: reconstructing p groups of local main synchronous time domain signals with set lengths; after zero padding is carried out on the tail of p groups of local main synchronous time domain signals, NFFT point FFT conversion is carried out to obtain p groups of frequency domain signals with the length of NFFT; and respectively carrying out cyclic shift on the p groups of frequency domain signals with the length of NFFT to obtain local frequency domain signals after frequency offset pre-correction. The technical scheme provided by the application has the advantages of improving the precision of time synchronization and improving the quality of communication.

Description

Timing drift resistant time synchronization method and related product
Technical Field
The present application relates to the field of communications processing technologies, and in particular, to a timing drift resistant time synchronization method and a related product.
Background
For a low-cost crystal oscillator, the frequency deviation is generally about + -10ppm, for a Communication system with a carrier frequency of 2.6GHz, the initial maximum frequency deviation of the crystal oscillator is 26kHz, for a deep coverage scenario which is supported by eMTC (enhanced Machine-Type Communication), the signal quality SNR (signal to noise ratio) received by a terminal may reach-18 db at least, in order to improve the estimation capability of the terminal timing synchronization, the timing estimation needs to consider the accumulation of multi-sample signals, and when the multi-sample signals are accumulated, the influence caused by timing drift due to large frequency deviation needs to be solved.
Under the condition of large frequency deviation, the timing position of data received continuously for a long time has drift, and the drift can influence the precision of time synchronization, thereby influencing the communication quality.
Disclosure of Invention
The embodiment of the application discloses a time synchronization method for resisting timing drift and a related product, wherein the peak-to-average ratio of position nodes is obtained by processing received time domain data with set duration, the number of effective nodes is judged according to the peak-to-average ratio and a preset threshold, and a time synchronization strategy is determined according to the number, so that the time synchronization precision is improved, and the communication quality is improved.
In a first aspect, a method for timing synchronization with timing drift resistance is provided, which includes the following steps:
reconstructing a p-group set length local master synchronization time domain signal LPssp,k，p＝0,1,2；
After zero padding is carried out on the tail part of p groups of local main synchronous time domain signals, NFFT point FFT (fast Fourier transform) is carried out to obtain p groups of frequency domain signals LPssF with the length of NFFTp,k；
Respectively carrying out cyclic shift on p groups of frequency domain signals with the length of NFFT to obtain local frequency domain signals after frequency offset pre-correction
Figure BDA0002726971310000011
User Equipment (UE) receives time domain data with preset duration, the received time domain data and local frequency domain signals
Figure BDA0002726971310000012
Respectively carrying out cyclic shift correlation to obtain a plurality of correlation power value sequences
Figure BDA0002726971310000013
Calculating a received signal strength indication RSSI value RSSI (k) of the received time domain data;
sequence a plurality of related power values
Figure BDA0002726971310000021
Corresponding array for accumulating correlation power to multiple samples
Figure BDA0002726971310000022
Accumulating the RSSI (k) into a multi-sample accumulated AccuRSSI;
obtaining
Figure BDA0002726971310000023
M distinguishable location nodes of medium RSSI normalized peak power strength
Figure BDA0002726971310000024
Computing
Figure BDA0002726971310000025
Peak to average ratio of
Figure BDA0002726971310000026
According to all nodes
Figure BDA0002726971310000027
With a predetermined validity threshold AbThsJudging the number N of effective nodes in all nodes according to the relation between the effective nodesdec；
According to said NdecA time synchronization strategy is determined that is resistant to timing drift.
In a second aspect, a UE is provided, the UE comprising:
a reconstruction unit for reconstructing the p groups of local master synchronization time domain signals LPss with the set lengthp,k，p＝0,1,2；
A processing unit, configured to perform NFFT point FFT after zero padding on p groups of local primary synchronization time domain signals to obtain p groups of frequency domain signals LPssF with NFFT lengthp,k(ii) a Respectively carrying out cyclic shift on p groups of frequency domain signals with the length of NFFT to obtain local frequency domain signals after frequency offset pre-correction
Figure BDA0002726971310000028
The communication unit is used for receiving time domain data with a preset time length;
a processing unit for receiving the time domain data and local frequency domain signal
Figure BDA0002726971310000029
Respectively carrying out cyclic shift correlation to obtain a plurality of correlation power value sequences
Figure BDA00027269713100000210
Calculating a received signal strength indication RSSI value RSSI (k) of the received time domain data; sequence a plurality of related power values
Figure BDA00027269713100000211
Corresponding array for accumulating correlation power to multiple samples
Figure BDA00027269713100000212
Accumulating the RSSI (k) into a multi-sample accumulated AccuRSSI; obtaining
Figure BDA00027269713100000213
M distinguishable location nodes of medium RSSI normalized peak power strength
Figure BDA00027269713100000214
Computing
Figure BDA00027269713100000215
Peak to average ratio of
Figure BDA00027269713100000216
According to all nodes
Figure BDA00027269713100000217
With a predetermined validity threshold AbThsJudging the number N of effective nodes in all nodes according to the relation between the effective nodesdec(ii) a According to said NdecDetermining time synchronization against timing driftAnd (4) strategy.
In a third aspect, there is provided a terminal comprising a processor, a memory, a communication interface, and one or more programs stored in the memory and configured to be executed by the processor, the programs comprising instructions for performing the steps of the method of the first aspect.
In a fourth aspect, a computer-readable storage medium is provided, storing a computer program for electronic data exchange, wherein the computer program causes a computer to perform the method of the first aspect.
In a fifth aspect, there is provided a computer program product, wherein the computer program product comprises a non-transitory computer readable storage medium storing a computer program operable to cause a computer to perform some or all of the steps as described in the first aspect of an embodiment of the present application. The computer program product may be a software installation package.
In a sixth aspect, a chip system is provided, the chip system comprising at least one processor, a memory and an interface circuit, the memory, the transceiver and the at least one processor being interconnected by wires, the at least one memory having a computer program stored therein; the computer program, when executed by the processor, implements the method of the first aspect.
By implementing the embodiment of the application, the technical scheme of the application obtains the number of effective nodes after processing the time domain data with the preset time length, and then determines the time synchronization strategy of timing drift according to the number of the effective nodes, so that whether the time domain data with the preset time length is related to the existing multi-sample accumulation group or not can be distinguished, if not, the synchronous position detection is finished, namely the timing drift value of the time domain data with the preset time length is not accumulated to the existing multi-sample timing drift value, if so, the timing drift value of the time domain data with the preset time length is accumulated to the existing multi-sample timing drift value, and then the step is executed on the next sample, so that the time synchronization precision of the data received for a continuous long time is improved, and the communication quality is improved.
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The drawings used in the embodiments of the present application are described below.
Fig. 1 is a system architecture diagram of an example communication system provided by an embodiment of the present application;
fig. 2 is a schematic flowchart of a timing drift resistant time synchronization method according to an embodiment of the present application;
FIG. 3 is a flow chart illustrating a timing synchronization method against timing drift according to an embodiment of the present application;
fig. 4 is a schematic flow chart of a single-sample one-segment time domain signal sliding correlation implementation according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of a terminal according to an embodiment of the present application;
fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
The embodiments of the present application will be described below with reference to the drawings.
The term "and/or" in this application is only one kind of association relationship describing the associated object, and means that there may be three kinds of relationships, for example, a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" in this document indicates that the former and latter related objects are in an "or" relationship.
The "plurality" appearing in the embodiments of the present application means two or more. The descriptions of the first, second, etc. appearing in the embodiments of the present application are only for illustrating and differentiating the objects, and do not represent the order or the particular limitation of the number of the devices in the embodiments of the present application, and do not constitute any limitation to the embodiments of the present application. The term "connect" in the embodiments of the present application refers to various connection manners, such as direct connection or indirect connection, to implement communication between devices, which is not limited in this embodiment of the present application.
The technical solution of the embodiment of the present application may be applied to the example communication system 100 shown in fig. 1, where the example communication system 100 includes a terminal 110 and a network device 120, and the terminal 110 is communicatively connected to the network device 120.
The example communication system 100 may be, for example: a Global System for Mobile communications (GSM) System, a Code Division Multiple Access (CDMA) System, a Wideband Code Division Multiple Access (WCDMA) System, a General Packet Radio Service (GPRS), a Long Term Evolution (Long Term Evolution, LTE) System, an Advanced Long Term Evolution (LTE-a) System, a New Radio (NR) System, an Evolution System of an NR System, an LTE-over-unlicensed spectrum (LTE-U) System, an NR-over-unlicensed spectrum (NR-over-licensed spectrum) System, a Universal Mobile Telecommunications System (UMTS) System, or other next generation communication systems.
Generally, conventional Communication systems support a limited number of connections and are easy to implement, however, with the development of Communication technology, mobile Communication systems will support not only conventional Communication, but also, for example, Device-to-Device (D2D) Communication, Machine-to-Machine (M2M) Communication, Machine Type Communication (MTC), and Vehicle-to-Vehicle (V2V) Communication, and the embodiments of the present application can also be applied to these Communication systems. Optionally, the communication system in the embodiment of the present application may be applied to a Carrier Aggregation (CA) scenario, may also be applied to a Dual Connectivity (DC) scenario, and may also be applied to an independent (SA) networking scenario.
A terminal 110 in the embodiments of the present application may refer to a user equipment, an access terminal, a subscriber unit, a subscriber station, a mobile station, a remote terminal, a mobile device, a user terminal, a wireless communication device, a user agent, or a user device. The terminal may also be a cellular phone, a cordless phone, a Session Initiation Protocol (SIP) phone, a Wireless Local Loop (WLL) station, a Personal Digital Assistant (PDA), a handheld device with wireless communication function, a computing device or other processing device connected to a wireless modem, a relay device, a vehicle-mounted device, a wearable device, a terminal in a future 5G network or a terminal in a future evolved Public Land Mobile Network (PLMN), and the like, which are not limited in this embodiment.
The eMTC is an Internet of things technology based on LTE evolution and aims to meet the requirements of Internet of things equipment based on LTE carriers. The eMTC is deployed based on a cellular network, supports the peak rate of the maximum 1Mbps of the uplink and the downlink, belongs to the rate in the Internet of things, and can be directly accessed to the LTE network by supporting the radio frequency and the baseband bandwidth of 1.4 MHz.
eMTC possesses four basic capabilities of LPWA: the method has the advantages that firstly, the coverage is wide, and the eMTC gains 15dB compared with the existing network under the same frequency band, so that the deep coverage capability of the LTE network is greatly improved; secondly, the capacity of supporting mass connection is achieved, and nearly 10 ten thousand connections can be supported by one sector of the eMTC; thirdly, the power consumption is lower, and the standby time of the eMTC terminal module can be as long as 10 years; fourth, the module cost is lower, and the large-scale connection will bring about the rapid reduction of the module chip cost.
The eMTC is a characteristic of LTE, the LTE design is basically adopted, and the eMTC frame structure is consistent with the LTE on the time domain structure; in a frequency domain structure, the 3GPP divides a system bandwidth into a plurality of NBs (non-overlapping 6 PRBs), scheduling of eMTC UEs is limited by the NBs and cannot be scheduled across the NBs, and different eMTC UEs may share resources of one NB.
For FDD/normal CP mode, SSS symbols occur in the 6 th OFDM symbol of subframe 0 and subframe 5, PSS occurs in the 7 th OFDM symbol of subframe 0 and subframe 5; for FDD/extended CP mode, SSS symbols occur in the 5 th OFDM symbol of subframe 0 and subframe 5, PSS occurs in the 6 th OFDM symbol of subframe 0 and subframe 5; for TDD mode, whether normal CP or extended CP, SSS symbols occur on the last OFDM of subframe 0 and subframe 5, PSS on the 3 rd OFDM symbol of subframe 1 and subframe 7. The UE initially synchronizes with the two synchronization symbols.
The primary synchronization signal detection is used as the first step of cell search, and is the first synchronization process carried out under the condition of no prior information, and has a crucial influence on the whole downlink synchronization performance, and the primary synchronization signal is composed of three Zadoff-Chu (ZC) sequences with the length of 62, and has good autocorrelation and cross-correlation. Common implementation methods include two major categories, frequency domain correlation and time domain correlation; in the downlink signal reception, in the initial synchronization stage, the receiver has not acquired the frequency offset in the received signal and the channel state experienced by the user, so that, to ensure better timing synchronization performance, the timing method needs to have the following characteristics: is insensitive to frequency offset; normal operation can still be guaranteed at lower signal-to-noise ratios. The influence of frequency deviation is reduced through pre-frequency deviation correction and sectional correlation, and the anti-noise capability is improved through the multiple accumulation of the correlation of the main synchronous signals.
The technical scheme of the application also reduces the influence of frequency deviation on the reduction of the main synchronizing signal correlation through pre-frequency deviation correction, the detection capability under weak signals is improved through the multiple accumulation of the main synchronizing signal correlation, in order to support the eMTC deep coverage capability, the minimum value of SINR required to be supported by the terminal UE is about-18 db, the data of hundreds of ms needs to be continuously received for the detection of the main synchronizing signal, under the large frequency deviation, the data received continuously for a long time, the timing position has drift, and the related power values of the main synchronizing signals of multiple samples cannot be directly added.
Referring to fig. 2, fig. 2 provides a timing synchronization method against timing drift, which may be implemented under the network architecture shown in fig. 1 and may be performed by an eMTC-like terminal, and as shown in fig. 2, the method includes the following steps:
step S200, reconstructing a local master synchronization time domain signal LPss with p groups of set lengthp,k，p＝0,1,2；
Step S201, after zero padding is carried out on the tail of p groups of local main synchronous time domain signals, NFFT point FFT conversion is carried out to obtain p groups of frequency domain signals LPssF with NFFT lengthp,k；
Step S202Respectively carrying out cyclic shift on p groups of frequency domain signals with the length of NFFT to obtain local frequency domain signals after frequency offset pre-correction
Figure BDA0002726971310000061
Step S203, the UE receives the time domain data with the preset duration, the received time domain data and the local frequency domain signal
Figure BDA0002726971310000062
Respectively carrying out cyclic shift correlation to obtain a plurality of correlation power value sequences
Figure BDA0002726971310000063
The time domain data with the predetermined duration may specifically be time domain data of 5ms plus 1 OFDM symbol. The plurality of related power value sequences
Figure BDA0002726971310000064
The number of the frequency offset intervals is related to the number of the frequency offset intervals, the size of the frequency offset intervals can be determined by pre-configuration, and the number of the frequency offset intervals specifically can be as follows: the number of frequency offset intervals spanned by the frequency domain signal for each NFFT. I.e. the above-mentioned plurality of sequences of correlation power values
Figure BDA0002726971310000065
The number of (c) may be:
Figure BDA0002726971310000066
wherein
Figure BDA0002726971310000067
A fractional number is tried for frequency offset.
Step S204, calculating a received signal strength indicator RSSI value (RSSI) (k) of the received time domain data;
Figure BDA0002726971310000068
m in the above formula may be the number of the accumulation nodes, where k is 0, 1., NFFT-OverLapLen-1, and OverLapLen is the length of the down-sampled primary synchronization signal (specifically, may be 1 OFDM symbol).
Step S205, a plurality of correlation power value sequences
Figure BDA0002726971310000071
Corresponding array for accumulating correlation power to multiple samples
Figure BDA0002726971310000072
Accumulating the RSSI (k) into a multi-sample accumulated AccuRSSI;
step S206, obtaining
Figure BDA0002726971310000073
M distinguishable location nodes of medium RSSI normalized peak power strength
Figure BDA0002726971310000074
Step S207, calculate
Figure BDA0002726971310000075
Peak to average ratio of
Figure BDA0002726971310000076
Step S208, according to all nodes
Figure BDA0002726971310000077
With a predetermined validity threshold AbThsJudging the number N of effective nodes in all nodes according to the relation between the effective nodesdec；
Step S209, according to the NdecA time synchronization strategy is determined that is resistant to timing drift.
According to the technical scheme, the time domain data with the preset time length is processed to obtain the number of effective nodes, and then the time synchronization strategy of timing drift is determined according to the number of the effective nodes, so that whether the time domain data with the preset time length is related to an existing multi-sample accumulation group or not can be distinguished, if not, synchronization position detection is finished, namely, the timing drift value of the time domain data with the preset time length is not accumulated to the existing timing drift value of multiple samples, if so, the timing drift value of the time domain data with the preset time length is accumulated to the existing timing drift value of the multiple samples, and then the step shown in figure 2 is executed on the next sample, so that the time synchronization precision of the data received for a continuous long time is improved, and the communication quality is improved.
In an optional scheme, the implementation method of step S209 may specifically include:
if N is presentdec>If the value is 1, ending the synchronous position detection; at this time, the timing drift values of the time domain data with the preset duration are determined to be irrelevant, and are not accumulated to the existing timing drift values of multiple samples.
If N is presentdecIf the received sample number is less than the preset maximum sample number, continuing the synchronization processing of the next sample; and if the correlation is determined, accumulating the timing drift value of the time domain data with the preset time length to the existing timing drift value of the multiple samples.
If N is presentdecIf the number of received samples is equal to the preset maximum number of samples, the synchronous position detection is finished, and the timing synchronization detection fails. It is determined that the sync detection fails at this time.
In an optional scheme, the p groups of frequency domain signals with the length of NFFT are respectively subjected to cyclic shift to obtain local frequency domain signals after frequency offset pre-correction
Figure BDA0002726971310000078
The method specifically comprises the following steps:
the frequency deviation pre-correction is carried out on the time domain signals with the p groups of length NFFT, and the signals are obtained by calculation according to the formula 1
Figure BDA0002726971310000079
Wherein freqoff (f)0) Is f at0Frequency offset value corresponding to each frequency offset branch, configuring freqoff (f)o) Local primary synchronization frequency domain signal LPssF with length NFFT point of 0p,kOther freqoff (f)o) Is synchronized with the signal passing pair
Figure BDA00027269713100000710
Cyclic shift to realize
Figure BDA0002726971310000081
In an alternative, the received time domain data is associated with a local frequency domain signal
Figure BDA0002726971310000082
Respectively carrying out cyclic shift correlation to obtain a plurality of correlation power value sequences
Figure BDA0002726971310000083
The method specifically comprises the following steps:
dividing received time domain data into N by sliding window length NFFTrSegments, each segment receiving a time domain signal of TempReci,k
TempReci,kObtaining an NFFT point receiving frequency domain signal after NFFT point FFT point transformation
The NFFT point receiving frequency domain signal is subjected to conjugate multiplication with a local main synchronization frequency domain signal, then NFFT point IFFT transformation is carried out, and finally correlation values are subjected to
Figure BDA0002726971310000084
Power is calculated to obtain the related power sequence
Figure BDA00027269713100000820
In an alternative scheme, the plurality of correlation power value sequences
Figure BDA0002726971310000085
Corresponding array for accumulating correlation power to multiple samples
Figure BDA0002726971310000086
The method specifically comprises the following steps:
timing drift attempt value according to each frequency deviation branch
Figure BDA0002726971310000087
Calculating timing drift values corresponding to different sample times
Figure BDA0002726971310000088
Then to
Figure BDA0002726971310000089
Performing cyclic shift;
the related power value sequence after cyclic shift is processed
Figure BDA00027269713100000810
Is accumulated into a multi-sample accumulated correlation power array.
In an alternative arrangement, the obtaining is performed
Figure BDA00027269713100000811
M distinguishable position nodes with strongest RSSI normalized peak power
Figure BDA00027269713100000812
Accumulated correlation power value for each frequency offset branch
Figure BDA00027269713100000813
Performing point-by-point RSSI normalization to find out the normalized peak power of each frequency offset branch corresponding to each NID2
Figure BDA00027269713100000814
Strongest M distinguishable location nodes
Figure BDA00027269713100000815
In an alternative arrangement, the node
Figure BDA00027269713100000816
Peak to average ratio of
Figure BDA00027269713100000817
The calculation specifically comprises the following steps:
Figure BDA00027269713100000818
wherein the content of the first and second substances,
Figure BDA00027269713100000819
wherein the content of the first and second substances,
α＝β1+β2；
wherein
Figure BDA0002726971310000091
Figure BDA0002726971310000092
noisewinlen is the noise window length, multipath _ R is the multipath window length;
i＝0,1...,M-1。
example one
An embodiment of the present application provides a timing drift resistant time synchronization method, which as shown in fig. 3, may specifically include:
receiving time domain data with the time duration of 5ms and 1 OFDM symbol, low-pass filtering and down-sampling the received data, wherein the data after low-pass filtering and down-sampling is r (N, the data length is N)fIn order to reduce the memory space of the memory during multi-sample accumulation, the received data is down-sampled by 32 times, the sampling frequency of the baseband signal is 30.72MHz, the sampling rate of the data after down-sampling is 0.96MHz, and N sets the sample number according to the SINR that the terminal UE needs to support.
Reconstructing 3 groups of local main synchronous signal time domain signals LPss with the length of 64 points (1 symbol is reduced to 64 points by 32 times)p,kP is 0,1,2, k is 0,1, 63, p represents the corresponding primary synchronization signal sequence, and then the 64-point primary synchronization signal sequence is followed by zero padding,zero padding number is (NFFT-64), NFFT (1024, 512, 2048 can all) point FFT is carried out, and local main synchronization frequency domain signal LPssF with the length being NFFT point is obtainedp,kK is 0, 1.., NFFT-1, NFFT is the sliding window length.
In order to reduce the influence of frequency deviation on the correlation of the master synchronization signal, the frequency deviation pre-correction is carried out on the local master synchronization signal,
Figure BDA0002726971310000093
to reduce computational complexity, Freqoff (f) may be stored (i.e., pre-configured)o) Local primary synchronization frequency domain signal LPssF with length NFFT point of 0p,kOther Freqoff (f)o) Can be synchronized by the pair of LPssFp,kIs realized by cyclic shift (f)0Representing the frequency of the local primary synchronization signal).
The length of the received data of a single sample (5ms +1 symbol) is 4864 (after downsampling), and the received data r (n) and the local primary synchronization signal are combined
Figure BDA0002726971310000101
Performing cyclic shift correlation to obtain a related power value sequence
Figure BDA0002726971310000102
Figure BDA0002726971310000103
Figure BDA0002726971310000104
A fractional number is tried for frequency offset. The flow of implementing the sliding correlation of the single-sample one-segment time domain signal is shown in fig. 4.
Taking a received time domain signal TempReci,k，TempReci,kR (i) (NFFT-OverLapLen) + k), OverLapLen being the length of the down-sampled primary synchronization signal (1 symbol), OverLapLen being 64,
Figure BDA0002726971310000105
i in the above formula is the number of the sections related to sliding;
TempReci,kand obtaining an NFFT point frequency domain signal after NFFT point FFT point transformation.
The NFFT point frequency domain signal is subjected to conjugate multiplication with a local main synchronous frequency domain signal, then NFFT point IFFT transformation is carried out, and finally correlation values are subjected to
Figure BDA0002726971310000106
Power is calculated to obtain the related power sequence
Figure BDA0002726971310000107
Figure BDA0002726971310000108
Figure BDA0002726971310000109
Constructing a sample correlated power sequence
Figure BDA00027269713100001010
k＝0,1,...,NFFT-OverLapLen-1
According to each frequency offset branch
Figure BDA00027269713100001011
Calculating timing drift values corresponding to different sample times
Figure BDA00027269713100001012
Then to
Figure BDA00027269713100001013
Performing cyclic shift processing; s is a sample label.
Figure BDA00027269713100001014
The RSSI value of the received data is calculated,
Figure BDA00027269713100001015
m adds up the number of points.
Correlated power after cyclic shift of each frequency offset branch
Figure BDA00027269713100001016
Accumulating to a multi-sample accumulated correlation power array
Figure BDA00027269713100001017
The RSSI (k) is accumulated into the AccuRSSI.
Accumulated correlation power value for each frequency offset branch corresponding to each NID2 (P2 of primary synchronization signal)
Figure BDA00027269713100001018
Performing point-by-point RSSI normalization, and finding out M distinguishable position nodes with strongest normalized peak power by each frequency offset branch corresponding to each NID2
Figure BDA00027269713100001019
Wherein, i is 0,1
RSSI normalized correlation power value of node k is
Figure BDA0002726971310000111
Computing node
Figure BDA0002726971310000112
The peak-to-average ratio of (a),
Figure BDA0002726971310000113
Figure BDA0002726971310000114
noisewinlen is the noise window length (length of one symbol) and multipath _ R is the multipath window length.
Presetting validity judgment thresholds AbTh according to different samplessFor all nodes
Figure BDA0002726971310000115
Making a validity judgment if
Figure BDA0002726971310000116
The detected position node is considered as an effective node, and the number of the nodes which over judge the threshold is assumed to be NdecIf N is presentdec>If 1, the sync position detection is ended (not accumulated), if N isdecIf the received sample number is less than the preset maximum sample number, continuing the processing of the next sample, and if N is equal to 0decIf the number of received samples is equal to the preset maximum number of samples, the synchronous position detection is finished, and the timing synchronization detection fails.
In the case of dividing the functional modules according to the corresponding functions, fig. 5 shows a schematic diagram of a user equipment UE, and as shown in fig. 5, the UE500 may include: a reconstruction unit 501, a processing unit 502 and a communication unit 503.
Among other things, processing unit 502 may be used to support the user equipment to perform steps 201, 202, 203, 204, 205, 206, 207, 208, 209, etc., described above, and/or other processes for the techniques described herein.
The reconstruction unit 501 may be used to support the user equipment in performing the above-described steps 200, etc., and/or other processes for the techniques described herein.
It should be noted that all relevant contents of each step related to the above method embodiment may be referred to the functional description of the corresponding functional module, and are not described herein again.
The electronic device or the terminal provided by the embodiment is used for executing the method shown in fig. 2, so that the same effect as the implementation method can be achieved.
In case of an integrated unit, the user equipment may comprise a processing module, a storage module and a communication module. The processing module may be configured to control and manage actions of the user equipment, and for example, may be configured to support the electronic equipment to perform the steps performed by the reconstructing unit 501, the processing unit 502, and the communication unit 503. The memory module may be used to support the electronic device in executing stored program codes and data, etc. The communication module can be used for supporting the communication between the electronic equipment and other equipment.
The processing module may be a processor or a controller. Which may implement or perform the various illustrative logical blocks, modules, and circuits described in connection with the disclosure. A processor may also be a combination of computing functions, e.g., a combination of one or more microprocessors, a Digital Signal Processing (DSP) and a microprocessor, or the like. The storage module may be a memory. The communication module may specifically be a radio frequency circuit, a bluetooth chip, a Wi-Fi chip, or other devices that interact with other electronic devices.
It should be understood that the interface connection relationship between the modules illustrated in the embodiments of the present application is only an exemplary illustration, and does not form a structural limitation on the user equipment. In other embodiments of the present application, the user equipment may also adopt different interface connection manners or a combination of multiple interface connection manners in the above embodiments.
Referring to fig. 6, fig. 6 is a terminal 60 according to an embodiment of the present application, where the terminal 60 includes a processor 601, a memory 602, and a communication interface 603, and the processor 601, the memory 602, and the communication interface 603 are connected to each other through a bus.
The memory 602 includes, but is not limited to, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), or a portable read-only memory (CD-ROM), and the memory 602 is used for related computer programs and data. The communication interface 603 is used for receiving and transmitting data.
The processor 601 may be one or more Central Processing Units (CPUs), and in the case that the processor 601 is one CPU, the CPU may be a single-core CPU or a multi-core CPU.
Processor 601 may include one or more processing units, such as: the processing unit may include an Application Processor (AP), a modem processor, a Graphics Processing Unit (GPU), an Image Signal Processor (ISP), a controller, a video codec, a Digital Signal Processor (DSP), a baseband processor, and/or a neural-Network Processing Unit (NPU), etc. Wherein the different processing units may be separate components or may be integrated in one or more processors. In some embodiments, the user equipment may also include one or more processing units. The controller can generate an operation control signal according to the instruction operation code and the time sequence signal to complete the control of instruction fetching and instruction execution. In other embodiments, a memory may also be provided in the processing unit for storing instructions and data. Illustratively, the memory in the processing unit may be a cache memory. The memory may hold instructions or data that have just been used or recycled by the processing unit. If the processing unit needs to reuse the instruction or data, it can be called directly from the memory. This avoids repeated accesses and reduces the latency of the processing unit, thereby improving the efficiency with which the user equipment processes data or executes instructions.
In some embodiments, processor 601 may include one or more interfaces. The interface may include an inter-integrated circuit (I2C) interface, an inter-integrated circuit audio (I2S) interface, a Pulse Code Modulation (PCM) interface, a universal asynchronous receiver/transmitter (UART) interface, a Mobile Industry Processor Interface (MIPI), a general-purpose input/output (GPIO) interface, a SIM card interface, a USB interface, and/or the like. The USB interface is an interface conforming to the USB standard specification, and may specifically be a Mini USB interface, a Micro USB interface, a USB Type C interface, or the like. The USB interface can be used for connecting a charger to charge the user equipment, and can also be used for transmitting data between the user equipment and peripheral equipment. The USB interface can also be used for connecting an earphone and playing audio through the earphone.
The processor 601 in the terminal 60 is configured to read the computer program code stored in the memory 602, and perform the following operations:
reconstructing a p-group set length local master synchronization time domain signal LPssp,k，p＝0,1,2；
After zero padding is carried out on the tail part of p groups of local main synchronous time domain signals, NFFT point FFT (fast Fourier transform) is carried out to obtain p groups of frequency domain signals LPssF with the length of NFFTp,k；
Respectively carrying out cyclic shift on p groups of frequency domain signals with the length of NFFT to obtain local frequency domain signals after frequency offset pre-correction
Figure BDA0002726971310000131
Receiving time domain data with preset time length, the received time domain data and local frequency domain signals
Figure BDA0002726971310000132
Respectively carrying out cyclic shift correlation to obtain a plurality of correlation power value sequences
Figure BDA0002726971310000133
Calculating a received signal strength indication RSSI value RSSI (k) of the received time domain data;
sequence a plurality of related power values
Figure BDA0002726971310000134
Corresponding array for accumulating correlation power to multiple samples
Figure BDA0002726971310000135
Accumulating RSSI (k) to multi-sample accumulationAccuRSSI;
obtaining
Figure BDA0002726971310000136
M distinguishable location nodes of medium RSSI normalized peak power strength
Figure BDA0002726971310000141
Computing
Figure BDA0002726971310000142
Peak to average ratio of
Figure BDA0002726971310000143
According to all nodes
Figure BDA0002726971310000144
With a predetermined validity threshold AbThsJudging the number N of effective nodes in all nodes according to the relation between the effective nodesdec；
According to said NdecA time synchronization strategy is determined that is resistant to timing drift.
All relevant contents of each scene related to the method embodiment may be referred to the functional description of the corresponding functional module, and are not described herein again.
The embodiment of the present application further provides a chip system, where the chip system includes at least one processor, a memory and an interface circuit, where the memory, the transceiver and the at least one processor are interconnected by a line, and the at least one memory stores a computer program; when the computer program is executed by the processor, the method flows shown in fig. 2 and fig. 3 are realized.
An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, and when the computer program runs on a network device, the method flows shown in fig. 2 and fig. 3 are implemented.
The embodiments of the present application also provide a computer program product, where when the computer program product runs on a terminal, the method flows shown in fig. 2 and fig. 3 are implemented.
The embodiments of the present application also provide a terminal, including a processor, a memory, a communication interface, and one or more programs, where the one or more programs are stored in the memory and configured to be executed by the processor, and the program includes instructions for executing steps in the methods of the embodiments shown in fig. 2 and 3.
The above description has introduced the solution of the embodiment of the present application mainly from the perspective of the method-side implementation process. It will be appreciated that the electronic device, in order to carry out the functions described above, may comprise corresponding hardware structures and/or software templates for performing the respective functions. Those of skill in the art will readily appreciate that the present application is capable of hardware or a combination of hardware and computer software implementing the various illustrative elements and algorithm steps described in connection with the embodiments provided herein. Whether a function is performed as hardware or computer software drives hardware depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
In the embodiment of the present application, the electronic device may be divided into the functional units according to the method example, for example, each functional unit may be divided corresponding to each function, or two or more functions may be integrated into one processing unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit. It should be noted that the division of the unit in the embodiment of the present application is schematic, and is only a logic function division, and there may be another division manner in actual implementation.
It should be noted that, for simplicity of description, the above-mentioned method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the present application is not limited by the order of acts described, as some steps may occur in other orders or concurrently depending on the application. Further, those skilled in the art will also appreciate that the embodiments described in the specification are presently preferred and that no acts or templates referred to are necessarily required by the application.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus may be implemented in other manners. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, the above-described division of the units is only one type of division of logical functions, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of some interfaces, devices or units, and may be an electric or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit may be stored in a computer readable memory if it is implemented in the form of a software functional unit and sold or used as a stand-alone product. Based on such understanding, the technical solution of the present application may be substantially implemented or a part of or all or part of the technical solution contributing to the prior art may be embodied in the form of a software product stored in a memory, and including several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the above-mentioned method of the embodiments of the present application. And the aforementioned memory comprises: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.
Those skilled in the art will appreciate that all or part of the steps in the methods of the above embodiments may be implemented by associated hardware instructed by a program, which may be stored in a computer-readable memory, which may include: flash Memory disks, Read-Only memories (ROMs), Random Access Memories (RAMs), magnetic or optical disks, and the like.

Claims (11)

1. A method of timing drift resistant time synchronization, said method comprising the steps of:
reconstructing a p-group set length local master synchronization time domain signal LPssp,k，p＝0,1,2；
After zero padding is carried out on the tail part of p groups of local main synchronous time domain signals, NFFT point FFT (fast Fourier transform) is carried out to obtain p groups of frequency domain signals LPssF with the length of NFFTp,k；
Respectively carrying out cyclic shift on p groups of frequency domain signals with the length of NFFT to obtain local frequency domain signals after frequency offset pre-correction
Figure FDA0002726971300000011
User Equipment (UE) receives time domain data with preset duration, the received time domain data and local frequency domain signals
Figure FDA0002726971300000012
Respectively performing cyclic shift correlation to obtain multiple correlationsSequence of power values
Figure FDA0002726971300000013
Calculating a received signal strength indication RSSI value RSSI (k) of the received time domain data;
sequence a plurality of related power values
Figure FDA0002726971300000014
Corresponding array for accumulating correlation power to multiple samples
Figure FDA0002726971300000015
Accumulating the RSSI (k) into a multi-sample accumulated AccuRSSI;
obtaining
Figure FDA0002726971300000016
M distinguishable location nodes of medium RSSI normalized peak power strength
Figure FDA0002726971300000017
Computing
Figure FDA0002726971300000018
Peak to average ratio of
Figure FDA0002726971300000019
According to all nodes
Figure FDA00027269713000000110
With a predetermined validity threshold AbThsJudging the number N of effective nodes in all nodes according to the relation between the effective nodesdec；
According to said NdecA time synchronization strategy is determined that is resistant to timing drift.
2. The method of claim 1, wherein said is dependent on said NdecDeterminingThe timing drift resistant time synchronization strategy specifically comprises:
if N is presentdec>If the value is 1, ending the synchronous position detection;
if N is presentdecIf the received sample number is less than the preset maximum sample number, continuing the synchronization processing of the next sample;
if N is presentdecIf the number of received samples is equal to the preset maximum number of samples, the synchronous position detection is finished, and the timing synchronization detection fails.
3. The method according to claim 1, wherein the p groups of frequency domain signals with length of NFFT are respectively circularly shifted to obtain local frequency domain signals after pre-correction of frequency offset
Figure FDA00027269713000000111
The method specifically comprises the following steps:
the frequency deviation pre-correction is carried out on the time domain signals with the p groups of length NFFT, and the signals are obtained by calculation according to the formula 1
Figure FDA00027269713000000112
Wherein freqoff (f)0) Is f at0Frequency offset value corresponding to each frequency offset branch, configuring freqoff (f)o) Local primary synchronization frequency domain signal LPssF with length NFFT point of 0p，kOther freqoff (f)o) Is synchronized with the signal passing pair
Figure FDA0002726971300000021
Cyclic shift to realize
Figure FDA0002726971300000022
4. The method of claim 1, wherein the received time domain data is associated with a local frequency domain signal
Figure FDA0002726971300000023
Respectively carrying out cyclic shift correlation to obtain a plurality of correlation power value sequences
Figure FDA0002726971300000024
The method specifically comprises the following steps:
dividing received time domain data into N by sliding window length NFFTrSegments, each segment receiving a time domain signal of TempReci,k
TempReci,kObtaining an NFFT point receiving frequency domain signal after NFFT point FFT point transformation
The NFFT point receiving frequency domain signal is subjected to conjugate multiplication with a local main synchronization frequency domain signal, then NFFT point IFFT transformation is carried out, and finally correlation values are subjected to
Figure FDA0002726971300000025
Power is calculated to obtain the related power sequence
Figure FDA0002726971300000026
5. The method of claim 1, wherein the sequence of multiple correlation power values
Figure FDA0002726971300000027
Corresponding array for accumulating correlation power to multiple samples
Figure FDA0002726971300000028
The method specifically comprises the following steps:
timing drift attempt value according to each frequency deviation branch
Figure FDA0002726971300000029
Calculating timing drift values corresponding to different sample times
Figure FDA00027269713000000210
Then to
Figure FDA00027269713000000211
Performing cyclic shift;
the related power value sequence after cyclic shift is processed
Figure FDA00027269713000000212
Is accumulated into a multi-sample accumulated correlation power array.
6. The method of claim 1, wherein the obtaining is performed
Figure FDA00027269713000000213
M distinguishable position nodes with strongest RSSI normalized peak power
Figure FDA00027269713000000214
Accumulated correlation power value for each frequency offset branch
Figure FDA00027269713000000215
Performing point-by-point RSSI normalization to find out the normalized peak work of each frequency offset branch corresponding to each NID2
Figure FDA00027269713000000216
M distinguishable position nodes with strongest rate
Figure FDA00027269713000000217
7. The method of claim 1, wherein the node is a master node
Figure FDA00027269713000000218
Peak to average ratio of
Figure FDA00027269713000000219
The calculation specifically comprises the following steps:
Figure FDA00027269713000000220
wherein the content of the first and second substances,
Figure FDA0002726971300000031
noisewinlen is the noise window length, multipath _ R is the multipath window length;
i＝0,1...,M-1。
8. a User Equipment (UE), the UE comprising:
a reconstruction unit for reconstructing the p groups of local master synchronization time domain signals LPss with the set lengthp,k，p＝0,1,2；
A processing unit, configured to perform NFFT point FFT after zero padding on p groups of local primary synchronization time domain signals to obtain p groups of frequency domain signals LPssF with NFFT lengthp,k(ii) a Respectively carrying out cyclic shift on p groups of frequency domain signals with the length of NFFT to obtain local frequency domain signals after frequency offset pre-correction
Figure FDA0002726971300000032
The communication unit is used for receiving time domain data with a preset time length;
a processing unit for receiving the time domain data and local frequency domain signal
Figure FDA0002726971300000033
Respectively carrying out cyclic shift correlation to obtain a plurality of correlation power value sequences
Figure FDA0002726971300000034
Calculating a received signal strength indication RSSI value RSSI (k) of the received time domain data; sequence a plurality of related power values
Figure FDA0002726971300000035
Corresponding array for accumulating correlation power to multiple samples
Figure FDA0002726971300000036
Accumulating the RSSI (k) into a multi-sample accumulated AccuRSSI; obtaining
Figure FDA0002726971300000037
M distinguishable location nodes of medium RSSI normalized peak power strength
Figure FDA0002726971300000038
Computing
Figure FDA0002726971300000039
Peak to average ratio of
Figure FDA00027269713000000310
According to all nodes
Figure FDA00027269713000000311
With a predetermined validity threshold AbThsJudging the number N of effective nodes in all nodes according to the relation between the effective nodesdec(ii) a According to said NdecA time synchronization strategy is determined that is resistant to timing drift.
9. A terminal comprising a processor, a memory, a communication interface, and one or more programs stored in the memory and configured to be executed by the processor, the programs comprising instructions for performing the steps of the method of any of claims 1-7.
10. A chip system, the chip system comprising at least one processor, a memory and an interface circuit, the memory, the transceiver and the at least one processor being interconnected by a line, the at least one memory having a computer program stored therein; the computer program, when executed by the processor, implements the method of any one of claims 1-7.
11. A computer-readable storage medium, in which a computer program is stored which, when run on a user equipment, performs the method of any one of claims 1-7.
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