CN112234436A

CN112234436A - Semiconductor device and method for manufacturing the same

Info

Publication number: CN112234436A
Application number: CN202011462300.3A
Authority: CN
Inventors: 董延; 李马惠; 潘彦廷; 刘钿
Original assignee: Shaanxi Yuanjie Semiconductor Technology Co ltd
Current assignee: Shaanxi Yuanjie Semiconductor Technology Co.,Ltd.
Priority date: 2020-12-14
Filing date: 2020-12-14
Publication date: 2021-01-15
Anticipated expiration: 2040-12-14
Also published as: CN112234436B

Abstract

The present application relates to a semiconductor device and a method of manufacturing the same. The semiconductor device includes a fourth substrate, a seventh confinement layer, a fourth active layer, an eighth confinement layer, and a fourth electron confinement layer. The surface of the fourth substrate is provided with a seventh confinement layer, a fourth active layer and an eighth confinement layer. The fourth electron confinement layer is disposed on the surface of the eighth confinement layer away from the fourth active layer. Or the fourth electron confinement layer is arranged between the eighth confinement layer and the fourth active layer. Wherein the forbidden band width of the fourth electron confinement layer is larger than that of the fourth active layer. And the forbidden band width of the fourth electron confinement layer is larger than that of the eighth confinement layer. The migration of electron can be effectively bound through the fourth electron binding layer, the electron overflow phenomenon is prevented, the recombination efficiency of electrons and holes in the fourth active layer is increased, and the light output power under the high-temperature working environment is further improved.

Description

Semiconductor device and method for manufacturing the same

Technical Field

The present disclosure relates to the field of semiconductor technologies, and in particular, to a semiconductor device and a method for manufacturing the same.

Background

Semiconductor devices utilize the special electrical properties of semiconductor materials to perform specific functions of electronic devices that can be used to generate, control, receive, convert, amplify signals, perform energy conversions, and the like. Meanwhile, with the improvement of the modulation rate of network systems such as data centers, telecommunication networks and the like, the modulation rate of related semiconductor devices reaches the upper limit, and a semiconductor device with higher modulation rate and higher light emitting power in a high-temperature working environment is required to be used as a light source in optical communication to meet the market demand.

However, the conventional semiconductor device is prone to electron overflow, which reduces the electron-hole recombination efficiency of the active region and cannot meet the market demand.

Disclosure of Invention

In view of the above, it is necessary to provide a semiconductor device and a method for manufacturing the same.

The present application provides a semiconductor device. The semiconductor device includes a fourth substrate, a seventh confinement layer, a fourth active layer, an eighth confinement layer, and a fourth electron confinement layer. The seventh confinement layer, the fourth active layer, and the eighth confinement layer are provided on a surface of the fourth substrate. The fourth electron confinement layer is disposed on a surface of the eighth confinement layer away from the fourth active layer. Or the fourth electron confinement layer is disposed between the eighth confinement layer and the fourth active layer. Wherein a forbidden bandwidth of the fourth electron confinement layer is larger than that of the fourth active layer. And the forbidden band width of the fourth electron confinement layer is larger than that of the eighth confinement layer.

In one embodiment, the fourth electron-binding layer comprises In_xAl_(1-x)And an As layer. The fourth active layer includes an InGaAsP layer. The eighth confinement layer comprises a P-type InGaAsP layer. Wherein, the In_xAl_(1-x)X in the As layer is greater than 0 and less than 1.

In one embodiment, the In_xAl_(1-x)The value of x in the As layer ranges from 0.4 to 0.6.

In one embodiment, the fourth electron-binding layer comprisesIn doped with iron element_xAl_(1-x)As layer or In doped with zinc element_xAl_(1-x)And an As layer.

In one embodiment, the In_xAl_(1-x)The doping concentration of iron element or zinc element in the As layer is 5e17cm^-3To 10e17cm^-3。

In one embodiment, the fourth electron-binding layer has a thickness of 20nm to 80 nm.

In one embodiment, the semiconductor device further comprises a seventh cladding layer, a plurality of fourth grating strips, and an eighth cladding layer. The seventh cladding layer is disposed between the fourth substrate and the seventh confinement layer. The plurality of fourth grating strips are arranged on the surface, far away from the eighth limiting layer, of the fourth electron confinement layer at intervals. Or, the plurality of fourth grating strips are arranged on the surface of the eighth limiting layer far away from the fourth electron confinement layer at intervals. The eighth cladding layer is disposed between the surfaces of the plurality of fourth grating bars and the gaps between the plurality of fourth grating bars. And the eighth cladding layer is provided with a ridge waveguide structure.

In one embodiment, the semiconductor device further includes a fourth ohmic contact layer, a seventh metal electrode layer, and an eighth metal electrode layer. The fourth ohmic contact layer is arranged on the surface of the ridge waveguide structure far away from the fourth grating strips. The seventh metal electrode layer is arranged on the surface, far away from the eighth cladding layer, of the fourth ohmic contact layer. The eighth metal electrode layer is arranged on the surface, far away from the seventh cladding layer, of the fourth substrate.

In one embodiment, the eighth metal electrode layer, the fourth substrate, the seventh cladding layer, the seventh confinement layer, the fourth active layer, the eighth confinement layer, the fourth electron confinement layer, the plurality of fourth grating strips, the eighth cladding layer, the fourth ohmic contact layer, and the seventh metal electrode layer form a matrix structure. The semiconductor device further comprises a fourth high-reflection coating layer and a fourth high-transmission coating layer. The fourth high-reflection coating layer is arranged on the first end face of the base structure parallel to the long axis of the fourth grating strip. The fourth high-transmission coating layer is arranged on the second end face of the substrate structure parallel to the long axis of the fourth grating strip. The first end face is arranged opposite to the second end face.

In one embodiment, the present application provides a method of manufacturing a semiconductor device, comprising the steps of:

providing a fourth substrate, and growing a seventh limiting layer and a fourth active layer on the surface of the fourth substrate;

growing an eighth limiting layer on the surface of the fourth active layer far away from the seventh limiting layer, and growing a fourth electron-confinement layer on the surface of the eighth limiting layer far away from the fourth active layer;

or growing the fourth electron confinement layer on a surface of the fourth active layer away from the seventh confinement layer, and growing the eighth confinement layer on a surface of the fourth electron confinement layer away from the fourth active layer;

the forbidden band width of the fourth electron confinement layer is greater than that of the fourth active layer, and the forbidden band width of the fourth electron confinement layer is greater than that of the eighth confinement layer.

In one embodiment, In is employed_xAl_(1-x)Growing the fourth electron-confinement layer on the surface of the eighth confinement layer away from the fourth active layer by the As material;

or In is used_xAl_(1-x)The As material grows the fourth electron-confinement layer on the surface of the fourth active layer far away from the seventh confinement layer;

wherein, In_xAl_(1-x)The value of x in the As material is in the range of 0.4 to 0.6.

In one embodiment, In doped with iron or zinc is used_xAl_(1-x)Growing the fourth electron-confinement layer on the surface of the eighth confinement layer away from the fourth active layer by the As material;

or In doped with iron or zinc_xAl_(1-x)As material in the fourth active layer away from the seventh confinementGrowing the fourth electron-confining layer on the surface of the layer;

wherein the doping concentration of iron element or zinc element is 5e17cm^-3To 10e17cm^-3。

In one embodiment, the fourth electron-confining layer has a stress of-0.2% Pa to 0.2% Pa when grown.

In one embodiment, the present application provides a semiconductor device. The semiconductor device comprises a seventh limiting layer, a fourth active layer and an eighth limiting layer which are arranged on the surface of the fourth substrate. The fourth electron confinement layer is arranged on the surface of the eighth confinement layer far away from the fourth active layer. Or the fourth electron confinement layer is disposed between the eighth confinement layer and the fourth active layer. The forbidden band width of the fourth electron confinement layer is greater than that of the fourth active layer, and the forbidden band width of the fourth electron confinement layer is greater than that of the eighth confinement layer. The fourth electron confinement layer comprises In doped with zinc element_0.5Al_0.5As layer, the doping concentration of zinc element is 7.5e17cm^-3And the thickness of the fourth electron confinement layer is 50nm, and the stress of the fourth electron confinement layer is 0.0% Pa.

In one embodiment, the present application provides a semiconductor device including a surface of the fourth substrate provided with a seventh confinement layer, a fourth active layer, and an eighth confinement layer. The fourth electron confinement layer is arranged on the surface of the eighth confinement layer far away from the fourth active layer. Or the fourth electron confinement layer is disposed between the eighth confinement layer and the fourth active layer. The forbidden band width of the fourth electron confinement layer is greater than that of the fourth active layer, and the forbidden band width of the fourth electron confinement layer is greater than that of the eighth confinement layer. The fourth electron-confining layer includes In doped with iron element_0.5Al_0.5As layer with doping concentration of iron element of 7.5e17cm^-3And the thickness of the fourth electron confinement layer is 50nm, and the stress of the fourth electron confinement layer is 0.0% Pa.

In the semiconductor device and the manufacturing method thereof, a forbidden bandwidth of the fourth electron confinement layer is larger than that of the fourth active layer and larger than that of the eighth confinement layer. The fourth electron confinement layer forms a conduction band energy level difference with respect to the fourth active layer or the eighth confinement layer. When electrons in the fourth active layer move to the eighth confinement layer, the fourth electron confinement layer can effectively confine electrons due to the large difference between the conduction band energy levels of the fourth electron confinement layer and the fourth active layer and the small electron energy, so that the electrons cannot escape from the fourth active layer. The difference between the conduction band energy levels of the fourth electron confinement layer and the eighth confinement layer is also large, and the electron energy is small, so that electrons are also confined. Even in a high-temperature environment, although the energy of electrons is increased, the fourth electron confinement layer and the fourth active layer and the eighth confinement layer respectively have conduction band energy level differences, electrons can still be effectively confined, and the electrons are confined in the fourth active layer.

The valence band energy level difference between the fourth electron confinement layer and the fourth active layer and between the fourth electron confinement layer and the eighth confinement layer is small relative to the valence band energy level of the holes, so that the probability of the holes entering the fourth active layer can be improved. Therefore, under the condition of an external current, the particle number of the particles of the fourth active layer is reversed, electrons of a low energy level are stimulated to transit to the high energy level, then the electrons are spontaneously transited from the high energy level to the low energy level to be compounded with holes, and meanwhile photons are emitted to generate light emitting power. The eighth confinement layer and the seventh confinement layer may act as graded layers of energy levels of the fourth active layer with respect to the fourth active layer. The fourth electron confinement layer is arranged above the eighth confinement layer or above the fourth active layer, so that electrons can be effectively confined in the fourth active layer, the recombination efficiency of the electrons and holes is improved, and the light output power is improved.

Therefore, through the fourth electron confinement layer set up in the eighth confinement layer is kept away from the surface of fourth active layer or the fourth electron confinement layer set up in the eighth confinement layer with between the fourth active layer, can effectual confinement electron's migration, prevent electron overflow phenomenon, increase the recombination efficiency of electron and hole in the fourth active layer, and then improve the luminous power under high temperature operational environment, make luminous power reach the requirement. Therefore, the semiconductor device provided by the application improves the electron injection efficiency of the quantum well and the radiation recombination efficiency of electrons and holes, so that the light extraction power of the semiconductor device at high temperature is improved. At this moment, through the semiconductor device that this application provided, need not adopt aspheric surface lens encapsulation to improve luminous power, reduced the encapsulation degree of difficulty. In addition, the TO tube cap with high price is not used in the packaging process of the semiconductor device, and the packaging cost is reduced.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments or the conventional technologies of the present application, the drawings used in the descriptions of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the following descriptions are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic cross-sectional structure of an embodiment after one-time epitaxy is completed.

Fig. 2 is a schematic cross-sectional structure diagram of a first active layer structure provided in an embodiment.

Fig. 3 is a schematic diagram of a process for forming a plurality of first grating strip structures according to an embodiment.

Fig. 4 is a schematic cross-sectional view of an embodiment of a double epitaxy process.

Fig. 5 is a schematic diagram of a process for forming a ridge waveguide structure according to an embodiment.

Fig. 6 is a schematic view of a long axis direction of a first grating strip provided in an embodiment.

FIG. 7 is a schematic cross-sectional view illustrating a finished end-face coating process in one embodiment.

Fig. 8 is a bandwidth distribution diagram at 85 ℃ obtained by different quantum well layers corresponding to different types of quantum wells in one embodiment.

Fig. 9 is a bandwidth distribution diagram at-40 ℃ obtained by different quantum well layers corresponding to different types of quantum wells in one embodiment.

Figure 10 is a graph of bandwidth distribution at 85 c obtained for different quantum well thicknesses in one embodiment.

FIG. 11 is a graph of bandwidth distribution at 85 ℃ obtained under different quantum well stresses in one embodiment.

FIG. 12 is a graph illustrating the bandwidth distribution at 85 ℃ obtained for different quantum well wavelength differences in one embodiment.

Fig. 13 is a schematic diagram illustrating the relationship between the gain and the wavelength of a laser material according to an embodiment.

FIG. 14 is a schematic diagram of the adjacent channel spacing for MWDM and LWDM provided in an embodiment.

Fig. 15 is a schematic cross-sectional view of a completed single epitaxy in one embodiment.

Fig. 16 is a schematic cross-sectional view of a second active layer structure provided in an embodiment.

Fig. 17 is a schematic diagram of a process for forming a plurality of second grating strip structures according to an embodiment.

Fig. 18 is a schematic cross-sectional view of an embodiment of a double epitaxy process.

Fig. 19 is a schematic diagram of a process for forming a ridge waveguide structure according to an embodiment.

Fig. 20 is a schematic view of a long axis direction of the second grating strips provided in an embodiment.

FIG. 21 is a schematic cross-sectional view illustrating a finished end-face coating process in one embodiment.

Fig. 22 is a diagram illustrating the bandwidth distribution at 50 ℃ of the LWDM channel 4 obtained for different quantum well types and different quantum well layer numbers in one embodiment.

Fig. 23 is a bandwidth distribution diagram at 50 ℃ of the LWDM channel 1 obtained by different quantum wells of different classes corresponding to different quantum well layer numbers in an embodiment.

Figure 24 is a graph of bandwidth distribution at 50 c obtained for different quantum well thicknesses in one embodiment.

FIG. 25 is a graph of bandwidth distribution at 50 ℃ obtained under different quantum well stresses in one embodiment.

FIG. 26 is a graph illustrating the bandwidth distribution at 50 ℃ obtained for different quantum well wavelength differences in one embodiment.

Fig. 27 is a schematic diagram of a laser chip according to an embodiment of the present application.

Fig. 28 is a schematic diagram illustrating the principle of gain coupling formed by the insulated grating layer according to an embodiment of the present application.

Fig. 29 is a schematic diagram of a laser chip according to another embodiment of the present application.

Fig. 30 is a schematic view illustrating a manufacturing process of an insulated grating layer according to an embodiment of the present application.

FIG. 31 is a graph comparing SMSR characteristics of different materials for the grating diffraction layers of examples 3-1 to 3-3.

FIG. 32 is a graph comparing the anti-reflection properties of different materials of the grating diffraction layers of examples 3-1 to 3-3.

FIG. 33 is a graph comparing SMSR characteristics of the Fe doping concentrations of the grating diffraction layers of examples 3-4 to 3-6.

FIG. 34 is a graph comparing the Fe doping concentration anti-reflection characteristics of the grating diffraction layers of examples 3-4 to 3-6.

FIG. 35 is a graph comparing SMSR characteristics of the thicknesses of the diffraction layers of examples 3-7 to 3-9.

FIG. 36 is a graph showing a comparison of the anti-reflection properties of the thicknesses of the diffraction layers of the gratings of examples 3-7 to 3-9.

FIG. 37 is a graph comparing doping and SMSR characteristics of the second cladding layers of examples 3-10 to 3-12.

FIG. 38 is a graph comparing the doping and anti-reflective properties of the second cladding layers of examples 3-10 to 3-12.

FIG. 39 is a graph comparing the second cladding thickness and SMSR characteristics of examples 3-13 to 3-15.

FIG. 40 is a graph comparing the second cladding thickness to the antireflective properties of examples 3-13 to 3-15.

Fig. 41 is a schematic cross-sectional structure diagram of a semiconductor device provided in an embodiment.

Fig. 42 is a schematic cross-sectional view of a semiconductor device provided in another embodiment.

Fig. 43 is a schematic view of a long axis direction of a fourth grating strip provided in an embodiment.

Fig. 44 is a schematic cross-sectional view of a part of a structure in a semiconductor device provided in an embodiment.

Fig. 45 is a schematic cross-sectional view of a part of a structure in a semiconductor device provided in an embodiment.

Fig. 46 is a schematic cross-sectional view of a semiconductor device provided in an embodiment.

FIG. 47 is a graph showing an electron concentration distribution of the fourth electron confinement layer grown and the fourth electron confinement layer not grown in one embodiment.

FIG. 48 is a graph of the luminous power at different currents for examples 4-1 to 4-3.

FIG. 49 is a graph of the luminous power at different currents for examples 4-4 to 4-6.

FIG. 50 is a graph of the luminous power at different currents for examples 4-7 to 4-9.

FIG. 51 is a graph of the luminous power at different currents for examples 4-10 to 4-12.

Fig. 52 is a schematic structural diagram of a laser chip provided in the present application.

Fig. 53 is a schematic structural diagram of a ninth confinement heterojunction layer provided in the present application.

Fig. 54 is a schematic structural view of a tenth confinement heterojunction layer provided in the present application.

Fig. 55 is a schematic illustration of the thickness of the ninth cladding layer, the thickness of the ninth confinement heterojunction layer and the thickness of the tenth confinement heterojunction layer provided herein.

Fig. 56 is a schematic diagram of the relationship between the different doping and the bandwidth of the ninth cladding layer provided in the present application.

Fig. 57 is a schematic diagram of different thicknesses of a ninth cladding layer in relation to a bandwidth provided herein.

Fig. 58 is a schematic diagram of the relationship between the different thicknesses and the bandwidths of the ninth confinement heterojunction layer provided in the present application.

Fig. 59 is a schematic diagram of the relationship between the different thicknesses and the bandwidths of the tenth confinement heterojunction layer provided in the present application.

Fig. 60 is a graph illustrating the relationship between the bandwidth and the doping concentration of a tenth confinement heterojunction layer provided in the present application.

Fig. 61 is a schematic diagram of a relationship between a gradient of a band gap width of a stack of a ninth confinement heterojunction layer and a tenth confinement heterojunction layer and a bandwidth provided in the present application.

Description of reference numerals:

200. a semiconductor device; 100. a laser chip; 110. a first substrate; 111. a first buffer layer; 120. a first confinement layer; 130. a first active layer; 131. a first quantum well layer; 132. a first barrier layer; 133. a second quantum well layer; 140 a second confinement layer; 150. a first cladding layer; 160. a first grating strip; 170. a second cladding layer; 180. a first ohmic contact layer; 190. a first passivation film; 101. a first metal electrode layer; 102. a second metal electrode layer; 103. a first highly reflective coating layer; 104. a first anti-reflective coating layer;

210. a second substrate; 211. a second buffer layer; 220. a third confinement layer; 230. a second active layer; 231. a third quantum well layer; 232. a second barrier layer; 233. a fourth quantum well layer; 240 a fourth confinement layer; 250. a third coating layer; 260. a second grating strip; 270. a fourth clad layer; 280. a second ohmic contact layer; 290. a second passivation film; 201. a third metal electrode layer; 202. a fourth metal electrode layer; 203. a second highly reflective coating layer; 204. a second antireflection coating layer;

310. a substrate; 312. a raised structure; 314. a high resistance state grating region; 316. a low resistance state grating region; 318. a gain region; 319. a gain-free region; 320. a first cladding layer; 321. a second cladding layer; 322. a third cladding layer; 330. a contact layer; 340. a third anti-reflection coating layer; 350. a third high reflection coating layer; 352. a third active layer; 354. a p-metal electrode; 356. an n-metal electrode; 360. an insulating grating layer; 370. a diffraction grating layer;

410. a fourth substrate; 420. a seventh clad layer; 430. a seventh confinement layer; 440. a fourth active layer; 450. an eighth confinement layer; 460. a fourth electron-binding layer; 407. a fourth grating strip; 480. an eighth cladding layer; 490. a fourth ohmic contact layer; 401. a seventh metal electrode layer; 402. an eighth metal electrode layer; 403. a fourth high reflection coating layer; 404. a fourth high transmission coating layer;

510. a fifth substrate; 520. a ninth clad layer; 530. a ninth confinement heterojunction layer; 531. a ninth sub-confinement heterojunction layer; 540. a fifth active layer; 550. a tenth confinement heterojunction layer; 551. a tenth confinement heterojunction layer; 560. a tenth clad layer; 570. a fifth ohmic contact layer; 501. a ninth metal electrode layer; 502. a tenth metal electrode layer; 503. a fifth highly reflective coating layer; 504. and a fifth anti-reflection coating layer.

Detailed Description

To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Embodiments of the present application are set forth in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application; for example, the first doping type may be made the second doping type, and similarly, the second doping type may be made the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

Spatial relational terms, such as "under," "below," "under," "over," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.

As used herein, the singular forms "a", "an" and "the" may include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises/comprising," "includes" or "including," etc., specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, in this specification, the term "and/or" includes any and all combinations of the associated listed items.

The design of a non-refrigeration industrial grade 25Gbps semiconductor laser, wherein the design and manufacturing technology of the refrigeration 25Gbps semiconductor laser are very mature abroad, if the performance of the laser needs to be further operated in the non-refrigeration industrial grade environment temperature ranging from-40 ℃ to 85 ℃, the bandwidth of the laser is reduced due to large temperature variation, and communication error codes are formed on transmission, so that the problem becomes the largest technical threshold of the product. The quantum well structure of the active region is optimized mainly through epitaxial structure design, so that the problem of high-temperature and low-temperature bandwidth degradation is solved, the product is operated at the ambient temperature of-40 ℃ to 85 ℃, and the bandwidth can have excellent performance of more than 18GHz without refrigeration.

Based on this, the present application provides a laser chip 100. The laser chip 100 includes a first active layer 130, and a first confinement layer 120 and a second confinement layer 140 respectively located on two opposite sides of the first active layer 130 and stacked with the first active layer 130. The first active layer 130 includes a first quantum well layer 131 and a second quantum well layer 133 disposed in the stacking direction, wherein a wavelength difference between the first quantum well layer 131 and the second quantum well layer 133 is 15nm to 30nm, the number of the first quantum well layers 131 is 5 to 9, and the number of the second quantum well layers 133 is 3 to 6.

Referring to fig. 1 and 2, a first confinement layer 120, a first active layer 130, and a second confinement layer 140 may be sequentially deposited on the first substrate 110. The first confinement layer 120, the first active layer 130 and the second confinement layer 140 may be made of aluminum indium gallium arsenide (AlInGaAs) materials.

Wherein the first active layer 130 includes two types of multiple quantum wells. One type of multiple quantum well is the first quantum well layer 131 and the other type of multiple quantum well is the second quantum well layer 133. The wavelength difference between the first quantum well layer 131 and the second quantum well layer 133 is 15nm to 30nm, the number of the first quantum well layers 131 is 5 to 9, and the number of the second quantum well layers 133 is 3 to 6. By setting the number of the first quantum well layers 131, the number of the second quantum well layers 133 and the wavelength difference between the first quantum well layers and the second quantum well layers, the first quantum well layer 131 structure can improve the operating bandwidth of the laser chip 100 in a high-temperature environment, the second quantum well layer 133 structure can improve the operating bandwidth of the laser chip 100 in a low-temperature environment, so that the laser chip 100 can operate in an environment temperature of-40 ℃ to 85 ℃, and when the laser chip is not cooled, the bandwidth can be ensured to be above 18GHz, the 25Gbps modulation rate requirement required by a 5G forward transmission system is met, and the high error code behavior of optical communication can be avoided.

In one embodiment, the first quantum well layer 131 has a thickness from 40A to 80A and the second quantum well layer 133 has a thickness from 40A to 80A. In the case that the number of the first quantum well layer 131 is 5 to 9 and the number of the second quantum well layer 133 is 3 to 6, the bandwidth at 85 ℃ can be more than 18GHz, and the design thickness is not difficult to adapt the device parameters using Metal-organic Chemical Vapor Deposition (MOCVD) technology in the epitaxial production process, and is suitable for mass production.

In one embodiment, the first active layer 130 further includes a first barrier layer 132, the first quantum well layer 131, and the second quantum well layer 133 are sequentially stacked along the stacking direction, the stress of the first quantum well layer 131 is +0.8% to +1.3%, the stress of the second quantum well layer 133 is +0.8% to +1.3%, and the stress of the first barrier layer 132 is-0.6% to-0.2%.

It is understood that the deposition sequence of the first quantum well layer 131 and the second quantum well layer 133 is not limited in particular, and the first quantum well layer 131 and the first barrier layer 132 may be deposited alternately on the first confinement layer 120, and then the second quantum well layer 133 and the first barrier layer 132 may be deposited alternately on the uppermost first barrier layer 132 (see fig. 2). Of course, the second quantum well layer 133 and the first barrier layer 132 may be deposited alternately on the first confinement layer 120, and then the first quantum well layer 131 and the first barrier layer 132 may be deposited alternately on the uppermost first barrier layer 132.

On one hand, the larger the stress of the quantum well or the potential barrier is, the more easily the lattice mismatch is generated in the epitaxial process, so that the quality of the wafer is degraded, and the yield and the characteristics are greatly reduced; on the other hand, the addition of the quantum well stress is beneficial to improving the differential quantum efficiency of the laser chip 100 and improving the bandwidth. In order to balance the contradiction between the addition of quantum well stress and lattice mismatch, reverse stress is added to a potential barrier adjacent to a stressed quantum well to be used as stress compensation, so that lattice mismatch is avoided; in the embodiment, under the condition that the compressive stress is added to the quantum well, the tensile stress of the adjacent barrier is simultaneously given to serve as stress compensation, so that the problem of lattice mismatch is avoided under the condition of a multi-layer quantum well and barrier stacking epitaxial process.

In one embodiment, the laser chip 100 further includes a first buffer layer 111, a first cladding layer 150, a plurality of first grating strips 160, and a second cladding layer 170.

The first buffer layer 111 is disposed on a surface of the first confinement layer 120 away from the first active layer 130. The first cladding layer 150 is disposed on a surface of the second confinement layer 140 away from the first active layer 130. The plurality of first grating bars 160 are disposed at intervals on the surface of the first cladding layer 150 away from the second confinement layer 140. The second cladding layer 170 is disposed on the surfaces of the plurality of first grating bars 160 and in the gaps between the plurality of first grating bars 160, and the second cladding layer 170 is provided with a ridge waveguide structure.

In this embodiment, the first buffer layer 111, the first cladding layer 150, and the second cladding layer 170 may be indium phosphide (InP) materials. The first cladding layer 150 and the second cladding layer 170 are both P-InP material, and the first buffer layer 111 is N-InP material. The first buffer layer 111 is disposed on the surface of the first substrate 110, and covers the first substrate 110 to perform a buffer function. In one embodiment, the plurality of first grating bars 160 includes In_1-xGa_xAs_yP_1-yAnd (3) a layer. Said In_1-xGa_xAs_yP_1-yThe value of x in the layer ranges from 0.05 to 0.32, and the value of y ranges from 0.05 to 0.69. In one can implementIn the embodiment (1), x =0.23 and y = 0.50. The second cladding layer 170 is disposed between the surfaces of the first grating bars 160 and the first grating bars 160, and covers the first grating bars 160 and fills gaps between the first grating bars 160. At this time, a large difference in refractive index is formed between the second cladding layer 170 and the plurality of first grating bars 160. The second cladding layer 170 is provided with a ridge waveguide structure, and has the advantages of high power, long-distance transmission and the like.

Referring to fig. 3 to 7, in an embodiment, the laser chip 100 further includes a first ohmic contact layer 180, a first metal electrode layer 101, and a second metal electrode layer 102. The first ohmic contact layer 180 is disposed on a surface of the ridge waveguide structure away from the plurality of first grating strips 160. The first metal electrode layer 101 is disposed on a surface of the first ohmic contact layer 180 away from the second cladding layer 170. The second metal electrode layer 102 is disposed on a surface of the first substrate 110 away from the first buffer layer 111. The first metal electrode layer 101 is a P-metal electrode layer. The second metal electrode layer 102 is an N-metal electrode layer. The material of the first ohmic contact layer 180 may be InGaAs material.

In one embodiment, the second metal electrode layer 102, the first substrate 110, the first buffer layer 111, the first confinement layer 120, the first active layer 130, the second confinement layer 140, the first cladding layer 150, the plurality of first grating strips 160, the second cladding layer 170, the first ohmic contact layer 180, and the first metal electrode layer 101 form a matrix structure (not labeled). The laser chip 100 further includes a first highly reflective coating 103 and a first anti-reflective coating 104. The first high-reflection coating layer 103 is arranged on the first end face of the base structure parallel to the long axis of the first grating strip. The first anti-reflective coating layer 104 is disposed on a second end surface of the base structure parallel to the long axis of the first grating strips. The first end face is arranged opposite to the second end face.

In this embodiment, the second metal electrode layer 102, the first substrate 110, the first buffer layer 111, the first confinement layer 120, the first active layer 130, the second confinement layer 140, the first cladding layer 150, the plurality of first grating strips 160, the second cladding layer 170, the first ohmic contact layer 180, and the first metal electrode layer 101 may be regarded as a single integral structure. As shown in fig. 7, the first high reflective coating layer 103 is provided on a first end surface of the base structure parallel to the long axis of the first grating bar, that is, a right end surface in fig. 7. The second end face is disposed opposite to the first end face, i.e., the left end face in fig. 7. The long axis direction of the first grating strips is an axis parallel to the length direction of the first grating strips, i.e., the direction shown in the right position in fig. 7. At this time, the second metal electrode layer 102, the first substrate 110, the first buffer layer 111, the first confinement layer 120, the first active layer 130, the second confinement layer 140, the first cladding layer 150, the plurality of first grating strips 160, the second cladding layer 170, the first ohmic contact layer 180, and the first metal electrode layer 101 are disposed between the first highly reflective plating layer 103 and the first anti-reflective plating layer 104.

Based on the same inventive concept, the present application provides a method for manufacturing a laser chip 100, comprising the following steps:

s10, providing a first substrate 110, and growing a first buffer layer 111 and a first confinement layer 120 on a surface of the first substrate 110;

s20, sequentially growing the first quantum well layer 131 and the first barrier layer 132 and the second quantum well layer 133 and the first barrier layer 132 alternately stacked on the surface of the first confinement layer 120 away from the first buffer layer 111 to generate the first active layer 130;

s30, growing a second confinement layer 140 on the surface of the first active layer 130 away from the first confinement layer 120;

wherein the wavelength difference between the first quantum well layer 131 and the second quantum well layer 133 is 15nm to 30nm, the number of the first quantum well layers 131 is 5 to 9, and the number of the second quantum well layers 133 is 3 to 6.

In this embodiment, the method for manufacturing the laser chip 100 adopts an MOCVD growth technique to sequentially grow the first buffer layer 111, the first confinement layer 120, the first active layer 130, and the second confinement layer 140 on the surface of the first substrate 110 from bottom to top. It is understood that the deposition sequence of the first quantum well layer 131 and the second quantum well layer 133 is not limited in particular, and the first quantum well layer 131 and the first barrier layer 132 may be deposited alternately on the first confinement layer 120, and then the second quantum well layer 133 and the first barrier layer 132 may be deposited alternately on the uppermost first barrier layer 132 (see fig. 2). Of course, the second quantum well layer 133 and the first barrier layer 132 may be deposited alternately on the first confinement layer 120, and then the first quantum well layer 131 and the first barrier layer 132 may be deposited alternately on the uppermost first barrier layer 132. The first confinement layer 120, the first active layer 130 and the second confinement layer 140 may be made of aluminum indium gallium arsenide (AlInGaAs) materials.

In the above embodiment, by setting the number of the first quantum well layers 131, the number of the second quantum well layers 133, and the wavelength difference between the two, the first quantum well layer 131 structure can improve the operating bandwidth of the laser chip 100 in a high temperature environment, and the second quantum well layer 133 structure can improve the operating bandwidth of the laser chip 100 in a low temperature environment, so that the laser chip 100 operates in an environment temperature of-40 ℃ to 85 ℃, and when the laser chip is in an uncooled condition, the bandwidth can be ensured to be above 18GHz, the 25Gbps modulation rate requirement required by a 5G fronthaul system is met, and the high error code behavior of optical communication can be avoided.

In one embodiment, the laser chip 100 is grown as follows: an indium phosphide layer (a first buffer layer 111), a first confinement layer 120, an aluminum indium gallium arsenide layer (a first active layer 130), a second confinement layer 140, an indium phosphide layer (a first cladding layer 150), indium gallium arsenide phosphide (InGaAsP, a plurality of first grating bars 160), and an indium phosphide layer (a second cladding layer 170) are sequentially grown on the surface of an InP first substrate 110 (also referred to as a wafer) from bottom to top by using an MOCVD method, so that the structure shown in fig. 1 is obtained.

The etching region is exposed through the photolithography and dry etching technology, that is, the top surface of the end face etching region is dry etched by using the rie (reactive Ion etching) technology, the second cladding layer 170 and the plurality of first grating bars 160 are etched from top to bottom, and the etching is stopped at the first cladding layer 150, so that the plurality of diffractive first grating bars are etched on the ingaasp material, and the structure shown in fig. 3 is obtained.

Referring to fig. 4, the second cladding layer 170 is grown as follows: the second cladding layer 170 and the first ohmic contact layer 180 are sequentially grown over the plurality of first grating bars 160 using the MOCVD growth technique. The second cladding layer 170 is an InP material, and the second cladding layer 170 completely covers and fills the plurality of etched first grating strips. The first ohmic contact layer 180 is InGaAs material to obtain a semi-finished wafer.

Referring to fig. 5, in order to effectively inject current into the active layer for electro-optic conversion, a ridge waveguide structure may be defined to confine current carriers and photons after the semi-finished wafer is obtained. And defining the ridge waveguide with the width of about 2 microns by utilizing a photoetching technology and a photomask, and then carrying out dry etching on the ridge waveguide to a plurality of first grating strips by utilizing an RIE (reactive ion etching) technology to obtain the ridge waveguide structure.

Referring to fig. 5 to 7, in an embodiment, after a layer of insulating first passivation film 190 of silicon dioxide or silicon nitride is formed on the structure surface by using a plasma enhanced chemical vapor deposition PECVD technique, the first passivation film 190 on the surface of the first ohmic contact layer 180 is etched and removed, and at this time, the first passivation film 190 only covers the surface of the region outside the ridge waveguide. Then plating a p-metal electrode layer (a first metal electrode layer 101) on the first ohmic contact layer 180, then thinning and polishing the back surface of the first substrate 110 of indium phosphide to 100 μm, and plating an n-metal electrode layer (a second metal electrode layer 102); and cutting the semi-finished wafer to obtain a chip semi-finished product, plating a first anti-reflection coating 104 on one end (the left side in the figure 7) of the chip semi-finished product, and plating a first high-reflection coating 103 on the opposite end (the right side in the figure 7), so that the process is completed, and obtaining the non-refrigeration industrial 25Gbps semiconductor chip.

In one embodiment, the present application provides the following specific 5 embodiments optimized for three types of structures in the active region. These three types of structures are, in epitaxial order, a first quantum well layer 131, a first barrier layer 132, and a second quantum well layer 133. Because the most serious part affecting the characteristics under the high-temperature and low-temperature operation is that the high-temperature bandwidth is easy to be degraded to less than 18GHz, the relation between the structural parameters of the active region and the high-temperature bandwidth is mainly optimized in the embodiments 1-1, 1-3, 1-4 and 1-5, and the low-temperature bandwidth is optimized in the embodiments 1-2; wherein, the Coupling Coefficient (Coupling Coefficient) of the laser chip 100 commonly used in the five embodiments is 100 cm^-1The cavity length is 150 μm, the ridge waveguide width is 2 μm, and the parameter setting is also within the commercial specification range of the general 25Gbps laser chip 100, wherein if the values of the coupling coefficient, the cavity length and the ridge waveguide width are changed, the trend of the influence on the bandwidth is consistent, and the result of the optimization of the embodiment on the five laser chips 100 is not influenced.

Examples 1 to 1

In this embodiment, the purpose of increasing the high-temperature bandwidth is achieved by optimizing the number of the first quantum well layers 131 in the active region, wherein four parameters are to be optimized, which are the number of the second quantum well layers 133, the thickness of the quantum wells, the stress of the quantum wells and the barriers, and the wavelength difference between the first quantum well layers 131 and the second quantum well layers 133, respectively, and these four parameters are optimized and designed in embodiments 1-2 to 1-5 one by one. In embodiment 1-1, the thickness of the quantum well is near the middle value of the available value range (i.e., thickness 70 a), the stress between the quantum well and the potential barrier is near the middle value of the available value range (i.e., compressive stress +1.2% of the quantum well and tensile stress-0.6% of the potential barrier), the wavelength difference between the two types of quantum wells is near the middle value of the available value range (i.e., 20 nm), and the above preliminary parameters are set, which are mainly considered as settings that an epitaxial device of a general commercial product is easily adaptable in production, and the parameters are finely adjusted before and after the production is performed on the premise that the production is easy, so that the production difficulty is reduced; according to the optimization result, as shown in fig. 8, when the number of the first quantum well layers 131 is in the range of 5 to 9, the bandwidth of most of the laser chips 100 can be greater than 18GHz at 85 ℃. Wherein, when the number of the first quantum well layers 131 is 7 and the number of the second quantum well layers 133 is 5, the high bandwidth value is 18.9 GHz. Therefore, the number of the first quantum well layers 131 is 7, which is the optimum value in this embodiment.

Examples 1 to 2

In this embodiment, the number of the second quantum well layers 133 in the active region is optimized to ensure that the bandwidth at-40 ℃ is greater than 18GHz, as shown in fig. 9, on the premise that the number of the first quantum well layers 131 in embodiment 1-1 is 7, when the number of the second quantum well layers 133 is 3 to 6, the requirement of the bandwidth at 18GHz can be satisfied. Moreover, when the number of the first quantum well layers 131 is 6 and the number of the second quantum well layers 133 is 3 to 6, the requirement can also be satisfied. Since the bandwidth at-40 ℃ is gradually increased as the number of the second quantum well layers 133 is increased, bandwidth value saturation is gradually formed when the number of the second quantum well layers 133 is increased to 5 to 6 layers. Therefore, the number of second quantum well layers 133 is the optimum value in this embodiment when 5 to 6 layers are provided.

Examples 1 to 3

In this embodiment, the individual thickness of all quantum wells in the active region is optimized to ensure that the bandwidth at 85 ℃ is greater than 18GHz, as shown in fig. 10, the best value results of embodiments 1-2 are taken: on the premise of the design that the number of the first quantum well layers 131 is 7 and the number of the second quantum well layers 133 is 5, when the value range of the thickness of the quantum well is from 40A to 80A, the bandwidth at 85 ℃ can be larger than 18 GHz. When the thickness of the quantum well is 60 a, the laser chip 100 has a bandwidth performance of 19.3GHz, and the thickness of the quantum well is not difficult to adapt to parameters of MOCVD equipment in an epitaxial production process, so that the laser chip is suitable for mass production.

Examples 1 to 4

In the embodiment, the stress of all quantum wells and barriers in the active region is optimized to ensure that the bandwidth at 85 ℃ is more than 18 GHz; generally speaking, the larger the stress of a quantum well or a potential barrier is, the more easily the lattice mismatch is generated in the epitaxial process, which causes the quality degradation of a wafer, and the yield and the characteristics are greatly reduced, and the addition of the quantum well stress is helpful for improving the differential quantum efficiency of the laser chip 100, improving the bandwidth, balancing the contradiction between the addition of the quantum well stress and the lattice mismatch, and generally adding reverse stress to the potential barrier adjacent to the stressed quantum well as compensating the stress to avoid the lattice mismatch; in the embodiment, under the stress added to the quantum well, the tensile stress of the adjacent potential barrier is also given as stress compensation so as to realize the problem of no lattice mismatch under the multilayer quantum well and potential barrier stacking epitaxial process; as shown in fig. 11, the best value results of examples 1 to 3 are taken: on the premise that the number of the first quantum well layers 131 is 7, the number of the second quantum well layers 133 is 5 and the thickness of the quantum well is 60A, when the value range of the quantum well stress is +0.8% to +1.3%, the value range of the barrier stress is-0.6% to-0.2%, and the requirements that the bandwidth is larger than 18GHz at 85 ℃ can be met. Wherein, when the quantum well stress is +1.3% and the barrier stress is-0.6%, the laser chip 100 has a bandwidth performance of 19.4 GHz. It can also be observed from the results of fig. 11 that the bandwidth requirement at 85 c is met at-0.8% barrier stress, but a significant drop in bandwidth relative to-0.6% barrier stress is considered. Moreover, considering the stress error condition of the actual MOCVD epitaxy during adjustment, the tolerance of the production quality is easily reduced. Therefore, it is not recommended to take-0.8% as a suitable value for barrier stress.

Examples 1 to 5

In the embodiment, the difference value of the energy system wavelength of the materials of the two types of quantum wells in the active region is optimized to ensure that the bandwidth at 85 ℃ is more than 18 GHz; the best value results of the examples 1 to 4 are taken as follows: the design that the number of the first quantum well layers 131 is 7, the number of the second quantum well layers 133 is 5, the thickness of the quantum well is 60 a, the stress of the quantum well is +1.3%, and the barrier stress is-0.6% is assumed as a premise. As shown in fig. 12, the quantum well wavelength difference defined by the horizontal axis represents the difference of the wavelength of the first quantum well layer 131 minus the wavelength of the second quantum well layer 133. When the wavelength difference is 15nm to 30nm, the bandwidth at 85 ℃ is more than 18 GHz. With an optimal quantum well wavelength difference value of 25nm, the laser chip 100 has a bandwidth representation of 19.7 GHz.

The five embodiments described above are embodied under the cost limit of commercial mass production, starting from the epitaxial design of the chip, and ensuring the feasibility of the non-refrigeration working temperature grade product, and the consideration of each working procedure and the optimization design of the embodiments all have the key commercial requirements of the 5G forwarding system and the data center system: the basic principle of localization, low cost, high speed, easy mass production and no sacrifice of product quality is favorable for promoting the process of commercial popularization of a 5G system and a data center system.

In general, because the gap between adjacent channels is large (the nearest gap between adjacent channels is 7 nm), in consideration of commercial yield, it is difficult to design a single wafer structure while providing 2 channels for MWDM, and the main bottleneck is degradation of bandwidth, which is described below with reference to a laser as an example, for the problem of bandwidth: the bandwidth of the laser is most sensitive to the physical parameter of the Differential Gain (Differential Gain) of the laser, the larger the value is, the higher the bandwidth is, the more the laser can work at high speed, and the communication quality is guaranteed, and the Differential Gain is respectively related to two design values, one is a wavelength channel, and the other is a wavelength position of a Material Gain Peak (Material Gain Peak), as shown in fig. 13, the upper graph shows that when the current density is increased (the current density is 1< the current density is 2< the current density is 3), different Material Gain curves are corresponded, when the current is added to the laser at the beginning, the current density is small, the current density is increased, the Material Gain is increased rapidly, when the current is increased to a critical Gain height represented by a horizontal broken line in the graph, the Material Gain of the laser at the moment overcomes the internal loss, and the output of the laser begins to be increased rapidly, this is the principle of laser action. The position and size of the material gain peak are mainly related to the epitaxial structure, especially the quantum well structure of the active region. The position of the wavelength channel below fig. 13 is related to the design and manufacture of the grating, and when the material gain peak wavelength position is close to the wavelength channel position, the obtained differential gain is larger, for example, the long wavelength channel in fig. 13 is very close to the material gain peak wavelength position, the corresponding differential gain dg1 is larger, and the short wavelength channel position is far from the material gain peak wavelength position, the corresponding differential gain dg2 is smaller, so the bandwidth of the long wavelength channel is larger than that of the short wavelength channel; in a communication system, if the distance between two channels is too large, the bandwidth of one channel is inevitably degraded and cannot reach the standard, so that in the MWDM technology with large distance between adjacent channels, one epitaxial structure is required to correspond to one wavelength channel, which impacts on production efficiency and cost.

In the design of the refrigeration type wavelength division multiplexing 25Gbps laser chip, the design of a single wafer corresponding to a single wavelength channel is very mature abroad. However, when laser chips with different wavelength channels are further manufactured by using the same wafer structure, the problem that the bandwidth of the laser chip is reduced and communication error codes are formed due to the fact that the differential gain is deteriorated caused by a large wavelength difference needs to be overcome. This application mainly when designing through epitaxial structure, optimizes the quantum well structure in active area to this single epitaxial structure satisfies the bandwidth demand in long wavelength passageway (LWDM passageway 4) to short wavelength passageway (LWDM passageway 1) scope simultaneously. Generally speaking, the laser products of the MWDM and LWDM schemes can ensure the bandwidth to be above 19GHz at 50 ℃, and can obtain good communication quality.

In order to achieve the above object, the present application provides a laser chip 100. Referring to fig. 15 and 16, the laser chip 100 includes a second substrate 210, a third confinement layer 220, a second active layer 230, and a fourth confinement layer 240. The third confinement layer 220 and the fourth confinement layer 240 are respectively located at two opposite sides of the second active layer 230 and are stacked with the second active layer 230. The second active layer 230 includes a third quantum well layer 231 and a fourth quantum well layer 233 disposed in the stacking direction, wherein a wavelength difference between the third quantum well layer 231 and the fourth quantum well layer 233 is 10nm to 20 nm.

A third confinement layer 220, a second active layer 230, and a fourth confinement layer 240 are sequentially deposited on the second substrate 210. The third confinement layer 220, the second active layer 230 and the fourth confinement layer 240 may be made of aluminum indium gallium arsenide (AlInGaAs) materials. Compared to the second active layer 230, the fourth confinement layer 240 and the third confinement layer 220 may serve as graded layers of the energy level of the second active layer 230, such that under the condition of an applied current, the particles of the second active layer 230 realize population inversion, electrons of a low energy level are excited to transit to the high energy level, and then spontaneously transit from the high energy level to the low energy level to recombine with holes, and simultaneously emit photons, thereby generating light output power.

Wherein the second active layer 230 includes two types of multiple quantum wells. One type of multiple quantum well is the third quantum well layer 231 and the other type of multiple quantum well is the fourth quantum well layer 233. The wavelength difference between the third quantum well layer 231 and the fourth quantum well layer 233 is 10nm to 20 nm. In one embodiment, the wavelength difference between the third quantum well layer 231 and the fourth quantum well layer 233 is 15 nm. By setting the wavelength difference between the third quantum well layer 231 and the fourth quantum well layer 233, the second active layer 230 has two types of quantum wells at the same time, and the material gains of the formed whole are overlapped by two groups of material gains with different wavelength positions, so that when a laser is manufactured on the laser chip 100, all wavelength channels within the range conforming to the two wavelength channels have excellent performance. The single laser chip 100 can be used for simultaneously manufacturing 2 channel laser chips with MWDM specification or 4 channel laser chips with LWDM specification, the technology that one laser chip 100 is only used as one channel laser chip is different from the technology that one laser chip 100 is used, the production efficiency and the yield are favorably improved, and meanwhile, the product performance is prevented from being influenced by errors in process manufacturing due to the advantage of ensuring the design of an epitaxial structure.

Specifically, for the MWDM technique, the distance between the two nearest wavelength channels is 7nm, the distance between the two groups of wavelength channels and the next two groups of wavelength channels is 13nm, and the distance between the two groups of wavelength channels and the next two groups of wavelength channels is too far beyond the limit of active region design, so the design invention of this patent mainly uses a single epitaxial structure to manufacture 2 wavelength channel lasers with a wavelength distance of 7nm in the MWDM technique.

For the LWDM technique, besides the channel with the longest wavelength of 1332.9nm, the distance between two adjacent wavelength channels is about 4.5nm, for example, 4 wavelength channels are included at a time, and the distance between the 1 st and the 4 th wavelength channels is 13.5nm, which can be realized in the design of the active area, so the invention of this patent also uses a single epitaxial structure to manufacture 4 wavelength channel lasers with the total wavelength distance of 13.5nm under the LWDM technique.

Combining the two technical requirements, as shown in fig. 14, in the 4-wavelength channel of the LWDM technical scheme, the distance from the channel 1 to the channel 4 is the farthest, which also represents that the distance from the channel 1 to the channel 4 of the LWDM technical scheme can be satisfied in design, and the specifications of the channel 1 and the channel 2 of the MWDM technical scheme can also be satisfied, so in the active region, the design of the third quantum well layer 231 is optimized for the LWDM channel 4, and the design of the fourth quantum well layer 233 is optimized for the LWDM channel 1, and by adjusting the number, thickness, stress and wavelength difference of the two types of quantum wells, the characteristic requirements of the MWDM two-channel and the LWDM 4-channel are satisfied. From the perspective of mass production, the scheme provided by the application emphasizes on the design of the epitaxial structure of the active region, and the designed epitaxial structure does not add other complex processes in the production process and has mass production advantages.

In one embodiment, the number of the third quantum well layers 231 is 5 to 7, and the number of the fourth quantum well layers 233 is 4 to 5. The number of the third quantum well layers 231 is 5 to 7, and the number of the fourth quantum well layers 233 is 4 to 5, so that the bandwidth of the LWDM channel 4 at 50 ℃ is more than 19 GHz. When the number of the third quantum well layers 231 is 7 and the number of the fourth quantum well layers 233 is 4, the laser chip 100 has a bandwidth value of 19.7 GHz. Meanwhile, when the number of the third quantum well layers 231 is 6 and the number of the fourth quantum well layers 233 is 5, the laser chip 100 has a bandwidth value of 19.6 GHz.

In one of the embodiments, the thickness of the third quantum well layer 231 is 50 a to 70 a and the thickness of the fourth quantum well layer 233 is 50 a to 70 a. With such a design thickness, when the number of the third quantum well layer 231 is 5 to 7 and the number of the fourth quantum well layer 233 is 4 to 5, the bandwidth at 50 ℃ can be more than 19GHz, and such a thickness is not difficult to adapt to parameters of MOCVD equipment in an epitaxial production process, and is suitable for mass production.

In one embodiment, the second active layer 230 further includes a second barrier layer 232, the third quantum well layer 231 and the fourth quantum well layer 233 are alternately stacked in sequence along the stacking direction, the stress of the third quantum well layer 231 is +0.8% to +1.3%, the stress of the fourth quantum well layer 233 is +0.8% to +1.3%, and the stress of the second barrier layer 232 is-0.6% to-0.2%.

It is understood that the deposition sequence of the third quantum well layer 231 and the fourth quantum well layer 233 is not limited in particular, and all of the third quantum well layer 231 and the second barrier layer 232 may be deposited alternately on the third confinement layer 220, and then the fourth quantum well layer 233 and the second barrier layer 232 may be deposited alternately on the uppermost second barrier layer 232 (see fig. 16 for details). Of course, the fourth quantum well layer 233 and the second barrier layer 232 may be deposited alternately on the third confinement layer 220, and then the third quantum well layer 231 and the second barrier layer 232 may be deposited alternately on the uppermost second barrier layer 232.

On one hand, the larger the stress of the quantum well or the potential barrier is, the more easily the lattice mismatch is generated in the epitaxial process, so that the quality of the wafer is degraded, and the yield and the characteristics are greatly reduced; on the other hand, the addition of quantum well stress is beneficial to improving the differential quantum efficiency of a semiconductor device (such as a laser) and improving the bandwidth. In order to balance the contradiction between the addition of quantum well stress and lattice mismatch, reverse stress is added to a potential barrier adjacent to a stressed quantum well to be used as stress compensation, so that lattice mismatch is avoided; in the embodiment, under the condition that the compressive stress is added to the quantum well, the tensile stress of the adjacent barrier is simultaneously given to serve as stress compensation, so that the problem of lattice mismatch is avoided under the condition of a multi-layer quantum well and barrier stacking epitaxial process.

In one embodiment, the laser chip 100 further includes a second buffer layer 211, a third cladding layer 250, a plurality of second grating strips 260, and a fourth cladding layer 270.

The second buffer layer 211 is disposed on a surface of the third confinement layer 220 away from the second active layer 230. The third cladding layer 250 is disposed on a surface of the fourth confinement layer 240 away from the second active layer 230. The plurality of second grating strips 260 are disposed at intervals on the surface of the third cladding layer 250 away from the fourth confinement layer 240. The fourth cladding layer 270 is disposed between the surfaces of the plurality of second grating bars 260 and the plurality of second grating bars 260, and the fourth cladding layer 270 is provided with a ridge waveguide structure.

In this embodiment, the second buffer layer 211, the third cladding layer 250 and the fourth cladding layer 270 may be indium phosphide (InP) materials. The third cladding layer 250 and the fourth cladding layer 270 are both P-InP material, and the second buffer layer 211 is N-InP material. The second buffer layer 211 is disposed on the surface of the second substrate 210, and covers the second substrate 210, thereby playing a role of buffering. The plurality of second grating strips 260 form a diffraction grating layer. Under the diffraction of the diffraction grating layer, the light with the wavelength of the single longitudinal mode is output, and single-wave light emission is formed. In one embodiment, the plurality of second grating bars 260 include In_1-xGa_xAs_yP_1-yAnd (3) a layer. Said In_1-xGa_xAs_yP_1-yThe value of x in the layer ranges from 0.05 to 0.32, and the value of y ranges from 0.05 to 0.69. In one possible embodiment, x =0.23 and y = 0.50. The fourth cladding layer 270 is disposed between the surfaces of the second grating bars 260 and the second grating bars 260, and covers the second grating bars 260 and fills gaps between the second grating bars 260. At this time, a large difference in refractive index is formed between the fourth clad layer 270 and the plurality of second grating bars 260. The fourth cladding layer 270 is provided with a ridge waveguide structure, and has advantages of high power, long-distance transmission and the like.

Referring to fig. 17 to fig. 21, in an embodiment, the laser chip 100 further includes a second ohmic contact layer 280, a third metal electrode layer 201, and a fourth metal electrode layer 202. The second ohmic contact layer 280 is disposed on a surface of the ridge waveguide structure away from the plurality of second grating strips 260. The third metal electrode layer 201 is disposed on the surface of the second ohmic contact layer 280 away from the fourth cladding layer 270. The fourth metal electrode layer 202 is disposed on a surface of the second substrate 210 away from the second buffer layer 211. The third metal electrode layer 201 is a P-metal electrode layer. The fourth metal electrode layer 202 is an N-metal electrode layer. The material of the second ohmic contact layer 280 may be InGaAs material.

In one embodiment, the fourth metal electrode layer 202, the second substrate 210, the second buffer layer 211, the third confinement layer 220, the second active layer 230, the fourth confinement layer 240, the third cladding layer 250, the plurality of second grating strips 260, the fourth cladding layer 270, the second ohmic contact layer 280 and the third metal electrode layer 201 form a matrix structure (not labeled). The laser chip 100 further includes a second highly reflective coating 203 and a second anti-reflective coating 204. The second high-reflection coating layer 203 is arranged on the first end face of the substrate structure parallel to the long axis of the second grating strip. The second antireflection coating layer 204 is disposed on a second end surface of the base structure parallel to the long axis of the second grating bar. The first end face is arranged opposite to the second end face.

In this embodiment, a matrix structure formed by the fourth metal electrode layer 202, the second substrate 210, the second buffer layer 211, the third confinement layer 220, the second active layer 230, the fourth confinement layer 240, the third cladding layer 250, the plurality of second grating strips 260, the fourth cladding layer 270, the second ohmic contact layer 280 and the third metal electrode layer 201 may be regarded as an integral structure. As shown in fig. 21, the second high reflection coating layer 203 is provided on a first end surface of the base structure parallel to the long axis of the second grating bar, that is, a right end surface in fig. 21. The second end face is disposed opposite to the first end face, i.e., the left end face in fig. 21. The long axis direction of the second grating bars is an axis parallel to the length direction of the second grating bars, i.e., the direction shown in fig. 20. At this time, the fourth metal electrode layer 202, the second substrate 210, the second buffer layer 211, the third confinement layer 220, the second active layer 230, the fourth confinement layer 240, the third cladding layer 250, the plurality of second grating strips 260, the fourth cladding layer 270, the second ohmic contact layer 280, and the third metal electrode layer 201 are disposed between the second highly reflective coating layer 203 and the second anti-reflective coating layer 204. One end plated with the second antireflection film coating layer 204 is a light emitting end, that is, one side of the second antireflection film coating layer 204 is the light emitting end of the laser chip 100.

s10, providing a second substrate 210, and growing a second buffer layer 211 and a third confinement layer 220 on the surface of the second substrate 210;

s20, sequentially growing the first quantum well layer 131 and the first barrier layer 132 and the second quantum well layer 133 and the first barrier layer 132 alternately stacked on the surface of the third confinement layer 220 away from the second substrate 210 to generate a second active layer 230;

s30, growing a fourth confinement layer 240 on the surface of the second active layer 230 away from the third confinement layer 220;

wherein the wavelength difference between the third quantum well layer 231 and the fourth quantum well layer 233 is 10nm to 20 nm.

In this embodiment, the method for preparing the semiconductor epitaxial structure adopts an MOCVD growth technique to sequentially grow the second buffer layer 211, the third confinement layer 220, the second active layer 230, and the fourth confinement layer 240 on the surface of the second substrate 210 from bottom to top. The third confinement layer 220, the second active layer 230 and the fourth confinement layer 240 may be made of aluminum indium gallium arsenide (AlInGaAs) materials. Compared to the second active layer 230, the fourth confinement layer 240 and the third confinement layer 220 may serve as graded layers of the energy level of the second active layer 230, such that under the condition of an applied current, the particles of the second active layer 230 realize population inversion, electrons of a low energy level are excited to transit to the high energy level, and then spontaneously transit from the high energy level to the low energy level to recombine with holes, and simultaneously emit photons, thereby generating light output power.

In the above embodiment, the second active layer 230 includes two types of multiple quantum wells. One type of multiple quantum well is the third quantum well layer 231 and the other type of multiple quantum well is the fourth quantum well layer 233. The wavelength difference between the third quantum well layer 231 and the fourth quantum well layer 233 is 10nm to 20 nm. In one embodiment, the wavelength difference between the third quantum well layer 231 and the fourth quantum well layer 233 is 15 nm. By setting the wavelength difference between the third quantum well layer 231 and the fourth quantum well layer 233, the second active layer 230 has two types of quantum wells at the same time, and the material gains of the formed whole are overlapped by two groups of material gains with different wavelength positions, so that when a laser is manufactured on the laser chip 100, all wavelength channels within the range conforming to the two wavelength channels have excellent performance. The single laser chip 100 can be used for simultaneously manufacturing 2 channel laser chips with MWDM specification or 4 channel laser chips with LWDM specification, the technology that one laser chip 100 is only used as one channel laser chip is different from the technology that one laser chip 100 is used, the production efficiency and the yield are favorably improved, and meanwhile, the product performance is prevented from being influenced by errors in process manufacturing due to the advantage of ensuring the design of an epitaxial structure.

In one embodiment, the laser chip 100 is grown as follows: an InP layer (second buffer layer 211), a third confinement layer 220, an aluminum indium gallium arsenide layer (second active layer 230), a fourth confinement layer 240, an indium phosphide (InP) third cladding layer 250, an indium gallium arsenide phosphide (InGaAsP) diffraction grating layer, and an indium phosphide (InP) fourth cladding layer 270 are sequentially grown on the surface of an InP second substrate 210 (also referred to as a wafer) from bottom to top by using an MOCVD method, so that the structure shown in fig. 15 is obtained. The process is the design center of gravity of the embodiment, two types of quantum wells are placed in the active area, the advantages of the partition optimization characteristics of the LWDM wavelength channel 4 and the LWDM wavelength channel 1 are achieved, the production complexity is not increased, and the mass production is facilitated.

Through photoetching and dry etching technologies, the etching area is exposed, namely the top surface of the end face etching area, rie (reactive Ion etching) technology is adopted for dry etching, the fourth cladding layer 270 and the plurality of second grating strips 260 are etched from top to bottom, the etching stops at the third cladding layer 250, so that the plurality of diffractive second grating strips are etched on the material of the diffractive grating layer, and the structure shown in fig. 17 is obtained, and the diffractive grating layer is obtained.

Referring to fig. 18, the fourth cladding layer 270 is grown as follows: a fourth cladding layer 270 and a second ohmic contact layer 280 are sequentially grown on the plurality of second grating bars 260 by using the MOCVD growth technique. The fourth cladding layer 270 is InP material, and the etched diffraction grating layer is completely clad by the fourth cladding layer 270. The second ohmic contact layer 280 is InGaAs material to obtain a semi-finished wafer.

Referring to fig. 19, in order to effectively inject current into the active region for electro-optic conversion, a ridge waveguide structure may be defined to confine current carriers and photons after obtaining the semi-finished wafer. And defining the ridge waveguide with the width of about 2 microns by utilizing a photoetching technology and a photomask, and then carrying out dry etching on the ridge waveguide to a plurality of first grating strips by utilizing an RIE (reactive ion etching) technology to obtain the ridge waveguide structure.

Referring to fig. 19 to 21, in one embodiment, after a layer of insulating second passivation film 290 of silicon dioxide or silicon nitride is formed on the structure surface by using a PECVD technique, the second passivation film 290 on the surface of the second ohmic contact layer 280 is etched and removed. At this time, the second passivation film 290 covers only the surface of the region other than the ridge waveguide. Then plating a p-metal electrode layer (a third metal electrode layer 201) on the second ohmic contact layer 280, then thinning and polishing the back surface of the second substrate 210 of indium phosphide to 100 μm, and plating an n-metal electrode layer (a fourth metal electrode layer 202); and cutting the semi-finished wafer to obtain a chip semi-finished product, plating a second anti-reflection coating layer 204 on one end (the left side in the figure 21) of the chip semi-finished product, and plating a second high-reflection coating layer 203 on the opposite end (the right side in the figure 21). The process is now complete and a non-cryogenic industrial grade 25Gbps semiconductor laser chip 100 is obtained.

In one embodiment, the present application provides the following specific 5 embodiments optimized for three types of structures in the active region. These three types of structures are, in epitaxial order, a third quantum well layer 231, a second barrier layer 232, and a fourth quantum well layer 233. Due to the fact thatThe most serious part affecting the characteristics under the high-temperature and low-temperature operation is that the high-temperature bandwidth is easy to be degraded to less than 18GHz, so that the relation between the structural parameters of the active region and the high-temperature bandwidth is mainly optimized in the embodiments 2-1, 2-3, 2-4 and 2-5, and the embodiment 2-2 is optimized for the low-temperature bandwidth; wherein, the Coupling Coefficient (Coupling Coefficient) of the laser commonly used in the five embodiments is 100 cm^-1The length of the resonant cavity is 150 μm, the width of the ridge waveguide is 2 μm, and the parameter setting is also within the commercial specification range of the common 25Gbps laser, wherein if the values of the coupling coefficient, the length of the resonant cavity and the width of the ridge waveguide are changed, the trend of influencing the bandwidth is consistent, and the result of optimizing the five lasers in the embodiment is not influenced.

Example 2-1

In this embodiment, the purpose of increasing the 50 ℃ bandwidth of the LWDM channel 4 is achieved by optimizing the number of the third quantum well layer 231 in the active region, wherein four parameters need to be optimized, which are the number of the fourth quantum well layers 233, the quantum well thickness, the stress of the quantum well and the barrier, and the wavelength difference between the third quantum well layer 231 and the fourth quantum well layer 233, and the four parameters are respectively optimized and designed in embodiments 2-2 to 2-5 one by one. In example 2-1, the thickness of the quantum well will be taken near the middle of the value range (i.e., thickness 60 a), the stress of the quantum well and the barrier will be taken near the middle of the value range (i.e., compressive stress +1.0% and tensile stress-0.4% of the barrier), and the wavelength difference between the two types of quantum wells will be taken near the middle of the value range (i.e., 15 nm). The main consideration of the value setting of the preliminary parameters is that the preliminary parameters are easily adjusted setting of epitaxial equipment in the production of general commercial products. And the parameters are finely adjusted front and back on the premise of easy production, so that the production difficulty is reduced. According to the optimization result shown in fig. 22, when the number of the third quantum well layer 231 is in the range of 5 layers to 7 layers, and the number of the fourth quantum well layer 233 is in the range of 4 layers to 5 layers, the laser chip 100 can satisfy that the bandwidth of the LWDM channel 4 is greater than 19GHz at 50 ℃. When the number of the third quantum well layers 231 is 7 and the number of the fourth quantum well layers 233 is 4, the laser chip 100 has a bandwidth value of 19.7 GHz. Meanwhile, when the number of the third quantum well layers 231 is 6 and the number of the fourth quantum well layers 233 is 5, the laser chip 100 has a bandwidth value of 19.6 GHz. Since the 50 ℃ bandwidth of the LWDM channel 1 in example 2-2 needs to be considered in design, it is found that the bandwidth value of the two channels has a smaller variation when the number of the third quantum well layers 231 is 6. Therefore, the number of the third quantum well layers 231 is 6, which is the best value in this embodiment.

Examples 2 to 2

In this embodiment, the number of the fourth quantum well layers 233 in the active region is optimized to ensure that the bandwidth of the LWDM channel 1 at 50 ℃ is greater than 19GHz, and as shown in fig. 23, the number of the third quantum well layers 231 in embodiment 2-1 is 5 to 7. When the number of the fourth quantum well layers 233 ranges from 4 to 5, the laser chip 100 can meet the requirement of the LWDM channel 1 for a bandwidth of 19GHz at 50 ℃. Wherein, when the number of the third quantum well layers 231 is 6 and the number of the fourth quantum well layers 233 is 5, the laser chip 100 has a bandwidth value of 19.7 GHz. Therefore, the number of the fourth quantum well layers 233 is preferably 5 in the present embodiment.

Examples 2 to 3

This example optimizes the individual thickness of all quantum wells in the active region to ensure that the bandwidths of LWDM channel 1 and LWDM channel 4 are greater than 19GHz at 50 ℃, as shown in fig. 24, taking the best results of example 2-2: on the premise of the design that the number of the third quantum well layers 231 is 6 and the number of the fourth quantum well layers 233 is 5, when the value range of the thickness of the quantum wells is from 50 a to 70 a, the bandwidth of the laser chip 100 at 50 ℃ is greater than 19 GHz. Where the LWDM channel 4 has a bandwidth behavior of 19.6GHz at a quantum well thickness of 60 a, and the LWDM channel 1 also has a bandwidth behavior of 19.7 GHz. The quantum well thickness has no difficulty in adjusting parameters of MOCVD equipment in the epitaxial production process, and is suitable for mass production.

Examples 2 to 4

The present embodiment optimizes the stress of all quantum wells and barriers in the active region to ensure that the bandwidth at 50 ℃ is greater than 19 GHz. Since the bandwidth performance of the LWDM channel 4 is poor compared to the bandwidth performance of the LWDM channel 1, the present embodiment is relatively strict and objective to optimize the bandwidth of the LWDM channel 4. Generally speaking, the larger the stress of the quantum well or the potential barrier is, the more easily the lattice mismatch is generated in the epitaxial process, which leads to the quality degradation of the wafer and causes the great reduction of the yield and the characteristics, and the addition of the quantum well stress is helpful for improving the differential quantum efficiency of the laser, improving the bandwidth and balancing the contradiction between the addition of the quantum well stress and the lattice mismatch. Typically, an inverse stress is added to the barrier adjacent to the stressed quantum well for stress compensation to avoid lattice mismatch. In the embodiment, under the condition that the compressive stress is added to the quantum well, the tensile stress of the adjacent barrier is simultaneously given to serve as stress compensation, so that the problem of lattice mismatch is avoided under the condition of a multi-layer quantum well and barrier stacking epitaxial process. As shown in fig. 25, the best value results of examples 2 to 3 are taken: on the premise of the design that the number of the third quantum well layers 231 is 6, the number of the fourth quantum well layers 233 is 5 and the thickness of the quantum well is 60 a, when the value range of the quantum well stress is from +0.8% to +1.3%, the value range of the barrier stress is from-0.6% to-0.2%, and the laser chip 100 can meet the requirement that the bandwidth is greater than 19GHz at 50 ℃. Wherein, when the quantum well stress is +1.3% and the barrier stress is-0.4%, the laser chip 100 has a bandwidth performance of 20 GHz.

Examples 2 to 5

In the embodiment, the bandwidth of the LWDM channel 1 and the bandwidth of the LWDM channel 4 at 50 ℃ are ensured to be greater than 19GHz by optimizing the material energy system wavelength difference value of the two types of quantum wells in the active region. The best value results of examples 2-4 were taken as follows: the design that the number of the third quantum well layers 231 is 6, the number of the fourth quantum well layers 233 is 5, the thickness of the quantum well is 60 a, the stress of the quantum well is +1.3%, and the barrier stress is-0.4% is assumed. As shown in fig. 26, the quantum well wavelength difference defined by the horizontal axis represents the difference of the wavelength of the third quantum well layer 231 minus the wavelength of the fourth quantum well layer 233. The laser chip 100 can obtain a bandwidth of more than 19GHz at 50 c when the wavelength difference is 10nm to 20 nm. When the optimal quantum well wavelength difference value is 15nm, the bandwidth of the LWDM channel 4 is 20GHz, the bandwidth of the LWDM channel 1 is 20.2GHz, and both channels have the optimal bandwidth performance.

The five embodiments described above are embodied in the cost limit of commercial mass production, and start with the epitaxial design of the chip, so as to ensure that the cooling type wavelength division multiplexing 25Gbps semiconductor laser product can realize the flexible application of sharing a wafer multi-wavelength channel. The consideration of each process and the optimization design of the embodiment both have the key commercialization requirements of the 5G forward system: the basic principle of localization, low cost, high speed, easy mass production and no sacrifice of product quality is favorable for promoting the process of commercial popularization of the 5G system.

Referring to fig. 27 and 28, an embodiment of the present application provides a laser chip 100. The laser chip 100 includes a substrate 310, an insulating grating layer 360, and a third active layer 352. The insulating grating layer 360 is disposed on the substrate 310. In the extending direction along the substrate 310, the insulating grating layer 360 includes a plurality of high-resistance state grating regions 314 and low-resistance state grating regions 316 arranged at intervals. The third active layer 352 is disposed on a side of the insulated grating layer 360 away from the insulated grating layer 360. The third active layer 352 includes a plurality of gain-free regions 319 and gain-active regions 318 disposed at intervals in a direction extending along the substrate 310. The high resistance state grating regions 314 correspond to the non-gain regions 319 one to one, and the low resistance state grating regions 316 correspond to the gain regions 318 one to one.

The substrate 310 may serve as support and protection. The substrate 310 may be silicon carbide, silicon oxide, or the like. The third active layer 352 and the insulated grating layer 360 are stacked on the surface of the substrate 310. The non-gain region 319 is located above the high-impedance grating region 314. The gain region 318 is located above the low resistance state grating region 316.

It can be appreciated that the third active layer 352 is in a non-gain state without current injection, i.e., constitutes the non-gain region 319. And the third active layer 352 forms a gain in the presence of current injection, i.e., constitutes the active gain region 318. The high-resistance state grating region 314 has a strong high-resistance state effect, and carriers are difficult to pass through. And carriers easily pass through the low resistance state grating region 316. I.e., carriers are not easily passed from the high resistance state grating region 314 to the corresponding non-gain region 319, while carriers are easily passed from the low resistance state grating region 316 to the gain region 318. And the direction of the waveguide may be an extension direction of a plane in which the substrate 310 is located. Therefore, the carriers are periodically distributed along the waveguide direction, so that the periodic gain distribution of the third active layer 352 along the waveguide direction is enhanced, the Side Mode Suppression Ratio (SMSR) and the anti-reflection characteristic of the longitudinal mode are improved, and the transmission error of the laser chip 100 caused by reflection is reduced. The laser chip 100 can save a space for disposing an isolator, so that the volume of the laser chip 100 can be reduced. Further, the laser chip 100 can also effectively reduce the sensitivity of the laser chip 100 to end reflection.

In one embodiment, the sum of the width of one of the no-gain regions 319 and the width of one of the gain regions 318 is equal to the grating period Λ of one of the insulating grating layers 360, and the width of the gain region 318 = (0.4 to 0.6) Λ. In one embodiment, the grating period Λ ranges from 190nm to 300 nm.

In one embodiment, the dielectric grating layer 360 includes a diffraction grating layer 370 and a first cladding layer 320. The diffraction grating layer 370 is disposed on the surface of the substrate 310. The diffraction grating layer 370 includes a plurality of raised structures 312 disposed at intervals. The high-resistance state grating region 314 is formed in the region where the raised structure 312 is located. The low resistance state grating region 316 is formed between the raised structure 312 and the raised structure 312. The first cladding layer 320 is disposed on a side of the diffraction grating layer 370 away from the substrate 310. After the diffraction grating layer 370 is deposited on the substrate 310, a first cladding layer 320 may be grown on the surface of the diffraction grating layer 370. The raised structures 312 may be formed by patterning the diffraction grating layer 370 and the first cladding layer 320 simultaneously.

The raised structures 312 may be stripe structures formed on the diffraction grating layer 370. The plurality of protruding structures 312 are spaced apart to form a grating structure. The raised structure 312 has a strong high resistance effect, so that current is not easy to pass through. A material in a low resistance state may be filled between two adjacent raised structures 312 to form the low resistance state grating region 316.

In one embodiment, the laser chip 100 further includes a second cladding layer 321. The second cladding layer 321 is disposed between the first cladding layer 320 and the third active layer 352. That is, the second cladding layer 321 is stacked on the first cladding layer 320 and the third active layer 352. The second cladding layer 321 and the third active layer 352 are disposed on a side of the first cladding layer 320 away from the substrate 310. After the raised structures 312 are formed by patterning the diffraction grating layer 370 and the first cladding layer 320, the material of the second cladding layer 321 may be filled between the adjacent raised structures 312 while covering the second cladding layer 321 on the surface of the first cladding layer 320.

In one embodiment, the laser chip 100 further includes a third cladding layer 322 and a contact layer 330. The third cladding layer 322 and the contact layer 330 are sequentially disposed on a side of the third active layer 352 away from the substrate 310. That is, the third cladding layer 322 and the contact layer 330 are sequentially disposed on the side of the third active layer 352 away from the substrate 310.

Referring to fig. 29, in one embodiment, a third anti-reflective coating 340 and a third highly reflective coating 350 are disposed on two sides of the laser chip 100. The third anti-reflective coating 340 may be used to emit a beam of light. The third highly reflective coating 350 may be used to reflect light. The side of the contact layer 330 remote from the substrate 310 may form a layer of p-metal electrode 354. The side of the substrate 310 away from the layer of p-metal electrodes 354 may be plated with a layer of n-metal electrodes 356.

In one embodiment, the raised structures 312 comprise Fe doped In_1-xGa_xAs_yP_1-yA material. Wherein, the value range of x is 0.00 to 0.6, and the value range of y is 0.00 to 0.95.

It can be understood that In_1-xGa_xAs_yP_1-yAfter doping Fe element In, In_1-xGa_xAs_yP_1-yDeep level carrier trapping centers are formed in the material. These carrier capture centers will capture carriers entering the material and block the carrier transmission path. Thus can have the advantages ofThe effect of the rim. By adjusting In_1-xGa_xAs_yP_1-yThe material composition can change In_1-xGa_xAs_yP_1-yStrength of the barrier to InP heterojunction. Suitable heterojunction barriers may also serve to hinder the efficiency of carrier transport at this interface. Therefore, by adjusting the concentration of Fe doping and In_1-xGa_xAs_yP_1-yThe high impedance characteristic of the high impedance state grating region 314 can be realized. Fe doped In_1-xGa_xAs_yP_1-yA region of material constitutes the high resistivity grating region 314. The resistance current cannot be injected into the third active layer 352 in the high resistance state grating region 314, and the third active layer 352 is in a non-gain state without current injection. Since the non-Fe doped region between the two protruding structures 312 is in a low resistance state to form the low resistance state grating region 316, current can be easily injected into the third active layer 352 through the low resistance state grating region 316 to form a gain. Therefore, the high-resistance state grating region 314 and the low-resistance state grating region 316 are arranged in the parallel waveguide direction to realize the gain period variation of the third active layer 352 in the direction, so as to form the laser chip 100 with the gain coupling type distribution function.

In one embodiment, the Fe is doped with In_1-xGa_xAs_yP_1-yIn the material, x is 0.258 and y is 0.468.

In one embodiment, the Fe is doped with In_1-xGa_xAs_yP_1-yIn the material, the doping concentration D of Fe_FeIs 5e16 cm^-3To 2e18 cm^-3。

In one embodiment, the Fe is doped with In_1-xGa_xAs_yP_1-yThe Fe doping concentration in the material is 1.5e18cm^-3。

In one embodiment, the thickness T of the diffraction grating layer 370_gIs 10nm to 500nm, and the thickness T of the first cladding layer 320_c5nm to 200nm, and the second cladding layer 321 has a thickness T_bIs 0nm to 500 nm.

In one embodiment, the thickness T of the diffraction grating layer 370_gIs 200 nm; first cladding 320 thickness T_cIs 50 nm; thickness T of second cladding 321_bIs 10 nm.

In one embodiment, the material of the first cladding layer 320 may be N-type InP. N type doping concentration D_cIs in the range of 1e17cm^-3To 2e18 cm^-3In one embodiment, the N-type doping concentration D_cIs 1e18cm^-3. In one embodiment, the material of the second cladding 321 is N-type InP.

In one embodiment, at least one of the first cladding 320 and the second cladding 321 has a doping concentration of 1e18cm^-3. In one embodiment, the doping concentrations of the first cladding 320 and the second cladding 321 are both 1e18cm^-3。

The embodiment of the present application further provides a manufacturing method of the laser chip 100. The method comprises the following steps:

s10, providing a substrate 310;

s20, forming an insulating grating layer 360 on the surface of the substrate 310; along the extending direction of the substrate 310, the insulating grating layer 360 includes a plurality of high-resistance state grating regions 314 and low-resistance state grating regions 316 arranged at intervals;

s30, forming a third active layer 352 on a side of the insulating grating layer 360 away from the substrate 310, wherein along an extending direction of the substrate 310, the third active layer 352 includes a plurality of non-gain regions 319 and gain regions 318 that are disposed at intervals, the high resistance state grating regions 314 correspond to the non-gain regions 319 one to one, and the low resistance state grating regions 316 correspond to the gain regions 318 one to one.

In S20, the diffraction grating layer 370 and the first cladding layer 320 may be sequentially deposited on the substrate 310 by using a Metal Organic Chemical Vapor Deposition (MOCVD) method; wherein the material of the diffraction grating layer 370 is Fe-doped semi-insulating In_1- _xGa_xAs_yP_1-yIn is induced by the addition of Fe_1-xGa_xAs_yP_1-yRefractive index and stress generation of materialsChanges and thus the elemental composition of the material can be re-optimized. In therein_1-xGa_xAs_yP_1-yThe value of the component x ranges from 0.00 to 0.60; y ranges from 0.00 to 0.95; fe doped semi-insulating In_1-xGa_xAs_yP_1-yHas a doping concentration range of 5e16 cm^-3To 2e18 cm^-3(ii) a Thickness T of diffraction grating layer 370_gThe value range of (a) is 10nm to 500 nm; the material of the first cladding 320 is N-type InP with a thickness T_cHas a value range of 5nm to 200nm and a doping concentration D_cIs in the range of 1e17cm^-3To 2e18 cm^-3。

Referring to fig. 30, the first cladding layer 320 and the diffraction grating layer 370 may then be etched by a general grating lithography process to form the insulated grating layer 360. Wherein the period Λ of the insulating grating layer 360 ranges from 190nm to 300 nm.

In S30, the second cladding layer 321, the third active layer 352, the third cladding layer 322, and the contact layer 330 may be sequentially deposited on the first cladding layer 320 using an MOCVD method. Wherein the material of the second cladding 321 may be InP. Its thickness T_bHas a value range of 0nm to 500nm and a doping concentration D_bIs in the range of 1e17cm^-3To 2e18 cm^-3. And obtaining the wafer after the working procedure is finished.

In one embodiment, after the S30, the method further includes:

s40: a waveguide structure may be formed on the wafer in S30 using photolithography techniques, and then an insulating layer may be formed on the waveguide surface using plasma chemical vapor deposition. The insulating layer on the upper surface of the waveguide is then removed by a general etching process to expose the contact layer 330. A layer of p-metal electrode 354 is then formed over the contact layer 330 and insulating layer. The back side of the substrate 310 is then polished back to 100 μm and plated with a layer of n-metal electrode 356. After the wafer is cut, one end of the wafer is plated with a third anti-reflection coating 340, and the other end of the wafer is plated with a third high-reflection coating 350, so that the laser chip 100 can be obtained.

In one embodiment, the laser chip 100 may constitute a 50Gb/s gain-coupled DFB laser chip for communication. In the waveguide direction parallel to the laser chip, the periodic distribution of carriers in the waveguide extending direction is realized by adjusting the material composition and doping of the insulating grating layer 360, so that the periodic gain component of the third active layer 352 in the waveguide extending direction is realized, and the output light of a single longitudinal mode can be realized. And in the direction perpendicular to the waveguide direction of the laser chip, the thickness of the insulated grating layer 360 is adjusted to change the distribution of carriers in the third active layer 352 relative to the placement position of the third active layer 352, the material composition and the thickness of the second cladding layer 321, so as to realize the gain period distribution of the third active layer 352.

In one embodiment, the laser chip 100 can be directly applied to 10G, 25G, and more than 50G direct modulated laser chips, electro-absorption modulated laser chips. The laser chip has the advantages of high cost performance, high reliability and high intelligence.

The following illustrates the advantageous effects of the above embodiments:

example 3-1

Referring to fig. 27, the laser chip 100 includes a substrate 310 and an insulating grating layer 360 disposed on the substrate 310. The insulating grating layer 360 is formed of a diffraction grating layer 370 disposed on a substrate 310 and the first cladding layer 320. The diffraction grating layer 370 may be formed of a grating structure formed of the raised structures 312. The surface of the insulated grating layer 360 away from the substrate 310 sequentially covers the second cladding layer 321, the third active layer 352, the third cladding layer 322 and the contact layer 330. The contact layer 330 covers the p-metal electrode 354 layer, and the lower surface of the substrate 310 is plated with the n-metal electrode 356 layer. One end of the laser chip 100 is plated with a third anti-reflection coating 340, and the other end is plated with a third highly-reflective coating 350.

Wherein the material of the diffraction grating layer 370 is Fe-doped semi-insulating In_1-xGa_xAs_yP_1-yX =0.00, y =0.00, Fe doping concentration D_Fe=1.5e18 cm^-3. Thickness T of the diffraction grating layer 370_g=200nm，Grating period Λ =204 nm. The first cladding 320 thickness T_c=50nm, doping concentration D_c=1e18 cm^-3. The second cladding 321 thickness T_b=10nm, doping concentration D_b=1e18 cm^-3。

Examples 3 to 2

This example is different from example 3-1 in that: x =0.258 and y = 0.468.

Examples 3 to 3

This example is different from example 3-1 in that: x =0.60 and y = 0.95.

Comparison of the anti-reflection and SMSR characteristics of the diffraction grating layer 370 of embodiments 3-1 to 3 shows that the SMSR yield and anti-reflection performance of this embodiment is better than that of the conventional index coupled dfb laser, as shown in fig. 31 and 32, where x =0.258 and y =0.468 is the best performance. As can be seen in fig. 31: the ratio of SMSR greater than 35dB is maximum when x =0.258 and y = 0.468; as can be seen from fig. 32: when x =0.258 and y =0.468, the RIN value is the smallest, which means the best anti-reflection performance.

Examples 3 to 4

The structure of this embodiment is the same as that of embodiment 3-1, and the material of the diffraction grating layer 370 is Fe-doped semi-insulating In_1- _xGa_xAs_yP_1-yThe component x =0.258, y =0.468, the doping concentration of Fe D_Fe=5e16 cm^-3Thickness T of diffraction grating layer 370_g=200nm, grating period Λ =204 nm; the first cladding 320 thickness T_c=50nm, doping concentration D_c=1e18 cm^-3(ii) a The second cladding 321 thickness T_b=10nm, doping concentration D_b=1e18 cm^-3。

Examples 3 to 5

This example differs from examples 3-4 in that: fe doping concentration D_Fe=1.5e18 cm^-3。

Examples 3 to 6

This example differs from examples 3-4 in that: fe doping concentration D_Fe=2e18 cm^-3。

Examples 3 to 4 to examples 3 to 6The results of comparing the anti-reflection and SMSR characteristics of different materials of the diffraction grating layer 370 are shown in fig. 33 and 34, and it can be seen from fig. 33 that: when D is present_Fe=1.5e18 cm^-3The SMSR is higher than 35 dB; as can be seen from fig. 34: d_Fe=1.5e18 cm^-3The resistance with the lowest RIN value is obtained, namely the reflection performance is optimal.

Examples 3 to 7

The structure of this embodiment is the same as that of embodiment 3-1, and the material of the diffraction grating layer 370 is Fe-doped semi-insulating In_1- _xGa_xAs_yP_1-yThe component x =0.258, y =0.468, the doping concentration of Fe D_Fe=1.5e18 cm^-3Thickness T_g=10, grating period Λ =204 nm; the first cladding 320 thickness T_c=50nm, doping concentration D_c=1e18 cm^-3(ii) a The second cladding 321 thickness T_b=10nm, doping concentration D_b=1e18 cm^-3。

Examples 3 to 8

This example differs from examples 3-7 in that: t of the diffraction grating layer 370_g=200nm。

Examples 3 to 9

This example differs from examples 3-7 in that: t of the diffraction grating layer 370_g=500nm。

The results of comparing the anti-reflection and SMSR characteristics of the diffraction grating layers 370 of examples 3-7 to 3-9 for different materials are shown in fig. 35 and 36, and it can be seen from fig. 35 that: t is_gThe highest ratio of SMSR greater than 35dB when the wavelength is 200 nm; as can be seen from fig. 36: t is_gRIN value minimum anti-reflection performance is optimal when the wavelength is 200 nm.

Examples 3 to 10

The structure of this embodiment is the same as that of embodiment 3-1, and the material of the diffraction grating layer 370 is Fe-doped semi-insulating In_1- _xGa_xAs_yP_1-yThe component x =0.258, y =0.468, the doping concentration of Fe D_Fe=1.5e18 cm^-3Thickness T_g=200nm, grating period Λ =204 nm; the first cladding 320 thickness T_c=50nm, doping concentration D_c=1e18 cm^-3(ii) a The above-mentionedSecond cladding 321 thickness T_b=10nm, doping concentration D of the second cladding layer 321_b=1e17 cm^-3。

Examples 3 to 11

This example differs from examples 3-10 in that: absolute doping concentration D_b=1e18cm^-3。

Examples 3 to 12

This example differs from examples 3-10 in that: absolute doping concentration D_b=2e18cm^-3。

The results of comparing the anti-reflection and SMSR characteristics of the diffraction grating layers 370 of examples 3-10 to examples 3-12 are shown in fig. 37 and 38, and it can be seen from fig. 37 that: d_b=1e18 cm^-3The SMSR is higher than 35 dB; as can be seen from fig. 38: d_b=1e18 cm^-3The RIN value is the lowest, so the anti-reflection performance is optimal.

Examples 3 to 13

The diffraction grating layer 370 is made of Fe-doped semi-insulating In_1-xGa_xAs_yP_1-yThe component x =0.258, y =0.468, the doping concentration of Fe D_Fe=1.5e18 cm^-3Thickness T_g=200nm, grating period Λ =204 nm; first cladding 320 thickness T_c=50nm, doping concentration D_c=1e18 cm^-3(ii) a Second cladding 321 thickness T_b=0, doping concentration D_b=1e18 cm^-3。

Examples 3 to 14

This example differs from examples 3 to 13 in that: the second cladding 321 thickness T_b=10nm。

Examples 3 to 15

This example differs from examples 3 to 13 in that: the second cladding 321 thickness T_b=500nm。

The results of comparing the anti-reflection and SMSR characteristics of the diffraction grating layer 370 of examples 3-13 to examples 3-15 are shown in fig. 39 and 40, and it can be seen from fig. 39 that: t is_bThe highest occupation ratio when the SMSR is more than 35dB when the SMSR is 10 nm; as can be seen from fig. 40: t is_bRIN value is lowest at 10nm, so anti-reflectionThe performance is optimal.

Referring to fig. 41 and 42, a semiconductor device 200 is provided. The semiconductor device 200 includes a fourth substrate 410, a seventh confinement layer 430, a fourth active layer 440, an eighth confinement layer 450, and a fourth electron confinement layer 460. The seventh confinement layer 430, the fourth active layer 440, and the eighth confinement layer 450 are disposed on a surface of the fourth substrate 410. The fourth electron confinement layer 460 is disposed on the surface of the eighth confinement layer 450 away from the fourth active layer 440 (see fig. 41). Alternatively, the fourth electron confinement layer 460 is disposed between the eighth confinement layer 450 and the fourth active layer 440 (see fig. 42). Wherein a forbidden band width of the fourth electron confinement layer 460 is greater than a forbidden band width of the fourth active layer 440. And the forbidden band width of the fourth electron confinement layer 460 is greater than that of the eighth confinement layer 450.

In this embodiment, the forbidden band width of the fourth electron confinement layer 460 is greater than the forbidden band width of the fourth active layer 440 and greater than the forbidden band width of the eighth confinement layer 450. The fourth electron confinement layer 460 forms a conduction band energy level difference with respect to the fourth active layer 440 or the eighth confinement layer 450. When the electrons of the fourth active layer 440 move to the eighth confinement layer 450, the fourth electron confinement layer 460 can effectively confine the electrons due to the large difference between the conduction band energy levels of the fourth electron confinement layer 460 and the fourth active layer 440 and the small electron energy, so that the electrons cannot escape from the fourth active layer 440. Since the difference between the conduction band energy levels of the fourth electron confinement layer 460 and the eighth confinement layer 450 is also large, and the electron energy is small, electrons are also confined. Even in a high temperature environment, although the energy of electrons is increased, the fourth electron confinement layer 460 has a conduction band energy level difference with the fourth active layer 440 and the eighth confinement layer 450, respectively, and can effectively confine electrons, thereby confining electrons in the fourth active layer 440.

The valence band energy level difference between the fourth electron confinement layer 460 and the fourth active layer 440 and between the fourth electron confinement layer 450 and the eighth confinement layer 450 is small relative to the valence band energy level of the holes, so that the probability of the holes entering the fourth active layer 440 can be increased. Therefore, under the condition of an applied current, the particles of the fourth active layer 440 realize population inversion, electrons in a low energy level are stimulated to transit to a high energy level, and then spontaneously transit from the high energy level to the low energy level to be combined with holes, and simultaneously emit photons to generate light output power. The eighth confinement layer 450 and the seventh confinement layer 430 may serve as graded layers of energy levels of the fourth active layer 440 with respect to the fourth active layer 440. By disposing the fourth electron confinement layer 460 (see fig. 41) above the eighth confinement layer 450 or disposing the fourth electron confinement layer 460 (see fig. 42) above the fourth active layer 440, electrons can be effectively confined in the fourth active layer 440, so that the recombination efficiency of electrons and holes is improved, and the light output is improved.

Therefore, by disposing the fourth electron confinement layer 460 on the surface of the eighth confinement layer 450 away from the fourth active layer 440 (see fig. 41) or disposing the fourth electron confinement layer 460 between the eighth confinement layer 450 and the fourth active layer 440 (see fig. 42), the migration of electrons can be effectively confined, the electron overflow phenomenon can be prevented, the recombination efficiency of electrons and holes in the fourth active layer 440 can be increased, and the light output power under the high temperature working environment can be increased, so that the light output power meets the requirement. Therefore, the semiconductor device 200 provided by the present application improves the electron injection efficiency of the quantum well and the radiation recombination efficiency of electrons and holes, thereby improving the light extraction power of the semiconductor device at high temperature. At this moment, through the semiconductor device 200 provided by the present application, it is not necessary to adopt aspheric lens package to improve the light output power, and the packaging difficulty is reduced. In addition, the semiconductor device 200 provided by the application does not use an expensive TO pipe cap in the packaging process, so that the packaging cost is reduced.

In one embodiment, the fourth electron confining layer 460 includes In_xAl_(1-x)And an As layer. The fourth active layer 440 includes an InGaAsP layer. The eighth confinement layer 450 comprises a P-type InGaAsP layer (P-InGaAsP). The seventh confinement layer 430Is an N-type InGaAsP layer (N-InGaAsP).

In this embodiment, the fourth electron confinement layer 460 comprises In_xAl_(1-x)And the As layer is an indium aluminum arsenic material. In a semiconductor, electrons move from an N-type semiconductor to a P-type semiconductor, whereas holes move in the opposite direction. In_xAl_(1-x)The As has a band gap of 1.33eV to 1.71eV, and the InGaAsP has a band gap of 0.58eV to 0.93 eV. At this time, the band gap of the fourth electron confinement layer 460 is greater than the band gap of the fourth active layer 440 and the band gap of the eighth confinement layer 450. The fourth electron confinement layer 460 has a conduction band difference of about 0.8eV with respect to the fourth active layer 440 or the eighth confinement layer 450. Electrons In the fourth InGaAsP active layer move to the P-type InGaAsP layer due to In_xAl_(1-x)The difference between the conduction band energy levels of As and InGaAsP is large, and the energy of electrons is small, so that the electrons cannot escape from the fourth active layer of InGaAsP. In although the energy of electrons increases even In a high-temperature environment_xAl_(1-x)The difference between the conduction band energy levels of As and InGaAsP can still effectively confine electrons, so that the electrons are limited in the fourth active layer of InGaAsP. In with respect to holes_xAl_(1-x)The valence band energy level difference between As and InGaAsP is small, which can increase the probability of holes entering the fourth active layer of InGaAsP. Therefore, the fourth electron confinement layer 460 can increase the recombination efficiency of electrons and holes in the InGaAsP fourth active layer, and improve the light output power in a high-temperature working environment.

In this embodiment, the fourth electron confining layer 460 (i.e., the In) is adjusted within a range of 0.4 to 0.6_xAl_(1-x)As layer), the stress of the fourth electron-confining layer 460 can be adjusted. At this time, the stress adjusted in the range of x from 0.4 to 0.6 is: -0.2% Pa to 0.2% Pa. Said In_xAl_(1-x)The As layer is stressed by two kinds of compressive stress and tensile stress. When the stress is too large, defects in the growth of the material increase, resulting in deterioration of the reliability of the semiconductor device. Therefore, the passing through is between 0.4 and 0Adjusting the fourth electron-confining layer 460 (i.e., the In) within the range of 6_xAl_(1-x)As layer) can adjust the stress of the fourth electron confining layer 460, such that the compressive stress of the fourth electron confining layer 460 is 0.0% Pa to 0.2% Pa and the tensile stress is-0.2% Pa to 0.0% Pa. Thus, by adjusting the fourth electron confining layer 460 (i.e., the In) In the range of 0.4 to 0.6_xAl_(1-x)As layer) improves the reliability of the semiconductor device 200 described herein.

In one embodiment, the fourth electron-binding layer 460 includes In doped with an iron element_xAl_(1-x)As layer or In doped with zinc element_xAl_(1-x)And an As layer.

In this embodiment, the doping material of the fourth electron confinement layer 460 is Fe or Zn, both of which can improve the current injection efficiency. Wherein, the In_xAl_(1-x)The doping concentration of iron element or zinc element in the As layer is 5e17cm^-3To 10e17cm^-3. When the doping concentration is lower than 5e17cm^-3In this case, current injection efficiency may be reduced, and current may not be effectively injected into the fourth active layer 440. When the doping concentration is higher than 10e17cm^-3In this case, the current may be diffused, which may deteriorate the reliability of the semiconductor device. Therefore, by setting the doping concentration of the iron element or the zinc element in the fourth electron-confining layer 460 at 5e17cm^-3To 10e17cm^-3In this range, the reliability of the semiconductor device 200 according to the present application can be improved.

Preferably, the fourth electron confinement layer 460 includes In doped with an iron element_xAl_(1-x)As layer, and the In_xAl_(1-x)The doping concentration of the iron element in the As layer is 5e17cm^-3To 10e17cm^-3. In this case, the semiconductor device 200 according to the present application has high reliability.

In one embodiment, the thickness of the fourth electron-binding layer 460 is 20nm to 80 nm.

In this embodiment, the thickness of the fourth electron confinement layer 460 is set to be in the range of 20nm to 80nm, so that the fourth electron confinement layer 460 can play a good role in confining electrons, the electron confinement effect is obvious, the radiation recombination probability of electrons and holes of the fourth active layer 440 is high, and the light output power of the semiconductor device 200 is improved.

Referring to fig. 41 and 42, in an embodiment, the semiconductor device 200 further includes a seventh cladding layer 420, a plurality of fourth grating strips 407, and an eighth cladding layer 480. The seventh cladding layer 420 is disposed between the fourth substrate 410 and the seventh confinement layer 430. The plurality of fourth grating strips 407 are disposed at intervals on the surface of the fourth electron confinement layer 460 away from the eighth confinement layer 450. Alternatively, the plurality of fourth grating strips 407 are disposed at intervals on the surface of the eighth confinement layer 450 away from the fourth electron confinement layer 460. The eighth cladding layer 480 is disposed between the surfaces of the plurality of fourth grating strips 407 and the plurality of fourth grating strips 407. And the eighth cladding layer 480 is provided with a ridge waveguide structure (not shown).

In this embodiment, the seventh cladding layer 420 and the eighth cladding layer 480 may be InP material. The seventh cladding layer 420 is an N-InP material and the eighth cladding layer 480 is a P-InP material. The seventh clad layer 420 is disposed on the surface of the fourth substrate 410, and covers the fourth substrate 410 to perform a buffer function. The plurality of fourth grating strips 407 form a diffraction grating layer. Under the diffraction of the diffraction grating layer, the light with the wavelength of the single longitudinal mode is output, and single-wave light emission is formed. The eighth cladding layer 480 is disposed between the surfaces of the fourth grating strips 407 and the fourth grating strips 407, and covers the fourth grating strips 407 and fills gaps between the fourth grating strips 407. At this time, a large difference in refractive index is formed between the eighth cladding layer 480 and the plurality of fourth grating strips 407. The eighth cladding layer 480 is provided with a ridge waveguide structure, and has the advantages of high power, long-distance transmission and the like.

In one embodiment, the semiconductor device 200 further includes a fourth ohmic contact layer 490, a seventh metal electrode layer 401, and an eighth metal electrode layer 402. The fourth ohmic contact layer 490 is disposed on a surface of the ridge waveguide structure away from the plurality of fourth grating strips 407. The seventh metal electrode layer 401 is disposed on the surface of the fourth ohmic contact layer 490 away from the eighth cladding layer 480. The eighth metal electrode layer 402 is disposed on a surface of the fourth substrate 410 away from the seventh cladding layer 420. The seventh metal electrode layer 401 is a P-metal electrode layer. The eighth metal electrode layer 402 is an N-metal electrode layer. The material of the fourth ohmic contact layer 490 may be InGaAs material.

Referring to fig. 43, in one embodiment, the eighth metal electrode layer 402, the fourth substrate 410, the seventh cladding layer 420, the seventh confinement layer 430, the fourth active layer 440, the eighth confinement layer 450, the fourth electron confinement layer 460, the plurality of fourth grating strips 407, the eighth cladding layer 480, the fourth ohmic contact layer 490 and the seventh metal electrode layer 401 form a matrix structure (not labeled). The semiconductor device 200 further includes a fourth highly reflective coating 403 and a fourth highly transmissive coating 404. The fourth high reflection coating 403 is disposed on the first end surface of the base structure parallel to the long axis of the fourth grating bar 407. The fourth high transmittance plating layer 404 is disposed on the second end surface of the base structure parallel to the long axis of the fourth grating strips 407. The first end face is arranged opposite to the second end face.

In this embodiment, the eighth metal electrode layer 402, the fourth substrate 410, the seventh cladding layer 420, the seventh confinement layer 430, the fourth active layer 440, the eighth confinement layer 450, the fourth electron confinement layer 460, the plurality of fourth grating strips 407, the eighth cladding layer 480, the fourth ohmic contact layer 490 and the seventh metal electrode layer 401 form a matrix structure (not shown), which can be regarded as a whole structure. As shown in fig. 43, the fourth high reflection coating 403 is provided on the first end surface of the base structure parallel to the long axis of the fourth grating bars 407, i.e., the left end surface in fig. 43. The second end face is disposed opposite to the first end face, i.e., a right-side end face in fig. 43. The long axis direction of the fourth grating strips 407 is an axis parallel to the longitudinal direction of the fourth grating strips 407, i.e., a direction shown in a left position in fig. 43. At this time, the eighth metal electrode layer 402, the fourth substrate 410, the seventh clad layer 420, the seventh confinement layer 430, the fourth active layer 440, the eighth confinement layer 450, the fourth electron confinement layer 460, the plurality of fourth grating strips 407, the eighth clad layer 480, the fourth ohmic contact layer 490, and the seventh metal electrode layer 401 are disposed between the fourth highly reflective coating 403 and the fourth highly transmissive coating 404. As shown by the arrows in fig. 41, the end plated with the fourth high-transmittance plating layer 404 is the light-emitting end, that is, the side of the fourth high-transmittance plating layer 404 is the light-emitting end of the semiconductor device 200.

s10: providing a fourth substrate 410, and growing a seventh confinement layer 430 and a fourth active layer 440 on the surface of the fourth substrate 410;

s201: growing an eighth confinement layer 450 on a surface of the fourth active layer 440 away from the seventh confinement layer 430;

s203: growing a fourth electron confinement layer 460 on a surface of the eighth confinement layer 450 away from the fourth active layer 440;

wherein a forbidden band width of the fourth electron confinement layer 460 is greater than a forbidden band width of the fourth active layer 440, and a forbidden band width of the fourth electron confinement layer 460 is greater than a forbidden band width of the eighth confinement layer 450.

In this embodiment, in the method for manufacturing a semiconductor device, Metal-organic Chemical Vapor Deposition (MOCVD) is used to grow the seventh confinement layer 430, the fourth active layer 440, the eighth confinement layer 450, and the fourth electron confinement layer 460 on the surface of the fourth substrate 410. According to the semiconductor device manufacturing method, during epitaxial growth, the fourth electron confinement layer 460 with a larger conduction band energy level difference relative to the fourth active layer 440 is grown above the fourth active layer 440, so that electrons at high temperature can still be effectively confined in the fourth active layer 440, the electron overflow phenomenon is reduced, and the light output power at high temperature is improved.

At this time, the fourth electron confinement layer 460 prepared by the semiconductor device preparation method is disposed on the surface of the eighth confinement layer 450 far from the fourth active layer 440 (see fig. 41), so that migration of electrons can be effectively confined, an electron overflow phenomenon can be prevented, recombination efficiency of electrons and holes in the fourth active layer 440 can be increased, and further, the light output power under a high-temperature working environment can be increased, so that the light output power meets requirements. At this time, the semiconductor device 200 manufactured by the semiconductor device manufacturing method does not need to be packaged by an aspheric lens to improve the light output power, and the packaging difficulty is reduced. In addition, the semiconductor device 200 provided by the application does not use an expensive TO pipe cap in the packaging process, so that the packaging cost is reduced.

s202: growing the fourth electron confinement layer 460 on the surface of the fourth active layer 440 away from the seventh confinement layer 430;

s204: growing the eighth confinement layer 450 at a surface of the fourth electron-confining layer 460 away from the fourth active layer 440;

In this embodiment, in the semiconductor device manufacturing method, MOCVD is adopted to grow the seventh confinement layer 430, the fourth active layer 440, the fourth electron confinement layer 460, and the eighth confinement layer 450 on the surface of the fourth substrate 410. The fourth electron confinement layer 460 is disposed between the eighth confinement layer 450 and the fourth active layer 440 (see fig. 42), and can effectively confine the migration of electrons, prevent the electron overflow phenomenon, increase the recombination efficiency of electrons and holes in the fourth active layer 440, and further improve the light output power in the high-temperature working environment, so that the light output power meets the requirement.

In one embodiment, In is employed_xAl_(1-x)The As material grows the fourth electron confinement layer 460 on the surface of the eighth confinement layer 450 away from the fourth active layer 440. Or In is used_xAl_(1-x)The As material grows the fourth electron confinement layer 460 on the surface of the fourth active layer 440 away from the seventh confinement layer 430. Wherein, In_xAl_(1-x)The value of x in the As material is in the range of 0.4 to 0.6. The stress of the fourth electron confinement layer 460 during growth is-0.2% Pa to 0.2% Pa.

In this embodiment, a layer of the fourth electron confinement layer 460 (In) with stress is grown by epitaxial technique on top of the eighth confinement layer 450 (P-InGaAsP layer) or the fourth active layer 440 (InGaAsP layer)_xAl_(1-x)As layer). The stress is controlled by adjusting the composition of x In the range of 0.4 to 0.6, so that the stress of the fourth electron confinement layer 460 during growth is-0.2% Pa to 0.2% Pa, thereby enabling In_xAl_(1-x)The As layer is better lattice matched with the P-InGaAsP layer or the InGaAsP fourth active layer. Meanwhile, the P-InGaAsP layer or the InGaAsP fourth active layer can be made to be In by adjusting the composition of x In the range of 0.4 to 0.6 to control the stress magnitude_xAl_(1-x)The As layer forms a form of level grading. And, In_xAl_(1-x)The As layer has a forbidden bandwidth larger than that of the P-InGaAsP layer or the InGaAsP fourth active layer, so that the electron overflow phenomenon can be effectively prevented, the high-temperature light output power of the chip is improved, and the problem of insufficient high power is solved. The preparation process is simple and stable, and the light output power under the high-temperature environment meets the high-power requirement. Therefore, by the semiconductor device manufacturing method, aspheric surface packaging is not needed, expensive TO pipe caps are not used in the packaging process, and packaging cost is reduced.

In one embodiment, In doped with iron or zinc is used_xAl_(1-x)The As material grows the fourth electron confinement layer 460 on the surface of the eighth confinement layer 450 away from the fourth active layer 440. Or In doped with iron or zinc_xAl_(1-x)The As material grows the fourth electron confinement layer 460 on the surface of the fourth active layer 440 away from the seventh confinement layer 430. Wherein the doping concentration of the iron element or the zinc element is 5e17cm^-3To 10e17cm^-3. The relevant description in this embodiment may refer to the relevant embodiments described above.

Referring to fig. 44, in one embodiment, the epitaxial structure is grown as follows: an N-InP layer (a seventh cladding layer 420), an N-InGaAsP layer (a seventh confinement layer 430), an InGaAsP fourth active layer (a fourth active layer 440), a combination layer, and a diffraction grating layer material are sequentially grown on a surface of an InP fourth substrate 410 (also called a wafer) from bottom to top by using an MOCVD method. By means of photoetching and dry etching technologies, a plurality of diffraction fourth grating strips 407 are etched on the diffraction grating layer material, and a diffraction grating layer is obtained. Wherein the epitaxial structure includes an N-InP layer (seventh cladding layer 420), an N-InGaAsP layer (seventh confinement layer 430), an InGaAsP fourth active layer (fourth active layer 440), a combination layer, and a diffraction grating layer. The combined layers include a P-InGaAsP layer (eighth confinement layer 450) and a fourth electron confinement layer 460. The fourth electron confinement layer 460 is grown under the P-InGaAsP layer (the eighth confinement layer 450) or over the P-InGaAsP layer (the eighth confinement layer 450). Both structures can achieve the effect of preventing the electron overflow, and reference can be made to the above embodiments.

Referring to fig. 45, in one embodiment, the eighth cladding layer 480 is grown as follows: an eighth cladding layer 480 and a fourth ohmic contact layer 490 are sequentially grown on the plurality of fourth grating strips 407 by using the MOCVD growth technique. The eighth cladding layer 480 is made of P-InP material and the fourth ohmic contact layer 490 is made of InGaAs material, so as to obtain a semi-finished wafer.

Referring to FIG. 46, in one embodiment, a PECVD technique using PECVD is used to form a semi-finished wafer as shown in FIG. 45Layer SiO₂As an insulating layer, a layer of SiO is formed on the surface of the fourth ohmic contact layer 490₂. Then, a ridge waveguide pattern is formed on the insulating layer using a photolithography technique. And etched to form a ridge waveguide structure (not shown). Next, the insulating layer on the surface of the ridge waveguide structure is removed, and the fourth ohmic contact layer 490 is exposed. Finally, a P-metal electrode layer (a seventh metal electrode layer 401) is formed over the fourth ohmic contact layer 490 and the insulating layer, and the back surface of the InP fourth substrate 410 is thinned and polished to 100 μm ± 10 μm. Meanwhile, an N-metal electrode layer (eighth metal electrode layer 402) is plated on the back surface of the InP fourth substrate 410. And cutting the semi-finished wafer to obtain a chip semi-finished product, plating a fourth high-transmission coating 404 on one end (right side in the figure 46) of the chip semi-finished product, and plating a fourth high-reflection coating 403 on the opposite end (left side in the figure 46), so that the working temperature high-power semiconductor device can be prepared.

In one embodiment, the present application provides the following specific 12 embodiments:

example 4-1, referring to fig. 41, the semiconductor device 200 includes an InP fourth substrate 410, and an N-InP layer (seventh cladding layer 420), an N-InGaAsP layer (seventh confinement layer 430), an InGaAsP fourth active layer (fourth active layer 440), a P-InGaAsP layer (eighth confinement layer 450), a fourth electron confinement layer 460, and a diffraction grating layer (formed of a plurality of fourth grating strips 407) provided on the InP fourth substrate 410 in this order from bottom to top. The diffraction grating layer (formed by the plurality of fourth grating strips 407) is covered with an eighth cladding layer 480, a fourth ohmic contact layer 490, and a P-metal electrode layer (a seventh metal electrode layer 401) in sequence from bottom to top. The lower surface of the InP fourth substrate 410 is plated with an N-metal electrode layer (eighth metal electrode layer 402). One end face of the substrate structure (not labeled) parallel to the long axis of the fourth grating strip 407 is plated with a fourth high-transmittance plating layer 404, and the other opposite end face is plated with a fourth high-reflectance plating layer 403. The thickness D of the fourth electron confinement layer 460 is 20nm, and the fourth electron confinement layer 460 is In doped with Zn element_0.6Al_0.4As with a doping concentration of 5e17 in cm^-3. The stress of the fourth electron confinement layer 460 is compressive stressThe stress was 0.2% Pa.

Example 4-2 is the same in structure as example 4-1 except that: the thickness D of the fourth electron-binding layer 460 was 50 nm. The fourth electron confinement layer 460 is In doped with Zn element_0.5Al_0.5As and Zn element doping concentration of 7.5e17 unit cm^-3. The stress of the fourth electron confinement layer 460 is 0.0% Pa.

Example 4-3 is the same in structure as example 4-1 except that: the thickness D of the fourth electron-binding layer 460 was 80 nm. The fourth electron confinement layer 460 is In doped with Zn element_0.4Al_0.6As and Zn element doping concentration is 10e17, unit is cm^-3. The stress of the fourth electron confinement layer 460 is tensile stress, and the stress is-0.2% Pa.

Referring to fig. 47, fig. 47 is a graph showing an electron concentration distribution of the epitaxial structure, wherein the axis of ordinate is the electron concentration distribution and the axis of abscissa is the distance, i.e., the height from the InP fourth substrate 410. As can be seen from fig. 47, the electron concentration distribution is significantly different between when the fourth electron confinement layer 460 is grown and when the fourth electron confinement layer 460 is not grown in the epitaxial structure. When the fourth electron confinement layer 460 was not grown, the electron concentration over the P-InGaAsP (eighth confinement layer 450) reached 16cm^-3. While the electron concentration above the fourth electron confinement layer 460 is 12cm when the fourth electron confinement layer 460 is grown^-3. This proves that the electron overflow phenomenon can be effectively prevented and the electron-hole recombination efficiency of the InGaAsP fourth active layer (fourth active layer 440) can be improved by using the structure of epitaxially growing the fourth electron confinement layer 460.

The P-I (mW-mA) curves of examples 4-1, 4-2 and 4-3 are shown in FIG. 48. As can be seen from fig. 48, the conventional structure without the fourth electron confinement layer 460 grown and the semiconductor device 200 of the present application show a significant difference in light extraction power at 85 ℃. For high power, when the driving current is 120mA, the working environment is 85 ℃, and the light extraction power needs more than 70 mW. The structure without the fourth electron confinement layer 460 has an emergent power of 48mW under a high-temperature working environment and a driving current of 120 mA. However, in the structures of the embodiments 4-1, 4-2, and 4-3 of the present application, in a high-temperature working environment, when the driving current is 120mA, the light-emitting power can reach more than 70mW, and the light-emitting requirement of a larger light-emitting power in the high-temperature working environment is satisfied.

Example 4-4, referring to fig. 42, the semiconductor device 200 includes an InP fourth substrate 410, and an N-InP layer (seventh cladding layer 420), an N-InGaAsP layer (seventh confinement layer 430), an InGaAsP fourth active layer (fourth active layer 440), a fourth electron confinement layer 460, a P-InGaAsP layer (eighth confinement layer 450), and a diffraction grating layer (formed of a plurality of fourth grating strips 407) provided on the InP fourth substrate 410 in this order from bottom to top. The diffraction grating layer (formed by the plurality of fourth grating strips 407) is covered with an eighth cladding layer 480, a fourth ohmic contact layer 490, and a P-metal electrode layer (a seventh metal electrode layer 401) in sequence from bottom to top. The lower surface of the InP fourth substrate 410 is plated with an N-metal electrode layer (eighth metal electrode layer 402). One end face of the substrate structure (not labeled) parallel to the long axis of the fourth grating strip 407 is plated with a fourth high-transmittance plating layer 404, and the other opposite end face is plated with a fourth high-reflectance plating layer 403. The thickness D of the fourth electron-binding layer 460 was 20 nm. The fourth electron confinement layer 460 is In doped with Zn element_0.6Al_0.4As and Zn element doping concentration is 5e17 with unit of cm^-3. The stress of the fourth electron confinement layer 460 is compressive stress, and the stress is 0.2% Pa.

Examples 4 to 5, the same as examples 4 to 4, were structured except that: the thickness D of the fourth electron-binding layer 460 was 50 nm. The fourth electron confinement layer 460 is In doped with Zn element_0.5Al_0.5As and Zn element doping concentration is 7.5e17, unit is cm^-3. The stress of the fourth electron confinement layer 460 is 0.0% Pa.

Examples 4-6 are the same as examples 4-4 except that: the thickness D of the fourth electron-binding layer 460 was 80 nm. The fourth electron confinement layer 460 is In doped with Zn element_0.4Al_0.6As and Zn element doping concentration is 10e17, unit is cm^-3. The stress of the fourth electron confinement layer 460 is tensile stress, and the stress is-0.2% Pa.

The P-I curves of examples 4-4, 4-5, and 4-6 are shown in FIG. 49. As can be seen from fig. 49, when the driving current is 120mA and the working environment is 85 ℃, the light-emitting power can also reach more than 70mW, thereby satisfying the light-emitting requirement of higher light-emitting power in the high-temperature working environment.

Embodiments 4 to 7, referring to fig. 42, the semiconductor device 200 includes an InP fourth substrate 410, and an N-InP layer (seventh cladding layer 420), an N-InGaAsP layer (seventh confinement layer 430), an InGaAsP fourth active layer (fourth active layer 440), a fourth electron confinement layer 460, a P-InGaAsP layer (eighth confinement layer 450), and a diffraction grating layer (formed of a plurality of fourth grating strips 407) provided on the InP fourth substrate 410 in this order from bottom to top. The diffraction grating layer (formed by the plurality of fourth grating strips 407) is covered with an eighth cladding layer 480, a fourth ohmic contact layer 490, and a P-metal electrode layer (a seventh metal electrode layer 401) in sequence from bottom to top. The lower surface of the InP fourth substrate 410 is plated with an N-metal electrode layer (eighth metal electrode layer 402). One end face of the substrate structure (not labeled) parallel to the long axis of the fourth grating strip 407 is plated with a fourth high-transmittance plating layer 404, and the other opposite end face is plated with a fourth high-reflectance plating layer 403. The thickness D of the fourth electron-binding layer 460 was 20 nm. The fourth electron confinement layer 460 is In doped with Fe element_0.6Al_0.4As and Fe element doping concentration is 5e17 with unit of cm^-3. The stress of the fourth electron confinement layer 460 is compressive stress, and the stress is 0.2% Pa.

Examples 4-8 are the same as examples 4-7 except that: the thickness D of the fourth electron-binding layer 460 was 50 nm. The fourth electron confinement layer 460 is In doped with Fe element_0.5Al_0.5As and Fe element doping concentration is 7.5e17 with unit of cm^-3. The stress of the fourth electron confinement layer 460 is 0.0% Pa.

Examples 4-9 and 4-1 have the same structure except that: the thickness D of the fourth electron-binding layer 460 was 80 nm. The fourth electron confinement layer 460 is In doped with Fe element_0.4Al_0.6As and Fe element doping concentration is 10e17, and the unit is cm^-3. The stress of the fourth electron confining layer 460 adopts a tensile stress,the stress was-0.2% Pa.

The P-I curves of examples 4-7, examples 4-8, and examples 4-9 in the above examples are shown in FIG. 50. As can be seen from fig. 50, when the driving current is 120mA and the working environment is 85 ℃, the light-emitting power can reach more than 70mW, and the light-emitting requirement of higher light-emitting power in the high-temperature working environment is met.

In embodiments 4 to 10, referring to fig. 42, the semiconductor device 200 includes an InP fourth substrate 410, and an N-InP layer (a seventh cladding layer 420), an N-InGaAsP layer (a seventh confinement layer 430), an InGaAsP fourth active layer (a fourth active layer 440), a fourth electron confinement layer 460, a P-InGaAsP layer (an eighth confinement layer 450), and a diffraction grating layer (formed by a plurality of fourth grating strips 407) sequentially disposed on the InP fourth substrate 410 from bottom to top. The diffraction grating layer (formed by the plurality of fourth grating strips 407) is covered with an eighth cladding layer 480, a fourth ohmic contact layer 490, and a P-metal electrode layer (a seventh metal electrode layer 401) in sequence from bottom to top. The lower surface of the InP fourth substrate 410 is plated with an N-metal electrode layer (eighth metal electrode layer 402). One end face of the substrate structure (not labeled) parallel to the long axis of the fourth grating strip 407 is plated with a fourth high-transmittance plating layer 404, and the other opposite end face is plated with a fourth high-reflectance plating layer 403. The thickness D of the fourth electron-binding layer 460 was 20 nm. The fourth electron confinement layer 460 is In doped with Zn element_0.6Al_0.4As with a doping concentration of 5e17 in cm^-3. The stress of the fourth electron confinement layer 460 is compressive stress, and the stress is 0.2% Pa.

Examples 4 to 11 are the same in structure as examples 4 to 4 except that: the thickness D of the fourth electron-binding layer 460 was 50 nm. The fourth electron confinement layer 460 is In doped with Fe element_0.5Al_0.5As and Fe element doping concentration is 7.5e17 with unit of cm^-3. The stress of the fourth electron confinement layer 460 is 0.0% Pa.

Examples 4-12 are the same as examples 4-4 except that: the thickness D of the fourth electron-binding layer 460 was 80 nm. The fourth electron confinement layer 460 is In doped with Fe element_0.4Al_0.6As in cm^-3. Fourth electron confinementThe stress of layer 460 is tensile with a stress of-0.2% Pa.

The P-I curves of examples 4-10, examples 4-11, and examples 4-12 in the above examples are shown in FIG. 51. As can be seen from fig. 51, when the driving current is 120mA and the working environment is 85 ℃, the light-emitting power can also reach more than 70mW, thereby satisfying the light-emitting requirement of higher light-emitting power in the high-temperature working environment.

In one embodiment, the present application provides an industrial-temperature high-power laser chip including the semiconductor device 200 described in any of the above embodiments. The working temperature high-power laser chip has higher modulation rate, has higher light-emitting power in a high-temperature working environment, and can be used as a light source in optical communication so as to meet market demands.

In one embodiment, the present application provides an industrial-temperature high-power laser chip, which is prepared by using the semiconductor device preparation method described in any one of the above embodiments. The work temperature high-power laser chip prepared by the preparation method of the semiconductor device has higher modulation rate. Meanwhile, the work temperature high-power laser chip prepared by the preparation method of the semiconductor device has higher light emitting power in a high-temperature working environment, and can be used as a light source in optical communication to meet market demands.

In one embodiment, the semiconductor device 200 and the semiconductor device manufacturing method in the above embodiments can also be applied to other laser chip technologies.

Referring to fig. 52, the present application provides a laser chip 100. The laser chip 100 includes a fifth substrate 510, a ninth cladding layer 520, a ninth confinement heterojunction layer 530, a fifth active layer 540, and a tenth confinement heterojunction layer 550. The ninth clad layer 520 is disposed on a surface of the fifth substrate 510. The ninth confinement heterojunction layer 530 is disposed on a surface of the ninth cladding layer 520 away from the fifth substrate 510. The fifth active layer 540 is disposed on the surface of the ninth confinement heterojunction layer 530 far from the ninth cladding layer 520. The tenth confinement heterojunction layer 550 is disposed on a surface of the fifth active layer 540 away from the ninth confinement heterojunction layer 530. Wherein the ninth confinement heterojunction layer 530 has a gradually decreasing forbidden bandwidth and the tenth confinement heterojunction layer 550 has a gradually increasing forbidden bandwidth along the ninth cladding layer 520 to the tenth confinement heterojunction layer 550.

In this embodiment, the ninth cladding layer 520 is disposed on the surface of the fifth substrate 510, and covers the fifth substrate 510 to perform a buffering function. The ninth confinement heterojunction layer 530 and the tenth confinement heterojunction layer 550 are respectively disposed at both sides of the fifth active layer 540, i.e., the fifth active layer 540 is disposed between the ninth confinement heterojunction layer 530 and the tenth confinement heterojunction layer 550. At this time, a graded layer of the energy level of the fifth active layer 540 is formed by the ninth confinement heterojunction layer 530 and the tenth confinement heterojunction layer 550. Furthermore, a difference in forbidden bandwidth gradient is formed between the ninth confinement heterojunction layer 530 and the tenth confinement heterojunction layer 550, which can accelerate the movement of carriers in the heterojunction, thereby reducing the transit time of carriers in the heterojunction, improving the carrier injection efficiency, and increasing the photoelectric confinement effect to meet the requirement of high-speed modulation rate of 25GHZ or more.

Referring to fig. 53, in one embodiment, the ninth confinement heterojunction layer 530 comprises a plurality of ninth sub-confinement heterojunction layers 531. A plurality of ninth sub-confinement heterojunction layers 531 are sequentially disposed on the surface of the ninth cladding layer 520 away from the fifth substrate 510. The difference in the gradient of the forbidden band widths of the adjacent ninth sub-confinement heterojunction layers 531 is 20meV to 100 meV. And the band gap widths of the plurality of ninth sub-confinement heterojunction layers 531 become gradually smaller in the direction from the ninth cladding layer 520 to the fifth active layer 540.

In this embodiment, the plurality of ninth sub-confinement heterojunction layers 531 are sequentially disposed on the surface of the ninth cladding layer 520 away from the fifth substrate 510, and it can be understood that the plurality of ninth sub-confinement heterojunction layers 531 are stacked one by one on the surface of the ninth cladding layer 520 (the structure shown in fig. 53). In addition, the difference Δ E between the band gap widths between the materials of the adjacent two ninth sub-confinement heterojunction layers 531_g1Is 20 to 100 meV. At this time, the process of the present invention,the plurality of ninth sub-confinement heterojunction layers 531 are different in forbidden bandwidth. The ninth confinement heterojunction layer 530 includes n layers of the ninth sub-confinement heterojunction layer 531 having different material compositions, which are sequentially disposed from bottom to top.

Meanwhile, the plurality of ninth sub-confinement heterojunction layers 531 gradually decrease in energy gap width in the direction from the ninth cladding layer 520 to the fifth active layer 540 (from bottom to top), and thus a plurality of graded layers having different energy gap widths are formed. At this time, the ninth confinement heterojunction layer 530 forms a plurality of graded layers with gradually decreasing forbidden band widths, so that the movement of carriers in the heterojunction can be accelerated, the transit time of the carriers in the heterojunction is reduced, and the carrier injection efficiency is improved.

In one embodiment, the difference between the forbidden band widths of the adjacent ninth sub-confinement heterojunction layers 531 is 50 meV.

In this embodiment, the difference Δ E between the adjacent two ninth sub-confinement heterojunction layers 531 in gradient of the forbidden bandwidth between the materials_g1Is 50 meV. At this time, the band gap of the first ninth sub-confinement heterojunction layer 531 in the ninth confinement heterojunction layer 530 is 50meV larger than the band gap of the second ninth sub-confinement heterojunction layer 531 in the direction from the ninth cladding layer 520 to the fifth active layer 540 (from bottom to top). The second ninth sub-confinement heterojunction layer 531 has a band gap 50meV larger than that of the third ninth sub-confinement heterojunction layer 531. The band gap of the third ninth sub-confinement heterojunction layer 531 is 50meV larger than the band gap of the fourth ninth sub-confinement heterojunction layer 531. By analogy, a plurality of graded layers with gradually decreasing forbidden band widths are formed in the ninth confinement heterojunction layer 530.

By making the difference Δ E between the band gap widths between the materials of the adjacent two ninth sub-confinement heterojunction layers 531_g1The gradual change layer with 50meV as an interval is formed between the plurality of ninth sub-confinement heterojunction layers 531, so that the movement of carriers in the heterojunction can be accelerated, the transit time of the carriers in the heterojunction is further reduced, and the carrier injection efficiency is improved.

In one embodiment, theThe number of the ninth sub-confinement heterojunction layers 531 is [ (E)_gc1-E_gb）/ΔE_g1]_{Get the whole downwards}. Wherein E is_gc1Is the forbidden band width of the ninth cladding layer 520, E_gbIs the forbidden bandwidth, Δ E, of the barrier material in the fifth active layer 540_g1The difference in the forbidden band width between adjacent ninth sub-confinement heterojunction layers 531 is determined.

In this embodiment, the number of the ninth sub-confinement heterojunction layers 531 in the ninth confinement heterojunction layer 530 may be selected according to a difference between a forbidden bandwidth of the ninth cladding layer 520 and a forbidden bandwidth of a barrier material in the fifth active layer 540. At this time, according to [ (E)_gc1-E_gb）/ΔE_g1]_{Get the whole downwards}The number of the ninth sub-confinement heterojunction layers 531 may be set such that a plurality of ninth sub-confinement heterojunction layers 531 are formed between the ninth cladding layer 520 and the barrier in the fifth active layer 540. Furthermore, the plurality of ninth sub-confinement heterojunction layers 531 have a gradually decreasing forbidden bandwidth, and a plurality of gradually changing layers having a gradually decreasing forbidden bandwidth are formed between the potential barrier in the ninth cladding layer 520 and the fifth active layer 540, so that the movement of carriers in the heterojunction can be accelerated, the transit time of carriers in the heterojunction can be reduced, and the carrier injection efficiency can be improved.

Referring to fig. 54, in one embodiment, the laser chip 100 further includes a tenth cladding layer 560. The tenth cladding layer 560 is disposed on a surface of the tenth confinement heterojunction layer 550 away from the fifth active layer 540. The tenth confinement heterojunction layer 550 includes a plurality of tenth sub-confinement heterojunction layers 551. A plurality of tenth sub-confinement heterojunction layers 551 are sequentially disposed on the surface of the fifth active layer 540 away from the ninth confinement heterojunction layer 530. The difference in the band gap width between adjacent tenth confinement heterojunction layers 551 is 20meV to 100 meV. And the band gap widths of the tenth confinement heterojunction layers 551 gradually increase along the direction from the fifth active layer 540 to the tenth cladding layer 560.

In this embodiment, the tenth cladding layer 560 is disposed on the surface of the tenth confinement heterojunction layer 550 away from the fifth active layer 540The tenth confinement heterojunction layer 550 is covered to serve as a buffer. The tenth confinement heterojunction layer 551 is sequentially disposed on the surface of the fifth active layer 540 away from the ninth confinement heterojunction layer 530, which can be understood as that the tenth confinement heterojunction layer 551 is sequentially disposed on the surface of the fifth active layer 540 in a stacked manner (the structure shown in fig. 54). In addition, the difference Δ E between the band gap widths between the materials of the adjacent two tenth confinement heterojunction layers 551_g2Is 20 to 100 meV. At this time, the plurality of tenth confinement heterojunction layers 551 are different in band gap. The tenth confinement heterojunction layer 550 includes n layers of the tenth sub-confinement heterojunction layer 551 different in material composition, which are sequentially disposed from bottom to top.

Meanwhile, the plurality of tenth confinement heterojunction layers 551 gradually increase in band gap width in a direction from the fifth active layer 540 to the tenth cladding layer 560 (from bottom to top), and thus a plurality of graded layers having different band gaps are formed. At this time, the tenth confinement heterojunction layer 550 forms a plurality of graded layers with gradually increasing forbidden band widths, so that the movement of carriers in the heterojunction can be accelerated, the transit time of the carriers in the heterojunction is reduced, and the carrier injection efficiency is improved.

A plurality of graded layers having a gradually decreasing energy gap and a plurality of graded layers having a gradually increasing energy gap are formed on both sides of the fifth active layer 540 from bottom to top in this order by the plurality of ninth sub-confinement heterojunction layers 531 and the plurality of tenth sub-confinement heterojunction layers 551 on both sides of the fifth active layer 540. At this time, the fifth active layer 540 is bound between the plurality of ninth confinement heterojunction layers 531 and the plurality of tenth confinement heterojunction layers 551 to form an energy level graded layer, so that carriers can move rapidly, the transit time of the carriers is reduced, and the carrier injection efficiency is improved.

In one embodiment, the difference in the gradient of the forbidden band widths of the adjacent tenth confinement heterojunction layers 551 is 50 meV.

In this embodiment, the difference Δ E between the band gaps between the materials of the adjacent tenth confinement heterojunction layers 551 is the gradient_g2Is 50 meV. At this time, along the secondIn the direction from the five active layer 540 to the tenth cladding layer 560 (from bottom to top), the band gap width of the first tenth confinement heterojunction layer 551 in the tenth confinement heterojunction layer 550 is 50meV smaller than the band gap width of the second tenth confinement heterojunction layer 551. The second tenth confinement heterojunction layer 551 has a band gap 50meV smaller than that of the third tenth confinement heterojunction layer 551. The band gap of the third tenth confinement heterojunction layer 551 is 50meV smaller than that of the fourth tenth confinement heterojunction layer 551. By analogy, a plurality of graded layers with gradually increasing forbidden band widths are formed in the tenth confinement heterojunction layer 550.

The difference Delta E of the forbidden band width between the materials of two adjacent tenth confinement heterojunction layers 551 is determined_g2The thickness of the layer is 50meV, a gradual change layer which changes gradually with 50meV as an interval is formed between the tenth confinement heterojunction layers 551, so that the movement of carriers in the heterojunction can be accelerated better, the transit time of the carriers in the heterojunction is further reduced, and the carrier injection efficiency is improved.

In one embodiment, the tenth confinement heterojunction layer 551 has a number of [ (E)_gc2-E_gb）/ΔE_g2]_{Get the whole downwards}. Wherein E is_gc2Is the forbidden band width of the tenth clad layer 560, E_gbIs the forbidden bandwidth, Δ E, of the barrier material in the fifth active layer 540_g2The difference in the band gap between adjacent tenth confinement heterojunction layers 551 is a gradient.

In this embodiment, the number of the tenth confinement heterojunction layer 551 in the tenth confinement heterojunction layer 550 may be selected according to a difference between a forbidden bandwidth of the tenth cladding layer 560 and a forbidden bandwidth of the barrier material in the fifth active layer 540. At this time, according to [ (E)_gc2-E_gb）/ΔE_g2]_{Get the whole downwards}The tenth confinement heterojunction layer 551 may be provided in number such that a plurality of tenth confinement heterojunction layers 551 are formed between the tenth cladding layer 560 and the barrier in the fifth active layer 540. The plurality of tenth confinement heterojunction layers 551 have a gradually increasing band gap, and the tenth cladding layer 560 and the fifth cladding layer haveA plurality of gradient layers with gradually increasing forbidden band widths are formed between the potential barriers in the source layer 540, so that the movement of carriers in the heterojunction can be accelerated, the transit time of the carriers in the heterojunction is reduced, and the carrier injection efficiency is improved.

In one embodiment, E_gc1A forbidden band width at 25 ℃ of a material used for the ninth clad layer 520, E_gbIs the forbidden band width at 25 ℃ of the barrier material in the fifth active layer 540, Delta E_g1A difference in gradient of a band gap at 25 ℃ of the adjacent ninth sub-confinement heterojunction layer 531. E_gc2A forbidden band width at 25 ℃ of a material used for the tenth clad layer 560, E_gbIs the forbidden band width at 25 ℃ of the barrier material in the fifth active layer 540, Delta E_g2A difference in gradient of a band gap at 25 ℃ of the adjacent tenth confinement heterojunction layer 551.

In the present embodiment, the number of the ninth sub-confinement heterojunction layer 531 and the number of the tenth sub-confinement heterojunction layer 551 are calculated by taking a band gap at 25 ℃. At this time, the band gap E of the barrier material in the fifth active layer 540 at 25 ℃_gbIs 1.18 eV. The temperature is not particularly limited in the application, and the forbidden band width can be other degrees centigrade.

In one embodiment, the ninth confinement heterojunction layer 530 comprises InGaAlAs doped N-type with a doping concentration in the range of 5e17cm^-3To 20e17cm^-3。

In this embodiment, the doping concentration range of the N-type doping in the ninth confinement heterojunction layer 530 is set to 5e17cm^-3To 20e17cm^-3The carrier concentration level in the material can be increased, and the scattering and accumulation of carriers at the heterojunction interface are reduced, so that the transit time of the carriers in the ninth confinement heterojunction layer 530 is reduced, and the carrier injection efficiency is improved.

In one embodiment, the doping concentration of the N-type doping in the ninth confinement heterojunction layer 530 is Dnsch =1.5e18cm^-3。

In one embodiment, the tenth confinement heterojunction layer 550 comprises P-doped InGaAlAs with a doping concentration dspsch in the range of 5e17cm^-3To 20e17cm^-3。

In the present embodiment, the doping concentration range of the P-type doping in the tenth confinement heterojunction layer 550 is set to 5e17cm^-3To 20e17cm^-3The carrier concentration level in the material can be increased, and the scattering and accumulation of carriers at the heterojunction interface can be reduced, so that the transit time of carriers in the tenth confinement heterojunction layer 550 can be reduced, and the carrier injection efficiency can be improved.

In one embodiment, the doping concentration of the P-type doping in the tenth confinement heterojunction layer 550 is dspsch =10e17 cm^-3。

Therefore, by setting the doping concentration and forbidden bandwidth gradient of the ninth confinement heterojunction layer 530 and the tenth confinement heterojunction layer 550 between the potential barrier in the fifth active layer 540 and the ninth cladding layer 520 and the tenth cladding layer 560 respectively to increase the carrier concentration level in the material and reduce the scattering and accumulation of carriers at the heterojunction interface, thereby realizing the reduction of the transit time of carriers in the ninth confinement heterojunction layer 530 and the tenth confinement heterojunction layer 550 and improving the carrier injection efficiency.

Referring to fig. 55, in one embodiment, the ninth confinement heterojunction layer 530 has a thickness ranging from 10nm to 200 nm. The thickness of the tenth confinement heterojunction layer 550 ranges from 10nm to 200 nm.

In the present embodiment, the thickness Tnsch of the ninth confinement heterojunction layer 530 ranges from 10nm to 200nm, preferably 100 nm. The thickness Tpsch of the tenth confinement heterojunction layer 550 ranges from 10nm to 200nm, preferably 50 nm.

By adjusting the thicknesses of the ninth confinement heterojunction layer 530 and the tenth confinement heterojunction layer 550 within the range of 10nm to 200nm, the equivalent refractive index distribution of the fifth active layer 540 can be improved, so that the confinement effect of carriers and photons in a quantum well is enhanced, the photon concentration in the fifth active layer 540 is increased, high-speed modulation with the bandwidth of more than 25G is realized, and the propulsion of 5G new infrastructure is assisted.

Referring to fig. 52, in one embodiment, the laser chip 100 further includes a fifth ohmic contact layer 570, a ninth metal electrode layer 501, a tenth metal electrode layer 502, a fifth highly reflective coating layer 503, and a fifth anti-reflective coating layer 504. The fifth ohmic contact layer 570 is disposed on a surface of the tenth cladding layer 560 away from the tenth confinement heterojunction layer 550. The ninth metal electrode layer 501 is disposed on the surface of the fifth ohmic contact layer 570 away from the tenth cladding layer 560. The tenth metal electrode layer 502 is disposed on the surface of the fifth substrate 510 away from the ninth cladding layer 520.

The fifth substrate 510, the ninth cladding layer 520, the ninth confinement heterojunction layer 530, the fifth active layer 540, the tenth confinement heterojunction layer 550, the tenth cladding layer 560, the fifth ohmic contact layer 570, the ninth metal electrode layer 501 and the tenth metal electrode layer 502 form a matrix structure (not labeled in the figure), which can be regarded as a whole structure. As shown in fig. 52, the fifth highly reflective coating layer 503 is disposed on the first side surface of the substrate structure (not shown). The fifth anti-reflective coating 504 is disposed on a second side of the substrate structure (not shown). The first side end face and the second side end face are arranged oppositely. As shown in fig. 52, the fifth highly reflective coating layer 503 is provided on the left end surface in fig. 52. The fifth antireflection coating 504 is provided on the right side end face in fig. 52.

At this time, the tenth metal electrode layer 502, the fifth substrate 510, the ninth cladding layer 520, the ninth limiting heterojunction layer 530, the fifth active layer 540, the tenth limiting heterojunction layer 550, the tenth cladding layer 560, the fifth ohmic contact layer 570, and the ninth metal electrode layer 501 are disposed between the fifth highly reflective coating layer 503 and the fifth anti-reflective coating layer 504. The end plated with the fifth anti-reflective coating 504 is a light-emitting end, that is, the light-emitting end of the laser chip 100 is located on one side of the fifth anti-reflective coating 504.

In one embodiment, the thickness Tn of the ninth cladding layer 520 is 0.2 μm to 3 μm, preferably 0.4 μm. Doping of the ninth cladding layer 520The concentration is 5e17cm^-3To 20e17cm^-3. The ninth cladding layer 520 is made of N-type InP and has a forbidden band width of E at 25 DEG C_gc1Is 1.43 eV. The value range of the doping concentration Dn of the N-type doping in the ninth cladding layer 520 is 5e17cm^-3To 20e17cm^-3Preferably 5e17cm^-3. The material of the tenth cladding layer 560 is P-type InP and the doping type is P-type doping.

The quantum well material of the fifth active layer 540 is undoped aluminum gallium indium arsenide (InGaAlAs). A forbidden band width E of 25 ℃ of the barrier material in the fifth active layer 540_gbThe range is 0.89eV to 1.38 eV. A forbidden band width E of 25 ℃ of the barrier material in the fifth active layer 540_gbIs 1.18 eV. The contact layer material of the fifth ohmic contact layer 570 is InGaAs, and the doping type is P-type doping.

In one embodiment, the present application provides a method for fabricating a laser chip, comprising the steps of:

providing a fifth substrate 510, and growing a ninth cladding layer 520 on the surface of the fifth substrate 510;

growing a ninth confinement heterojunction layer 530 on the surface of the ninth cladding layer 520 away from the fifth substrate 510;

growing a fifth active layer 540 on the surface of the ninth confinement heterojunction layer 530 away from the ninth cladding layer 520;

growing a tenth confinement heterojunction layer 550 on the surface of the fifth active layer 540 away from the ninth confinement heterojunction layer 530;

wherein the ninth confinement heterojunction layer 530 has a gradually decreasing forbidden bandwidth and the tenth confinement heterojunction layer 550 has a gradually increasing forbidden bandwidth along the ninth cladding layer 520 to the tenth confinement heterojunction layer 550.

In this embodiment, the laser chip manufacturing method deposits the ninth cladding layer 520 on the surface of the fifth substrate 510 by Metal-organic Chemical Vapor Deposition (MOCVD). The ninth confinement heterojunction layer 530, the fifth active layer 540 and the tenth confinement heterojunction layer 550 are sequentially deposited over the ninth cladding layer 520. The materials of the fifth active layer 540, the ninth confinement heterojunction layer 530 and the tenth confinement heterojunction layer 550 are all InGaAlAs, and the material composition thereof depends on the material forbidden bandwidth. The ninth confinement heterojunction layer 530 and the tenth confinement heterojunction layer 550 are both composed of material stacks with different forbidden band widths.

The ninth clad layer 520 is disposed on the surface of the fifth substrate 510, and covers the fifth substrate 510 to perform a buffer function. The ninth confinement heterojunction layer 530 and the tenth confinement heterojunction layer 550 are respectively disposed at both sides of the fifth active layer 540, i.e., the fifth active layer 540 is disposed between the ninth confinement heterojunction layer 530 and the tenth confinement heterojunction layer 550. Meanwhile, the band gap of the ninth confinement heterojunction layer 530 gradually decreases and the band gap of the tenth confinement heterojunction layer 550 gradually increases along the ninth cladding layer 520 to the tenth confinement heterojunction layer 550. At this time, a graded layer of the energy level of the fifth active layer 540 is formed by the ninth confinement heterojunction layer 530 and the tenth confinement heterojunction layer 550. Furthermore, a difference in forbidden bandwidth gradient is formed between the ninth confinement heterojunction layer 530 and the tenth confinement heterojunction layer 550, which can accelerate the movement of carriers in the heterojunction, thereby reducing the transit time of carriers in the heterojunction, improving the carrier injection efficiency, and increasing the photoelectric confinement effect to meet the requirement of high modulation rate of 25G or more.

In one embodiment, the laser chip preparation method further comprises:

depositing the ninth confinement heterojunction layer 530, the fifth active layer 540, the tenth confinement heterojunction layer 550, the tenth cladding layer 560, and the fifth ohmic contact layer 570 in sequence over the ninth cladding layer 520, resulting in a wafer.

In one embodiment, the step of growing a ninth confinement heterojunction layer 530 on the surface of the ninth cladding layer 520 away from the fifth substrate 510 comprises:

a plurality of ninth sub-confinement heterojunction layers 531 with a gradually decreasing forbidden band width are sequentially grown on the surface of the ninth cladding layer 520 away from the fifth substrate 510. Wherein a difference in a gradient of forbidden band widths of adjacent ninth sub-confinement heterojunction layers 531 is 20meV to 100 meV.

In this embodiment, the plurality of ninth sub-confinement heterojunction layers 531 have a gradually decreasing band gap along the direction from the ninth cladding layer 520 to the fifth active layer 540 (from bottom to top), and further form a plurality of graded layers having different band gaps. At this time, the ninth confinement heterojunction layer 530 forms a plurality of graded layers with gradually decreasing forbidden band widths, so that the movement of carriers in the heterojunction can be accelerated, the transit time of the carriers in the heterojunction is reduced, and the carrier injection efficiency is improved.

In one embodiment, the step of growing a tenth confinement heterojunction layer 550 on the surface of the fifth active layer 540 away from the ninth confinement heterojunction layer 530 includes:

a plurality of tenth confinement heterojunction layers 551 having a gradually increasing forbidden band width are sequentially grown on the surface of the fifth active layer 540 away from the ninth confinement heterojunction layer 530. Wherein a difference in a gradient of a forbidden band width of the adjacent tenth confinement heterojunction layer 551 is 20meV to 100 meV.

In this embodiment, the plurality of tenth confinement heterojunction layers 551 gradually increase in band gap along the direction from the fifth active layer 540 to the tenth cladding layer 560 (from bottom to top), and further form a plurality of graded layers having different band gaps. At this time, the tenth confinement heterojunction layer 550 forms a plurality of graded layers with gradually increasing forbidden band widths, so that the movement of carriers in the heterojunction can be accelerated, the transit time of the carriers in the heterojunction is reduced, and the carrier injection efficiency is improved.

At this time, a plurality of graded layers having a gradually decreasing bandgap and a plurality of graded layers having a gradually increasing bandgap are formed on both sides of the fifth active layer 540 from bottom to top in this order by the plurality of ninth sub-confinement heterojunction layers 531 and the plurality of tenth sub-confinement heterojunction layers 551 on both sides of the fifth active layer 540. At this time, the fifth active layer 540 is bound between the plurality of ninth confinement heterojunction layers 531 and the plurality of tenth confinement heterojunction layers 551 to form an energy level graded layer, so that carriers can move rapidly, the transit time of the carriers is reduced, and the carrier injection efficiency is improved.

In one embodiment, the laser chip preparation method further comprises:

a waveguide structure (not labeled) is formed on the fifth ohmic contact layer 570 of the wafer by using a photolithography technique. And then, forming an insulating layer on the upper surface of the waveguide structure by using plasma chemical vapor deposition, and then removing the insulating layer on the upper surface of the waveguide structure by using an etching method to expose the fifth ohmic contact layer 570. The ninth metal electrode layer 501 (i.e., a p-metal electrode layer) is then formed over the fifth ohmic contact layer 570 and the insulating layer. Subsequently, the back surface of the fifth substrate 510 is polished down to 100 μm, and the tenth metal electrode layer 502 (i.e., n-metal electrode layer) is plated. After the wafer is cut, one end face of the wafer is plated with the fifth anti-reflection coating layer 504, and the other end of the wafer is plated with the fifth high-reflection coating layer 503, so that the high-speed chip for communication is obtained.

In one embodiment, the present application provides the following specific 6 embodiments:

example 5-1: the ninth clad layer 520 is provided with a thickness Tn =0.2 μm and a doping concentration Dn =5e17cm^-3，Dn=1.5e18cm^-3，Dn=2e18cm^-3Three groups. A forbidden band width E of 25 ℃ of the barrier material in the fifth active layer 540_gb=1.18 eV. The thickness Tnsch =100nm of the ninth confinement heterojunction layer 530. The thickness Tpsch =200nm of the tenth confinement heterojunction layer 550. The doping concentration of the ninth confinement heterojunction layer 530, Dnsch =1.5e18cm^-3. The doping concentration of the tenth confinement heterojunction layer 550 dspsch =1e18cm^-3. A difference Δ E in gap width gradient between stacked materials of the plurality of ninth sub-confinement heterojunction layers 531 in the ninth confinement heterojunction layer 530_g1=100 meV. A difference Δ E in band gap width between stacked materials of the tenth confinement heterojunction layer 551 in the tenth confinement heterojunction layer 550_g2=100 meV. As shown in fig. 55, when the doping concentration values of the ninth cladding layer 520 are different, the three layers are differentThe 3dB bandwidth (shown in dashed horizontal lines in fig. 56) can meet the requirement of high speed adjustment bandwidth of 25GHZ and above. And has a doping concentration Dn =5e17cm^-3The electro-optic response intensity is maximum for a 3dB bandwidth.

Please refer to fig. 57, example 5-2: the ninth cladding layer 520 has three groups of thicknesses Tn =0.2 μm, Tn =0.4 μm, and Tn =2 μm, and has a doping concentration Dn =5e17cm^-3. A forbidden band width E of 25 ℃ of the barrier material in the fifth active layer 540_gb=1.18 eV. The thickness Tnsch =100nm of the ninth confinement heterojunction layer 530. The thickness Tpsch =200nm of the tenth confinement heterojunction layer 550. The doping concentration of the ninth confinement heterojunction layer 530, Dnsch =1.5e18cm^-3. The doping concentration of the tenth confinement heterojunction layer 550 dspsch =1e18cm^-3. A difference Δ E in gap width gradient between stacked materials of the plurality of ninth sub-confinement heterojunction layers 531 in the ninth confinement heterojunction layer 530_g1=100 meV. A difference Δ E in band gap width between stacked materials of the tenth confinement heterojunction layer 551 in the tenth confinement heterojunction layer 550_g2=100 meV. As shown in fig. 57, the difference between the three groups of Tn =0.2 μm, Tn =0.4 μm, and Tn =2 μm is small, and all of the three thicknesses can satisfy the requirement of the high-speed adjustment bandwidth of 25GHZ and above. And the electro-optic response intensity of the 3dB bandwidth (shown by the lateral dashed line in fig. 57) is maximum at Tn =0.4 μm.

See fig. 58, example 5-3: the ninth clad layer 520 is provided with a thickness Tn =0.4 μm and a doping concentration Dn =5e17cm^-3. A forbidden band width E of 25 ℃ of the barrier material in the fifth active layer 540_gb=1.18 eV. The thicknesses of the ninth confinement heterojunction layer 530 are set to be Tnsch =10nm, Tnsch =100nm, and Tnsch =200nm, respectively. The doping concentration of the ninth confinement heterojunction layer 530, Dnsch =1.5e18cm^-3. The tenth confinement heterojunction layer 550 has a thickness Tpsch =200nm and a doping concentration dspsch =1e18cm^-3. A difference Δ E in gap width gradient between stacked materials of the plurality of ninth sub-confinement heterojunction layers 531 in the ninth confinement heterojunction layer 530_g1=100 meV. A difference Δ E in band gap width between stacked materials of the tenth confinement heterojunction layer 551 in the tenth confinement heterojunction layer 550_g2=100meV。As shown in fig. 58, all three thicknesses can satisfy the requirement of high speed adjustment bandwidth of 25GHZ and above. And, when Tnsch =100nm, the electro-optic response intensity of the 3dB bandwidth is maximum.

Please refer to fig. 59, examples 5-4: the ninth clad layer 520 is provided with a thickness Tn =0.4 μm and a doping concentration Dn =5e17cm^-3. A forbidden band width E of 25 ℃ of the barrier material in the fifth active layer 540_gb=1.18 eV. The thickness of the ninth confinement heterojunction layer 530 is set to Tnsch =100 nm. The doping concentration of the ninth confinement heterojunction layer 530, Dnsch =1.5e18cm^-3. The thickness of the tenth confinement heterojunction layer 550 is set to Tpsch =10nm, Tpsch =50nm, Tpsch =200nm, and doping concentration dspsch =1e18cm, respectively^-3. A difference Δ E in gap width gradient between stacked materials of the plurality of ninth sub-confinement heterojunction layers 531 in the ninth confinement heterojunction layer 530_g1=100 meV. A difference Δ E in band gap width between stacked materials of the tenth confinement heterojunction layer 551 in the tenth confinement heterojunction layer 550_g2=100 meV. As shown in fig. 59, all three thicknesses of the tenth confinement heterojunction layer 550 can satisfy the requirement of high speed adjustment bandwidth of 25GHZ and above. Also, the electro-optic response intensity of 3dB is maximum at Tpsch =50 nm.

See fig. 60, examples 5-5: the ninth clad layer 520 is provided with a thickness Tn =0.4 μm and a doping concentration Dn =5e17cm^-3. A forbidden band width E of 25 ℃ of the barrier material in the fifth active layer 540_gb=1.18 eV. The thickness of the ninth confinement heterojunction layer 530 is set to Tnsch =100 nm. The doping concentration of the ninth confinement heterojunction layer 530, Dnsch =1.5e18cm^-3. The thickness of the tenth confinement heterojunction layer 550 is set to Tpsch =50nm, and the doping concentrations are respectively dspsch =5e17cm^-3，Dpsch=1e18cm^-3，Dpsch=2e18cm^-3. A difference Δ E in gap width gradient between stacked materials of the plurality of ninth sub-confinement heterojunction layers 531 in the ninth confinement heterojunction layer 530_g1=100 meV. A difference Δ E in band gap width between stacked materials of the tenth confinement heterojunction layer 551 in the tenth confinement heterojunction layer 550_g2=100 meV. As shown in fig. 60, the tenth confinement heterojunction layer 550 has three doping concentrationsCan meet the requirement of high-speed adjustment bandwidth of 25GHz and above. And at dspsch =1e18cm^-3The electro-optic response intensity is maximum for a 3dB bandwidth.

See fig. 61, examples 5-6: the ninth clad layer 520 is provided with a thickness Tn =0.4 μm and a doping concentration Dn =5e17cm^-3. A forbidden band width E of 25 ℃ of the barrier material in the fifth active layer 540_gb=1.18 eV. The thickness of the ninth confinement heterojunction layer 530 is set to Tnsch =100 nm. The doping concentration of the ninth confinement heterojunction layer 530, Dnsch =1.5e18cm^-3. The thickness of the tenth confinement heterojunction layer 550 is set to Tpsch =50nm, and the doping concentrations are respectively dspsch =1e18cm^-3. The difference in width gradient between the stacked materials of the plurality of ninth sub-confinement heterojunction layers 531 in the ninth confinement heterojunction layer 530 is Δ E_g1=20meV，ΔE_g1=50meV，ΔE_g1=100 meV. A difference Δ E in band gap width between stacked materials of the tenth confinement heterojunction layer 551 in the tenth confinement heterojunction layer 550_g2=20meV，ΔE_g2=50meV，ΔE_g2=100 meV. As shown in FIG. 61, Δ E in FIG. 61_gRepresents Delta E_g1And Δ E_g2Here, it is understood that Δ E_g1=ΔE_g2=ΔE_g. Difference Delta E of forbidden band width gradient among three laminated materials of 20meV, 50meV and 100meV_gCan meet the requirement of high-speed adjustment bandwidth of 25GHz and above. And the 3dB bandwidth reaches the optimum at 50 meV.

Thus, with the above embodiments, it can be seen that: by setting the doping concentrations and the gradient difference of the laminated forbidden band widths of the ninth confinement heterojunction layer 530 and the tenth confinement heterojunction layer 550, the laser chip 100 can meet the requirement of realizing a high-speed modulation rate of more than 25 GHZ.

In one embodiment, the present application provides an industrial-temperature high-power laser chip, including the laser chip 100 described in any of the above embodiments. The application provides a working temperature high-power laser chip which is prepared by adopting the preparation method of the laser chip in any embodiment. At the moment, the working temperature high-power laser chip can be a chip with a speed of more than 25G, the bandwidth is more than 18GHZ, and the requirement of the current 5G network is completely met. Moreover, the industrial temperature high-power laser chip can meet the requirement of a single channel of a data center for more than 50G on bandwidth, the domestic scheme batch production of the 5G network optical module can be realized, the import dependence of the high-speed optical chip is eliminated, the national new infrastructure is assisted, and the rapid deployment of the domestic 5G network is promoted.

In one embodiment, the laser chip 100 and the laser chip manufacturing method in the above embodiments can also be applied to other semiconductor device technologies.

In the description herein, references to the description of "some embodiments," "other embodiments," or the like, mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, a schematic description of the above terminology may not necessarily refer to the same embodiment or example.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features of the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the claims. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims

1. A semiconductor device, comprising:

the surface of the fourth substrate is provided with a seventh limiting layer, a fourth active layer and an eighth limiting layer;

a fourth electron confinement layer disposed on a surface of the eighth confinement layer away from the fourth active layer; or the fourth electron confinement layer is disposed between the eighth confinement layer and the fourth active layer;

2. The semiconductor device according to claim 1, wherein the fourth electron-confining layer comprises In_xAl_(1-x)An As layer, the fourth active layer comprising an InGaAsP layer, the eighth confinement layer comprising a P-type InGaAsP layer; wherein, the In_xAl_(1-x)X in the As layer is greater than 0 and less than 1.

3. The semiconductor device according to claim 2, wherein the In_xAl_(1-x)The value of x in the As layer ranges from 0.4 to 0.6.

4. The semiconductor device according to claim 2, wherein the fourth electron-binding layer comprises In doped with an iron element_xAl_(1-x)As layer or In doped with zinc element_xAl_(1-x)And an As layer.

5. The semiconductor device according to claim 4, wherein the In_xAl_(1-x)The doping concentration of iron element or zinc element in the As layer is 5e17cm^-3To 10e17cm^-3。

6. The semiconductor device according to claim 1, wherein a thickness of the fourth electron-binding layer is 20nm to 80 nm.

7. The semiconductor device according to claim 1, further comprising:

a seventh cladding layer disposed between the fourth substrate and the seventh confinement layer;

a plurality of fourth grating strips which are arranged on the surface of the fourth electron confinement layer away from the eighth confinement layer at intervals; or the plurality of fourth grating strips are arranged on the surface, away from the fourth electron confinement layer, of the eighth confinement layer at intervals;

the eighth cladding layer is disposed on the surfaces of the plurality of fourth grating strips and in gaps between the plurality of fourth grating strips, and the eighth cladding layer is provided with a ridge waveguide structure.

8. The semiconductor device according to claim 7, further comprising:

the fourth ohmic contact layer is arranged on the surface of the ridge waveguide structure far away from the fourth grating strips;

the seventh metal electrode layer is arranged on the surface, far away from the eighth cladding layer, of the fourth ohmic contact layer;

and the eighth metal electrode layer is arranged on the surface, far away from the seventh cladding layer, of the fourth substrate.

9. The semiconductor device according to claim 8, wherein the eighth metal electrode layer, the fourth substrate, the seventh clad layer, the seventh confinement layer, the fourth active layer, the eighth confinement layer, the fourth electron confinement layer, the plurality of fourth grating strips, the eighth clad layer, the fourth ohmic contact layer, and the seventh metal electrode layer form a base structure;

the semiconductor device further includes: the fourth high-reflection coating layer is arranged on the first end face of the matrix structure parallel to the long axis of the fourth grating strip;

and the fourth high-transmission coating layer is arranged on the second end surface of the matrix structure parallel to the long axis of the fourth grating strip, and the first end surface and the second end surface are oppositely arranged.

10. A method for manufacturing a semiconductor device is characterized by comprising the following steps:

11. The manufacturing method of a semiconductor device according to claim 10, wherein In is used_xAl_(1-x)Growing the fourth electron-confinement layer on the surface of the eighth confinement layer away from the fourth active layer by the As material;

12. The method for manufacturing a semiconductor device according to claim 10, wherein In doped with an iron element or a zinc element is used_xAl_(1-x)Growing the fourth electron-confinement layer on the surface of the eighth confinement layer away from the fourth active layer by the As material;

or In doped with iron or zinc_xAl_(1-x)The As material grows the fourth electron-confinement layer on the surface of the fourth active layer far away from the seventh confinement layer;

13. The method for manufacturing a semiconductor device according to claim 10, wherein a stress at the time of growing the fourth electron confinement layer is-0.2% Pa to 0.2% Pa.

14. A semiconductor device, comprising:

the forbidden band width of the fourth electron confinement layer is greater than that of the fourth active layer, and the forbidden band width of the fourth electron confinement layer is greater than that of the eighth confinement layer;

the fourth electron confinement layer comprises In doped with zinc element_0.5Al_0.5As layer, the doping concentration of zinc element is 7.5e17cm^-3And the thickness of the fourth electron confinement layer is 50nm, and the stress of the fourth electron confinement layer is 0.0% Pa.

15. A semiconductor device, comprising:

the fourthThe electron-binding layer comprises In doped with iron element_0.5Al_0.5As layer with doping concentration of iron element of 7.5e17cm^-3And the thickness of the fourth electron confinement layer is 50nm, and the stress of the fourth electron confinement layer is 0.0% Pa.