CN112230880A - Data transmission control method and device, FPGA (field programmable Gate array) and medium - Google Patents
Data transmission control method and device, FPGA (field programmable Gate array) and medium Download PDFInfo
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Abstract
The application discloses a data transmission control method, a data transmission control device, an FPGA and a medium, wherein the method comprises the following steps: sending the data frame to a second kernel of the receiving end FPGA; receiving an ACK response frame sent by the second kernel; and controlling the data traffic of a local data sending port according to a receiving credit use field, a frame response sequence number, the size of the receiving end cache residual space and locally-stored sending credit consumption data in the ACK response frame, wherein the sending credit consumption data represents the data volume sent by the first kernel to the second kernel. Therefore, the data transmission of the sending end can be automatically controlled according to the condition of the receiving end, the bandwidth can be fully utilized, and the data loss is avoided.
Description
Technical Field
The present application relates to the field of FPGA technologies, and in particular, to a data transmission control method, apparatus, FPGA, and medium.
Background
With the rapid development of technologies such as big data, internet of things, mobile internet, cloud computing and the like, a large amount of data needs to be processed and analyzed efficiently in real time, and the analysis, the processing and the like of the data occupy a large amount of server resources, so that the heterogeneous acceleration platform becomes a main selection direction, and related data computing can be unloaded to the heterogeneous acceleration platform for processing. With the rapid development of Field Programmable Gate Array (FPGA) devices, a new implementation way is provided for the application of heterogeneous acceleration platforms.
By utilizing the parallel and low-delay characteristics of the FPGA, a large amount of data needing to be calculated can be unloaded from the CPU to be calculated in the kernel of the FPGA, and the data needing to be calculated can be distributed to the kernel of each FPGA in a distributed network for calculation. In the data transmission process, if there is no flow control, the interconnected FPGA kernel may cause data loss or great memory consumption, and may also consume the entire processing bandwidth. Therefore, in the data transmission process of realizing multi-channel kernel interconnection, the flow control can ensure that the data flow can not cause serious congestion, and the reliable transmission mechanism can ensure the correctness of the data.
As shown in fig. 1, in the existing data flow control method, a static flow limit similar to a speed limiter is implemented at a sending end, after a data volume is sent out from the sending end, the data volume is first transmitted to the speed limiter for rate control, and after a data transmission rate is adjusted, the data volume is sent to a receiving end. For example, the rate of the sending end is 2MB/s, but after the current limitation of the speed limiter, the rate of the sending end to the Buffer (Buffer) can be reduced to 1MB/s, so that the data transmitted in the network and received at the receiving end are transmitted in 1MB/s, and the rate of the sending end is matched with the rate of the receiving end, so that the data can be stably transmitted.
The inventor finds that the prior art may have the following technical problem that the receiving end needs to manually modify the speed of the speed limiter according to the situation at any time because the receiving end cannot know the maximum speed, and the receiving end may dynamically fluctuate at any time, so that the receiving end cannot be timely adjusted, and the situation that the flow is suddenly large and small exists, so that the bandwidth cannot be fully utilized. If the sending rate of the sending end is too high, the data received by the receiving end is lost, and if the sending rate of the sending end is too low, the waste of bandwidth use is caused.
Disclosure of Invention
In view of this, an object of the present application is to provide a data transmission control method, apparatus, FPGA, and medium, which can automatically control data transmission of a transmitting end according to a condition of a receiving end, and can fully utilize a bandwidth without causing data loss. The specific scheme is as follows:
in a first aspect, the present application discloses a data transmission control method, which is applied to a first kernel of a transmitting end FPGA, and includes:
sending a data frame to a second kernel of a receiving end FPGA, wherein the data frame comprises a frame request sequence number, and the frame request sequence number represents the number of the data frames sent to the second kernel by the first kernel;
receiving an ACK response frame sent by the second kernel, wherein the ACK response frame comprises a receiving credit use field, a frame response sequence number and a receiving end cache residual space size, the receiving credit use field represents the data volume sent by the first kernel and received by the second kernel, and the frame response sequence number represents the data frame quantity sent by the first kernel and received by the second kernel;
and controlling the data traffic of a local data transmission port according to the receiving credit use field, the frame response sequence number, the size of the receiving end cache residual space and locally stored transmission credit consumption data, wherein the transmission credit consumption data represents the data volume which is transmitted to the second kernel by the first kernel.
Optionally, the sending the data frame to the second kernel of the receiving end FPGA includes:
adding 1 to a locally stored frame request serial number to obtain a current frame request serial number, and adding the current frame request serial number to a data frame to be sent;
accumulating the number of bytes of data in the data frame to be sent to the sending credit consumption data;
and sending the data frame to be sent to a second kernel of a receiving end FPGA, so that the second kernel compares a current frame request sequence number in the data frame with a locally-stored expected frame sequence number after receiving the data frame, adds 1 to a frame response sequence number in the second kernel when the current frame request sequence number is consistent with the locally-stored expected frame sequence number, and adds the number of received bytes to receive credit use data in the second kernel, wherein the expected frame sequence number represents a frame request sequence number which the second kernel expects to receive currently.
Optionally, the receiving the ACK response frame sent by the second kernel includes:
receiving an ACK response frame sent by the second kernel after the data corresponding to the data frame to be sent is cached in a receiving end;
and/or receiving an ACK response frame sent by the second kernel according to a preset time interval.
Optionally, the controlling the data traffic of the local data transmission port according to the reception credit usage field, the frame response sequence number, the size of the receiving-end cache remaining space, and the locally stored transmission credit consumption data includes:
comparing the received credit usage data in the received credit usage field with locally stored transmit credit consumption data;
and if the receiving credit use data in the receiving credit use field is smaller than the locally stored sending credit consumption data, controlling the data flow of a local data sending port according to the frame response sequence number and the size of the receiving end cache residual space.
Optionally, the controlling the data traffic of the local data sending port according to the frame response sequence number and the size of the receiving end cache residual space includes:
determining a target data frame which is sent by the first kernel and not received in the second kernel according to the frame response sequence number and the size of the receiving end cache residual space;
and retransmitting the target data frame to the second kernel.
Optionally, the determining, according to the frame response sequence number and the size of the receiving-end cache residual space, that the first kernel has sent and the second kernel does not receive the target data frame includes:
determining a first target data frame which is sent by the first kernel and not received in the second kernel according to the frame response sequence number;
judging whether the size of the residual space of the receiving end cache is smaller than or equal to a preset cache space size threshold value or not;
and if the size of the residual space of the receiving end cache is smaller than or equal to a preset cache space size threshold value, determining a second target data frame with the data volume equal to the size of the residual space of the receiving end cache from the first target data frame.
Optionally, the determining, according to the frame response sequence number, that the first target data frame has been sent by the first kernel and is not received in the second kernel includes:
reading a first pointer value from a preset RAM by taking the frame response serial number as an address, wherein the preset RAM stores the pointer values of data corresponding to each frame request serial number by taking the frame request serial number as the address;
comparing the first pointer value with a current second pointer value of a preset FIFO;
and if the first pointer value is inconsistent with the current second pointer value of a preset FIFO, taking data which is in the preset FIFO and corresponds to the first pointer value and the second pointer value as a first target data frame, wherein the preset FIFO is used for storing the data which is sent by the first kernel to the second kernel.
In a second aspect, the present application discloses a data transmission control device, which is applied to a first kernel of a transmitting end FPGA, and includes:
the data frame sending module is used for sending data frames to a second kernel of the receiving end FPGA, wherein the data frames comprise frame request sequence numbers which represent the number of the data frames sent to the second kernel by the first kernel;
an ACK response frame receiving module, configured to receive an ACK response frame sent by the second kernel, where the ACK response frame includes a reception credit usage field, a frame response sequence number, and a size of a receiving-end cache residual space, the reception credit usage field indicates a data amount sent by the first kernel and received by the second kernel, and the frame response sequence number is used to indicate a data frame amount sent by the first kernel and received by the second kernel;
and the flow control module is used for controlling the data flow of a local data sending port according to the receiving credit use field, the frame response sequence number, the size of the receiving end cache residual space and locally stored sending credit consumption data, wherein the sending credit consumption data represents the data volume sent by the first kernel to the second kernel.
In a third aspect, the present application discloses an FPGA, comprising:
a storage unit and a processing unit;
wherein the storage unit is used for storing a computer program;
the processing unit is configured to execute the computer program to implement the data transmission control method disclosed in the foregoing.
In a fourth aspect, the present application discloses a computer readable storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the data transmission control method disclosed in the foregoing.
It can be seen that in the present application, a data frame is sent to a second kernel of a receiving end FPGA, where the data frame includes a frame request sequence number, the frame request sequence number indicates a number of data frames that have been sent by the first kernel to the second kernel, and receives an ACK response frame sent by the second kernel, where the ACK response frame includes a reception credit usage field, a frame response sequence number, and a size of a receiving end cache residual space, the reception credit usage field indicates a data amount received by the second kernel and sent by the first kernel, the frame response sequence number indicates a number of data frames received by the second kernel and sent by the first kernel, and then the data flow of a local data sending port can be controlled according to the reception credit usage field, the frame response sequence number, the size of the receiving end cache residual space, and locally stored transmission credit consumption data, wherein the transmission credit consumption data represents an amount of data that the first kernel has transmitted to the second kernel. In view of this, after the first kernel of the sending-end FPGA sends the data frame to the second kernel of the receiving-end FPGA, the first kernel of the sending-end FPGA receives the ACK response frame returned by the second kernel of the receiving-end FPGA, so that the data amount and the data frame number sent by the second kernel that have been received by the second kernel can be obtained from the received ACK response frame, and then the data traffic of the data sending port corresponding to the first kernel is controlled by combining the data amount that has been sent to the second kernel and is recorded in the first kernel itself, so that the first kernel of the sending-end FPGA can control the data traffic of the first kernel by combining the data amount that has been sent to the second kernel of the receiving-end FPGA and the received data amount fed back by the second kernel, and whether the second kernel receives all the sent data amounts, so that the data transmission of the sending-end FPGA can be automatically controlled according to the condition of the receiving end, the bandwidth can be fully utilized, and data loss is avoided.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a flow chart of a conventional data transmission control;
FIG. 2 is a flow chart of a data transmission control method disclosed in the present application;
FIG. 3 is a schematic diagram of an FPGA connection disclosed herein;
FIG. 4 is a schematic diagram of an FPGA connection disclosed herein;
FIG. 5 is a flow chart of a specific data transmission control method disclosed herein;
FIG. 6 is a flow chart of a specific data transmission control method disclosed herein;
FIG. 7 is a schematic structural diagram of a data transmission control apparatus according to the present disclosure;
fig. 8 is a schematic structural diagram of an FPGA disclosed in the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
At present, a data flow control method between interconnected kernels is to implement a static current limit similar to a speed limiter at a sending end, transmit a data volume to the speed limiter for rate control after the data volume is sent out from the sending end, and then send the data volume to a receiving end after the data transmission rate is adjusted. For example, the rate of the sending end is 2MB/s, but after the current limitation of the speed limiter, the rate of the sending end to the Buffer (Buffer) can be reduced to 1MB/s, so that the data transmitted in the network and received at the receiving end are transmitted in 1MB/s, and the rate of the sending end is matched with the rate of the receiving end, so that the data can be stably transmitted. Because it is unknown what the receiving end can bear the maximum speed, the speed of the speed limiter needs to be manually modified at any time according to the situation, and the receiving end may fluctuate dynamically at any time, so that the speed limiter cannot be adjusted in time, the situation that the flow is suddenly large and small exists, and the bandwidth cannot be fully utilized. If the sending rate of the sending end is too high, the data received by the receiving end is lost, and if the sending rate of the sending end is too low, the waste of bandwidth use is caused. In view of this, the present application provides a data transmission control method, which can automatically control data transmission of a sending end according to a condition of a receiving end, and can fully utilize bandwidth without causing data loss.
Referring to fig. 2, an embodiment of the present application discloses a data transmission control method, which is applied to a first kernel of a transmitting end FPGA, and the method includes:
step S11: and sending a data frame to a second kernel of the FPGA at a receiving end, wherein the data frame comprises a frame request sequence number, and the frame request sequence number represents the number of the data frames sent to the second kernel by the first kernel.
Referring to fig. 3, the FPGAs may be directly interconnected. Referring to fig. 4, the FPGAs may also be interconnected through a switch.
In a specific implementation process, the first kernel sends a data frame to a second kernel of the receiving end FPGA, where header information of the data frame generally includes a frame type, a frame request sequence number, and ID (identity) information. The frame type represents whether a current frame is a data frame or an ACK response frame, the frame request sequence number represents the number of data frames which have been sent by the first kernel to the second kernel, and the ID information comprises the ID information of the FPGA at the sending end, the ID information of the first kernel, the ID information of the FPGA at the receiving end, and the ID information of the second kernel. The transmitting end FPGA can comprise a plurality of kernel, and the receiving end FPGA can also comprise a plurality of kernel.
Specifically, sending the data frame to the second kernel of the receiving end FPGA includes: adding 1 to a locally stored frame request serial number to obtain a current frame request serial number, and adding the current frame request serial number to a data frame to be sent; accumulating the number of bytes of data in the data frame to be sent to the sending credit consumption data; and sending the data frame to be sent to a second kernel of a receiving end FPGA, so that the second kernel compares a current frame request sequence number in the data frame with a locally-stored expected frame sequence number after receiving the data frame, adds 1 to a frame response sequence number in the second kernel when the current frame request sequence number is consistent with the locally-stored expected frame sequence number, and adds the number of received bytes to receive credit use data in the second kernel, wherein the expected frame sequence number represents a frame request sequence number which the second kernel expects to receive currently.
According to the configured ID information of the receiving end, a first kernel of the FPGA of the transmitting end starts to transmit a data frame to a second kernel of the corresponding FPGA of the receiving end, the first kernel can accumulate the frame request serial number when transmitting one data frame, adds the value into the frame request serial number field of the frame header information, and simultaneously accumulates the number of transmitted bytes, namely transmits credit consumption data.
And an expected frame sequence number (starting from 0) is arranged in the second kernel of the receiving end, the frame request sequence number of a frame is compared with the expected frame sequence number every time the frame of the frame is received, if the frame request sequence number is the same as the expected frame sequence number, the frame is received and buffered, and 1 is added to the frame response sequence number, and if the frame request sequence number is not the same as the expected frame sequence number, the frame is discarded, and the expected frame sequence number keeps an original value between the frames received. When a correct frame request sequence number is received, the receive credit usage data in the second kernel is accumulated with the number of bytes received in the frame.
Step S12: and receiving an ACK response frame sent by the second kernel, wherein the ACK response frame comprises a reception credit usage field, a frame response sequence number and a receiving end cache residual space size, the reception credit usage field represents the data volume sent by the first kernel and received by the second kernel, and the frame response sequence number represents the data frame number sent by the first kernel and received by the second kernel.
After the second kernel receives the data frame sent by the first kernel, if the frame request sequence number in the data frame received this time is different from the frame request sequence number in the data frame received before, an ACK response frame is sent to the first kernel, and/or the ACK response frame is sent to the first kernel according to a preset time interval. Therefore, the receiving the ACK response frame sent by the second kernel includes: receiving an ACK response frame sent by the second kernel after the data corresponding to the data frame to be sent is cached in a receiving end; and/or receiving an ACK response frame sent by the second kernel according to a preset time interval. The ACK response frame comprises a receiving credit use field, a frame response serial number and the size of a receiving end cache residual space, wherein the receiving credit use field represents the data volume sent by the first kernel received by the second kernel, the frame response serial number represents the number of data frames sent by the first kernel received by the second kernel, in addition, the ACK response frame also comprises ID information which comprises the ID information of the receiving end FPGA, the kernel information of the receiving end FPGA, the ID information of the sending end FPGA and the kernel information of the sending end FPGA, when the second kernel sends the ACK response frame to the first kernel, the kernel of the receiving end FPGA is the first kernel, and the kernel of the sending end FPGA is the second kernel.
Step S13: and controlling the data traffic of a local data transmission port according to the receiving credit use field, the frame response sequence number, the size of the receiving end cache residual space and locally stored transmission credit consumption data, wherein the transmission credit consumption data represents the data volume which is transmitted to the second kernel by the first kernel.
After receiving the ACK response frame, the first kernel may control data traffic of a local data transmission port according to the reception credit usage field, the frame response sequence number, the size of the receiving-end buffer remaining space, and locally stored transmission credit consumption data, where the transmission credit consumption data indicates the amount of data that the first kernel has transmitted to the second kernel.
That is, the first kernel may perform data flow control operations such as retransmission control according to the reception credit usage field, the frame response sequence number, the size of the receiving-end cache remaining space, and the locally stored transmission credit consumption data.
It can be seen that in the present application, a data frame is sent to a second kernel of a receiving end FPGA first, where the data frame includes a frame request sequence number, the frame request sequence number indicates a number of data frames that have been sent by the first kernel to the second kernel, and receives an ACK response frame sent by the second kernel, where the ACK response frame includes a reception credit usage field, a frame response sequence number, and a size of a receiving end cache residual space, the reception credit usage field indicates a data amount that is received by the second kernel and sent by the first kernel, the frame response sequence number is used to indicate a number of data frames that are received by the second kernel and sent by the first kernel, and then the data flow of a local data sending port can be controlled according to the reception credit usage field, the frame response sequence number, the size of the receiving end cache residual space, and locally stored transmission credit consumption data, wherein the transmission credit consumption data represents an amount of data that the first kernel has transmitted to the second kernel. In view of this, after the first kernel of the sending-end FPGA sends the data frame to the second kernel of the receiving-end FPGA, the first kernel of the sending-end FPGA receives the ACK response frame returned by the second kernel of the receiving-end FPGA, so that the data amount and the data frame number sent by the second kernel that have been received by the second kernel can be obtained from the received ACK response frame, and then the data traffic of the data sending port corresponding to the first kernel is controlled by combining the data amount that has been sent to the second kernel and is recorded in the first kernel itself, so that the first kernel of the sending-end FPGA can control the data traffic of the first kernel by combining the data amount that has been sent to the second kernel of the receiving-end FPGA and the received data amount fed back by the second kernel, and whether the second kernel receives all the sent data amounts, so that the data transmission of the sending-end FPGA can be automatically controlled according to the condition of the receiving end, the bandwidth can be fully utilized, and data loss is avoided.
Referring to fig. 5, an embodiment of the present application discloses a specific data transmission control method, which is applied to a first kernel of a transmitting end FPGA, and the method includes:
step S21: and sending a data frame to a second kernel of the FPGA at a receiving end, wherein the data frame comprises a frame request sequence number, and the frame request sequence number represents the number of the data frames sent to the second kernel by the first kernel.
Step S22: and receiving an ACK response frame sent by the second kernel, wherein the ACK response frame comprises a reception credit usage field, a frame response sequence number and a receiving end cache residual space size, the reception credit usage field represents the data volume sent by the first kernel and received by the second kernel, and the frame response sequence number represents the data frame number sent by the first kernel and received by the second kernel.
The specific implementation of step S21 and step S22 can refer to the disclosure in the foregoing embodiments, and will not be described herein again.
Step S23: comparing the received credit usage data in the received credit usage field with locally stored transmitted credit consumption data.
After the first kernel receives the ACK response frame, it is further required to control data traffic of a local data transmission port according to the reception credit usage field, the frame response sequence number, the size of the receiving-end cache residual space, and locally stored transmission credit consumption data.
Specifically, the reception credit usage data in the reception credit usage field is compared with the transmission credit consumption data stored locally, so that it can be determined whether the second kernel receives all data transmitted by the first kernel.
Step S24: and if the receiving credit use data in the receiving credit use field is smaller than the locally stored sending credit consumption data, controlling the data flow of a local data sending port according to the frame response sequence number and the size of the receiving end cache residual space.
If the reception credit usage data in the reception credit usage field is smaller than the transmission credit consumption data stored locally, it indicates that the second kernel does not receive all the data transmitted by the first kernel, so the data traffic of the local data transmission port needs to be controlled according to the frame response sequence number and the size of the receiving-end cache residual space.
Specifically, it is required to determine, according to the frame response sequence number and the size of the receiving-end cache residual space, that the first kernel has sent a target data frame that is not received in the second kernel; and retransmitting the target data frame to the second kernel.
Specifically, the determining, according to the frame response sequence number and the size of the receiving-end cache residual space, that the first kernel has sent and the second kernel does not receive the target data frame includes: determining a first target data frame which is sent by the first kernel and not received in the second kernel according to the frame response sequence number; judging whether the size of the residual space of the receiving end cache is smaller than or equal to a preset cache space size threshold value or not; and if the size of the residual space of the receiving end cache is smaller than or equal to a preset cache space size threshold value, determining a second target data frame with the data volume equal to the size of the residual space of the receiving end cache from the first target data frame.
That is, it is determined according to the frame response sequence number that the second kernel receives the data frames sent by the first kernel, and then it can be determined by combining the frame request sequence number in the first kernel which data frames are sent by the first kernel but not received by the second kernel, and these data frames are used as the first target data frame. In the actual process, it is necessary to consider that the size of the remaining space of the receiving-end cache in the second kernel may not be able to store all the first target data frames, so it is also necessary to determine whether the size of the remaining space of the receiving-end cache is smaller than or equal to a preset cache space size threshold, when the size of the remaining space of the receiving-end cache is smaller than or equal to the preset cache space size threshold, it is indicated that the size of the remaining space of the receiving-end cache in the second kernel is not able to store all the first target data frames, so it is necessary to determine a second target data frame whose data amount is equal to the size of the remaining space of the receiving-end cache from the first target data frame, and retransmit the second target data frame to the second kernel, and when the size of the remaining space of the receiving-end cache is greater than the preset cache space size threshold, it is indicated that the size of the remaining space of the receiving-end cache in the second kernel is able to store all the first target, so that the first target data frame is directly retransmitted to the second kernel.
In practical applications, the determining, according to the frame response sequence number, that the first target data frame has been sent by the first kernel and has not been received in the second kernel includes: reading a first pointer value from a preset RAM by taking the frame response serial number as an address, wherein the preset RAM stores the pointer values of data corresponding to each frame request serial number by taking the frame request serial number as the address; comparing the first pointer value with a current second pointer value of a preset FIFO; and if the first pointer value is inconsistent with the current second pointer value of a preset FIFO, taking data which is in the preset FIFO and corresponds to the first pointer value and the second pointer value as a first target data frame, wherein the preset FIFO is used for storing the data which is sent by the first kernel to the second kernel.
That is, a First Input First Output (FIFO) and a Random Access Memory (RAM) are required to be preset, where the FIFO stores data that has been sent to the second kernel, and the RAM stores pointer values corresponding to each data frame using the frame request sequence number as an address. For example, if the data with the frame request sequence number of 1 is stored in the positions 1 to 100 in the preset FIFO, the pointer value corresponding to the frame request sequence number of 1 is 100, and 1 is used as the address, and 100 is stored in the memory space with the address of 1 in the preset RAM. And storing the data with the frame request sequence number of 2 in the positions from 101 to 200 in the preset FIFO, wherein the pointer value corresponding to the frame request sequence number of 2 is 200, and the address of 2 is used as the address, and 200 is stored in the storage space with the address of 2 in the preset RAM. Therefore, a first pointer value is read from a preset RAM according to the response frame sequence number, then the first pointer value is compared with a current second pointer value of a preset FIFO, if the first pointer value is inconsistent with the current second pointer value of the preset FIFO, it is indicated that the second kernel does not completely receive data sent by the first kernel, and the part of data, starting from the data corresponding to the first pointer value to the data corresponding to the second pointer value, in the preset FIFO is required to be used as a first target data frame. And if the first pointer value is consistent with the current second pointer value of the preset FIFO, the second key receives all data sent by the first key.
And after the first target data frame or the second target data frame is sent to the second kernel, sending a new data frame to the second kernel until the data in the credit use field of the receiving end in the ACK response frame sent by the second kernel is equal to the credit consumption sending data stored in the first kernel, wherein the new data frame is the data which is not sent to the second kernel by the first kernel.
Each kernel of each FPGA has a set of data transmission control mechanism, so that the data transmission control mechanisms are not interfered with each other, and the transmission bandwidth can be fully utilized. Performing flow control by using the link state represented by the transmission credit consumption in the kernel of the transmitting end and the receiving credit of the ACK response frame of the receiving end; the frame request sequence number in the data frame is compared with the frame response sequence number of the ACK response frame, so that the correctness of data transmission is ensured. Therefore, effective flow control and reliable transmission of each kernel are realized, and the algorithm processing efficiency of the FPGA heterogeneous acceleration platform is improved.
Fig. 6 is a schematic diagram of a data transmission control flow. After the kernel of the sending end sends the data frame to the kernel of the receiving end, the kernel of the receiving end determines whether to update the receiving credit usage (credit usage in the figure) in the kernel of the receiving end, the receiving end cache residual space (Rx cache space in the figure) and the frame response sequence number according to the frame request sequence number and the like in the data frame, so that the sending end sends an ACK response frame to the kernel of the sending end according to the result, and the kernel of the sending end determines whether to perform data flow control such as data frame retransmission and the like according to the data in the ACK response frame.
Referring to fig. 7, an embodiment of the present application discloses a data transmission control apparatus, which is applied to a first kernel of a transmitting end FPGA, and includes:
the data frame sending module 11 is configured to send a data frame to a second kernel of the receiving end FPGA, where the data frame includes a frame request sequence number, and the frame request sequence number indicates the number of data frames that the first kernel has sent to the second kernel;
an ACK response frame receiving module 12, configured to receive an ACK response frame sent by the second kernel, where the ACK response frame includes a reception credit usage field, a frame response sequence number, and a size of a receiving-end cache residual space, the reception credit usage field indicates a data amount sent by the first kernel and received by the second kernel, and the frame response sequence number indicates a number of data frames sent by the first kernel and received by the second kernel;
and a flow control module 13, configured to control data flow of a local data transmission port according to the reception credit usage field, the frame response sequence number, the size of the receiving-end cache remaining space, and locally stored transmission credit consumption data, where the transmission credit consumption data indicates a data amount that the first kernel has transmitted to the second kernel.
It can be seen that in the present application, a data frame is sent to a second kernel of a receiving end FPGA, where the data frame includes a frame request sequence number, the frame request sequence number indicates a number of data frames that have been sent by the first kernel to the second kernel, and receives an ACK response frame sent by the second kernel, where the ACK response frame includes a reception credit usage field, a frame response sequence number, and a size of a receiving end cache residual space, the reception credit usage field indicates a data amount received by the second kernel and sent by the first kernel, the frame response sequence number indicates a number of data frames received by the second kernel and sent by the first kernel, and then the data flow of a local data sending port can be controlled according to the reception credit usage field, the frame response sequence number, the size of the receiving end cache residual space, and locally stored transmission credit consumption data, wherein the transmission credit consumption data represents an amount of data that the first kernel has transmitted to the second kernel. In view of this, after the first kernel of the sending-end FPGA sends the data frame to the second kernel of the receiving-end FPGA, the first kernel of the sending-end FPGA receives the ACK response frame returned by the second kernel of the receiving-end FPGA, so that the data amount and the data frame number sent by the second kernel that have been received by the second kernel can be obtained from the received ACK response frame, and then the data traffic of the data sending port corresponding to the first kernel is controlled by combining the data amount that has been sent to the second kernel and is recorded in the first kernel itself, so that the first kernel of the sending-end FPGA can control the data traffic of the first kernel by combining the data amount that has been sent to the second kernel of the receiving-end FPGA and the received data amount fed back by the second kernel, and whether the second kernel receives all the sent data amounts, so that the data transmission of the sending-end FPGA can be automatically controlled according to the condition of the receiving end, the bandwidth can be fully utilized, and data loss is avoided.
Specifically, the data frame sending module 11 is configured to:
adding 1 to a locally stored frame request serial number to obtain a current frame request serial number, and adding the current frame request serial number to a data frame to be sent;
accumulating the number of bytes of data in the data frame to be sent to the sending credit consumption data;
and sending the data frame to be sent to a second kernel of a receiving end FPGA, so that the second kernel compares a current frame request sequence number in the data frame with a locally-stored expected frame sequence number after receiving the data frame, adds 1 to a frame response sequence number in the second kernel when the current frame request sequence number is consistent with the locally-stored expected frame sequence number, and adds the number of received bytes to receive credit use data in the second kernel, wherein the expected frame sequence number represents a frame request sequence number which the second kernel expects to receive currently.
Further, the ACK response frame receiving module 12 is configured to:
receiving an ACK response frame sent by the second kernel after the data corresponding to the data frame to be sent is cached in a receiving end;
and/or receiving an ACK response frame sent by the second kernel according to a preset time interval.
Specifically, the flow control module 13 is configured to:
comparing the received credit usage data in the received credit usage field with locally stored transmit credit consumption data;
and if the receiving credit use data in the receiving credit use field is smaller than the locally stored sending credit consumption data, controlling the data flow of a local data sending port according to the frame response sequence number and the size of the receiving end cache residual space.
Specifically, the flow control module 13 is configured to:
determining a target data frame which is sent by the first kernel and not received in the second kernel according to the frame response sequence number and the size of the receiving end cache residual space;
and retransmitting the target data frame to the second kernel.
Specifically, the flow control module 13 is configured to:
determining a first target data frame which is sent by the first kernel and not received in the second kernel according to the frame response sequence number;
judging whether the size of the residual space of the receiving end cache is smaller than or equal to a preset cache space size threshold value or not;
and if the size of the residual space of the receiving end cache is smaller than or equal to a preset cache space size threshold value, determining a second target data frame with the data volume equal to the size of the residual space of the receiving end cache from the first target data frame.
Specifically, the flow control module 13 is configured to:
reading a first pointer value from a preset RAM by taking the frame response serial number as an address, wherein the preset RAM stores the pointer values of data corresponding to each frame request serial number by taking the frame request serial number as the address;
comparing the first pointer value with a current second pointer value of a preset FIFO;
and if the first pointer value is inconsistent with the current second pointer value of a preset FIFO, taking data which is in the preset FIFO and corresponds to the first pointer value and the second pointer value as a first target data frame, wherein the preset FIFO is used for storing the data which is sent by the first kernel to the second kernel.
Further, as shown in fig. 8, an embodiment of the present application further discloses an FPGA, which includes: a processing unit 21 and a storage unit 22.
Wherein, the storage unit 22 is used for storing computer programs; the processing unit 21 is configured to execute the computer program to implement the data transmission control method disclosed in the foregoing embodiment.
For the specific process of the data transmission control method, reference may be made to corresponding contents disclosed in the foregoing embodiments, and details are not repeated here.
Further, an embodiment of the present application also discloses a computer-readable storage medium for storing a computer program, wherein the computer program is executed by a processor to implement the data transmission control method disclosed in any of the foregoing embodiments.
For the specific process of the data transmission control method, reference may be made to corresponding contents disclosed in the foregoing embodiments, and details are not repeated here.
The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
Finally, it is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of other elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The data transmission control method, the data transmission control device, the FPGA and the media provided by the present application are introduced in detail, and a specific example is applied in the present application to explain the principle and the implementation of the present application, and the description of the above embodiment is only used to help understanding the method and the core idea of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (10)
1. A data transmission control method is characterized in that the method is applied to a first kernel of a transmitting end FPGA and comprises the following steps:
sending a data frame to a second kernel of a receiving end FPGA, wherein the data frame comprises a frame request sequence number, and the frame request sequence number represents the number of the data frames sent to the second kernel by the first kernel;
receiving an ACK response frame sent by the second kernel, wherein the ACK response frame comprises a receiving credit use field, a frame response sequence number and a receiving end cache residual space size, the receiving credit use field represents the data volume sent by the first kernel and received by the second kernel, and the frame response sequence number represents the data frame quantity sent by the first kernel and received by the second kernel;
and controlling the data traffic of a local data transmission port according to the receiving credit use field, the frame response sequence number, the size of the receiving end cache residual space and locally stored transmission credit consumption data, wherein the transmission credit consumption data represents the data volume which is transmitted to the second kernel by the first kernel.
2. The data transmission control method according to claim 1, wherein the sending of the data frame to the second kernel of the receiving end FPGA comprises:
adding 1 to a locally stored frame request serial number to obtain a current frame request serial number, and adding the current frame request serial number to a data frame to be sent;
accumulating the number of bytes of data in the data frame to be sent to the sending credit consumption data;
and sending the data frame to be sent to a second kernel of a receiving end FPGA, so that the second kernel compares a current frame request sequence number in the data frame with a locally-stored expected frame sequence number after receiving the data frame, adds 1 to a frame response sequence number in the second kernel when the current frame request sequence number is consistent with the locally-stored expected frame sequence number, and adds the number of received bytes to receive credit use data in the second kernel, wherein the expected frame sequence number represents a frame request sequence number which the second kernel expects to receive currently.
3. The data transmission control method according to claim 2, wherein the receiving the ACK response frame sent by the second kernel includes:
receiving an ACK response frame sent by the second kernel after the data corresponding to the data frame to be sent is cached in a receiving end;
and/or receiving an ACK response frame sent by the second kernel according to a preset time interval.
4. The data transmission control method according to any one of claims 1 to 3, wherein the controlling of the data traffic of the local data transmission port according to the reception credit usage field, the frame response sequence number, the size of the receiving-end buffer remaining space, and the transmission credit consumption data stored locally comprises:
comparing the received credit usage data in the received credit usage field with locally stored transmit credit consumption data;
and if the receiving credit use data in the receiving credit use field is smaller than the locally stored sending credit consumption data, controlling the data flow of a local data sending port according to the frame response sequence number and the size of the receiving end cache residual space.
5. The data transmission control method according to claim 4, wherein the controlling the data traffic of the local data transmission port according to the frame response sequence number and the size of the space left in the receiver buffer includes:
determining a target data frame which is sent by the first kernel and not received in the second kernel according to the frame response sequence number and the size of the receiving end cache residual space;
and retransmitting the target data frame to the second kernel.
6. The data transmission control method according to claim 5, wherein the determining, according to the frame response sequence number and the size of the remaining buffer space of the receiver, that the first kernel has sent the target data frame that is not received in the second kernel includes:
determining a first target data frame which is sent by the first kernel and not received in the second kernel according to the frame response sequence number;
judging whether the size of the residual space of the receiving end cache is smaller than or equal to a preset cache space size threshold value or not;
and if the size of the residual space of the receiving end cache is smaller than or equal to a preset cache space size threshold value, determining a second target data frame with the data volume equal to the size of the residual space of the receiving end cache from the first target data frame.
7. The data transmission control method of claim 6, wherein the determining, according to the frame response sequence number, that the first target data frame has been sent and is not received in the second kernel comprises:
reading a first pointer value from a preset RAM by taking the frame response serial number as an address, wherein the preset RAM stores the pointer values of data corresponding to each frame request serial number by taking the frame request serial number as the address;
comparing the first pointer value with a current second pointer value of a preset FIFO;
and if the first pointer value is inconsistent with the current second pointer value of a preset FIFO, taking data which is in the preset FIFO and corresponds to the first pointer value and the second pointer value as a first target data frame, wherein the preset FIFO is used for storing the data which is sent by the first kernel to the second kernel.
8. The data transmission control device is characterized by being applied to a first kernel of a transmitting end FPGA and comprising the following steps:
the data frame sending module is used for sending data frames to a second kernel of the receiving end FPGA, wherein the data frames comprise frame request sequence numbers which represent the number of the data frames sent to the second kernel by the first kernel;
an ACK response frame receiving module, configured to receive an ACK response frame sent by the second kernel, where the ACK response frame includes a reception credit usage field, a frame response sequence number, and a size of a receiving-end cache residual space, the reception credit usage field indicates a data amount sent by the first kernel and received by the second kernel, and the frame response sequence number indicates a number of data frames sent by the first kernel and received by the second kernel;
and the flow control module is used for controlling the data flow of a local data sending port according to the receiving credit use field, the frame response sequence number, the size of the receiving end cache residual space and locally stored sending credit consumption data, wherein the sending credit consumption data represents the data volume sent by the first kernel to the second kernel.
9. An FPGA, comprising:
a storage unit and a processing unit;
wherein the storage unit is used for storing a computer program;
the processing unit is configured to execute the computer program to implement the data transmission control method according to any one of claims 1 to 7.
10. A computer-readable storage medium for storing a computer program, wherein the computer program when executed by a processor implements the data transmission control method according to any one of claims 1 to 7.
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