CN112230489A

CN112230489A - Binary phase shift keying coded sub-wavelength general linear logic gate and implementation method thereof

Info

Publication number: CN112230489A
Application number: CN202011170291.0A
Authority: CN
Inventors: 刘厚权; 权志强; 苑立波
Original assignee: Guilin University of Electronic Technology
Current assignee: Guilin University of Electronic Technology
Priority date: 2020-10-28
Filing date: 2020-10-28
Publication date: 2021-01-15

Abstract

The invention provides a sub-wavelength general linear logic gate of binary phase shift keying coding and an implementation method thereof. The method is characterized in that: the sub-wavelength universal linear logic gate with binary phase shift keying coding comprises a substrate 1, a nano metal film 2, a rectangular nano groove 3, input signal light 4-1 and input signal light 4-2, and an excited surface plasma wave (SPP)_S)5 and an output port 6. The specific implementation method is that two beams of circularly polarized light with different circular polarization states are vertically input from the lower part of the substrate 1 to be used as input signal light, and the '1' and '0' of an input logic state are defined by regulating and controlling the phase shift of the input signal. Input circular polarization signal light excites SPPs in the rectangular nanometer groove 3, and the SPPs are transmitted on the surface of the nanometer metal film. And selecting a specific area in the transmission direction of the specific SPPs as an output port, and defining different output logic states through different SPPs strength values at the output port. The universal linear logic gate can realize seven basic logic gates on a single structure by adjusting the relative phase difference of input signals.

Description

Binary phase shift keying coded sub-wavelength general linear logic gate and implementation method thereof

(I) technical field

The invention relates to the fields of all-optical computation and all-optical information processing, in particular to a method for manufacturing a high-integration all-optical logic device.

(II) background of the invention

In the big data era, the requirement of large-capacity data transmission can be met only by realizing ultrahigh-speed network data exchange and information processing. However, the conventional electrical information processing apparatus has reached a speed bottleneck due to the limitation of electrical response time, and all-optical information processing is an effective method for solving this bottleneck problem, and is considered as a strong candidate for next-generation information processing technology. An all-optical logic gate is a key component for realizing all-optical information processing, and is a leading-edge hotspot widely researched in recent years [ Journal of optics 47.3(2018):365-

All-optical logic gates can be divided into two broad categories, those based on nonlinear effects and those based on linear coherence effects. However, the optical logic gate based on the nonlinear effect needs to use very high optical power to excite the nonlinear response of the conventional nonlinear material, which is a great obstacle in practical application. While all-optical logic gates based on linear coherence effects may not be power limited. In a linear coherent all-optical logic gate, the reduction of the size of the device can obviously reduce the transmission delay of light in the device and reduce the power consumption, thereby improving the overall performance of logic operation. Therefore, researchers have conducted many studies on the integration of all-optical logic devices, such as constructing small-sized, high-stability all-optical logic gates by confining an optical field to a sub-wavelength range using a plasmonic structure. However, most implementations of linear coherent logic gates based on SPPs rely on path mode coherence. The logic gates are realized by etching two SPPs transmission waveguides separated from each other on a photonic chip, and defining two SPPs transmitted in the two waveguides as two input signals. Although the lateral dimensions of SPPs waveguides can reach sub-wavelength dimensions, the longitudinal dimension typically requires lengths of several microns, thus limiting the size of the logic structure to the micron scale. Further miniaturization of logic devices to the nanometer scale remains a challenge. In addition to using different path modes, the two input signals of the all-optical logic gate may also be two mutually orthogonal modes in other dimensions, such as different orbital angular momentum modes [ Nanomaterials 9.12(2019):1649, Quantum information processing 18.8(2019):256 ] or different polarization modes [ nanoscales 10.9(2018): 4523-. By using these degrees of freedom to construct an all-optical logic gate, some superior performance over path-mode coherent all-optical logic gates can be obtained. The article [ Nanoscale 10.9(2018): 4523-. However, since paper authors use polarization shift keying to encode the input logic states "1" AND "0", they need to implement the OR AND gates by L-shaped nano-slot antennas, NOT, NAND AND NOR gates by inverted L-shaped nano-slot antennas, AND XNOR gates by rectangular nano-slot antennas. Therefore, their all-optical logic devices are not universal. In addition, in the OR, AND, NOR AND NAND gates reported in the paper, when the input logic states are different, the output intensities of the same output logic state are not consistent, which is very disadvantageous for the cascade design of multiple logic gates in practical application. Therefore, the development of a novel logic device which is ultra-compact and can overcome various defects of the logic gate in the paper (Nanoscale 10.9(2018): 4523-4527) by utilizing the degree of freedom of polarization of the optical field has very important practical application significance.

Against this background, the present invention discloses a sub-wavelength general linear logic gate for binary phase shift keying coding. The invention is essentially different from the logic gates in the papers (Nanoscale 10.9(2018): 4523-. The all-optical logic gate disclosed by the invention has the characteristics of ultra-compactness and high integration as a logic gate in a paper (Nanoscale 10.9(2018): 4523-: 1. the logic gate disclosed by the invention is a universal logic gate, AND 7 common logic gates including AND, OR, NOT, NAND, NOR, XOR AND XNOR logic gates can be realized by using the same logic structure; 2. in any logic gate, when the input logic states are different, the output intensities of the same output logic state are completely consistent, and the logic gate is suitable for the cascade design of a plurality of logic gates in practical application. The invention provides a highly integrated general linear coherent all-optical logic device which has important significance and value in future all-optical calculation and all-optical information processing.

Disclosure of the invention

The invention aims to provide a sub-wavelength universal linear logic gate of binary phase shift keying coding and an implementation method thereof.

The purpose of the invention is realized as follows:

the binary phase shift keying coded sub-wavelength general linear logic gate and the implementation method thereof. The method is characterized in that: the binary phase shift keying coded sub-wavelength universal linear logic gate comprises a substrate 1, a nano metal film 2, a rectangular nano groove 3, input signal lights 4-1 and 4-2, excited SPPs 5 and an output port 6, and a schematic diagram of the binary phase shift keying coded sub-wavelength universal linear logic gate is shown in FIG. 1. The specific implementation method comprises the following steps: two beams of circularly polarized light with different circular polarization states, namely left-handed circularly polarized light and right-handed circularly polarized light, are vertically input from the lower part of a substrate to be used as input signal light, and the '1' and '0' of an input logic state are defined by regulating and controlling the phase shift of an input signal, namely the input logic state is coded by phase shift keying; inputting circular polarization signal light to excite SPPs in the rectangular nanometer groove 3, and transmitting the SPPs on the surface of the nanometer metal film; and selecting a specific area in the transmission direction of the specific SPPs as an output port, and defining different output logic states through different SPPs strength values at the output port.

The substrate material may be silicon or silicon dioxide.

The two circularly polarized signal lights with different circular polarization states are coherent and have equal amplitudes, and in addition, the two signal lights are spatially overlapped with each other, and in the schematic diagram shown in fig. 1, the signal lights 4-1 and 4-2 are spatially separated from each other only for convenience of illustration.

The nano metal film 2 can be gold or silver. After the incident signal light passes through the substrate 1, SPPs are excited at the nanometer groove 3 on the nanometer metal film 2, and the SPPs are transmitted on the upper surface of the nanometer metal film 2 and form spatial distribution.

The output port can be preferably a point or a nanoscale region which is just below the center position of the nanometer groove (in the negative y-axis direction) and is away from the center point of the nanometer groove by a quantity level of tens to hundreds of nanometers. A nanometer probe can be placed at an output port to measure the strength of the output SPPs, so that an output logic state is directly obtained; the input port of the photonic device on the next stage can also be set at the output port, so that the output SPPs of the logic gate is used as the input signal of the photonic device on the next stage.

It is well known that rectangular nano-grooves have very excellent polarization response characteristics. When the polarization direction of the input light is perpendicular to the long side of the rectangular nano-groove 3, namely y polarization, the strongest excitation of the SPPs can be realized, and when the polarization direction of the input light is parallel to the long side of the rectangular nano-groove 3, namely x polarization, almost no SPPs is excited. This can be illustrated by the distribution of the mode values of SPPs excited when the input optical field is in different linear polarization states on the upper surface of the nanometal film 2 shown in fig. 2, where 2(a) is the distribution of the mode values of SPPs when the input light is in x-polarization, and 2(b) is the distribution of the mode values of SPPs when the input light is in y-polarization. As can be seen from the figure, when the input optical field is x-polarized, the maximum SPPs electric field intensity on the upper surface of the nano metal film 2 is only 1.1V/m; when the input light is y-polarized, the maximum SPPs electric field intensity on the upper surface of the nano metal film 2 can reach 16V/m, which is obviously larger than 1.1V/m. The following materials and structural parameters were selected for the above calculations: the substrate material is silicon dioxide, the thickness of the substrate is 100nm, the nano metal film is a gold film, the thickness of the gold film is 50nm, the wavelength of signal light is 960nm, the amplitude of input light is 1V/m, the length, width and depth of the nano groove are respectively L-200 nm, w-50 nm and h-50 nm. The above material and structure parameters are only used for calculation to illustrate that the rectangular nano-groove has good polarization response characteristics, and the invention is not limited by the above material and structure parameters.

When the phase delay of one input signal light beam is modulated by binary phase shift keying, the linear polarization direction of the superposed light field of the two signal light beams is changed. As described above, the rectangular nano-groove has excellent polarization response characteristics, and the intensity of SPPs excited on the upper surface of the nano-metal film 2 changes accordingly, so that the modulation of SPPs excited by one input signal light on another input signal light, that is, the control of light on light is realized, which is the fundamental reason why the all-optical logic gate can be realized by the present invention.

Quantitatively describing the polarization response characteristic of the rectangular nanometer slot antenna, the coupling coefficients of coupling the y-polarized light field and the x-polarized light field to SPPs at the output port can be respectively eta_yAnd η_xDue to the excellent polarization response characteristics of the rectangular nano-slot antenna, | η is known easily_x|＜＜|η_yL. The coupling coefficients of the right-handed circularly polarized light and the left-handed circularly polarized light to the SPPs at the output port are then respectively

And

therefore, the response matrix of the two input signal light-excited SPPs in our logic gate can be expressed as:

wherein E₁And E₂Respectively representing the complex amplitudes of the right-handed circularly polarized input signal light 4-1 and the left-handed circularly polarized input signal light 4-2; e_SPP1And E_SPP2Each represents E₁And E₂The electric field amplitude of the SPPs excited at the output port. Total output SPPs electric field is E_SPP＝E_SPP1+E_SPP2The total output intensity is I_SPP＝|E_SPP1+E_SPP2|²。

Consider that the electric field amplitudes of the two input signals are equal and are E₀I.e. | E₁|＝|E₂|＝E₀The initial phase factors of signals 4-1 and 4-2 are alpha and beta, respectively, and define σ γ as the relative phase shift between the input logic states "1" and "0" in binary phase shift keying coding, where σ is the number of spin quanta of the input signal and γ is a constant angle. Thus, the total output SPPs electric field is:

where a and B are binary variables representing the logic states of the input signal lights 4-1 and 4-2, the values of a and B may be 1 or 0, representing the input logic state "1" or "0", respectively. The logic gates are denoted collectively below by (A, B)The input logic state of (1). Thus, for different input logic states (0,0), (1,0), (0,1) and (1,1), the output SPPs have intensities F | α (η |)_x-iη_y)+β(η_x+iη_y)|²,F|α(η_x-iη_y)e^-iγ+β(η_x+iη_y)|²,F|α(η_x-iη_y)+β(η_x+iη_y)e^iγ|²And F | α (η)_x-iη_y)e^-iγ+β(η_x+iη_y)e^iγ|²Wherein

For an ideal logic gate, the output SPPs strength corresponding to the output logic state "0" needs to be zero. In the invention, the SPPs excited by the superposed optical field with the x polarization is weakest, but the field of the SPPs is still not zero, so that the invention cannot realize an ideal all-optical logic gate. Thus, the present invention defines that a smaller value of the SPPs intensity at the output port represents an output logic state "0", and a larger value of the SPPs intensity at the output port represents an output logic state "1". By setting the values of α, β, γ, different logic gates can be realized. When α ═ 1, β ═ 1, and γ ═ 2 π/3, an OR gate is implemented; when alpha is 1, beta is e^-πi/3When gamma is 2 pi/3, an AND logic gate is realized; when alpha is 1, beta is e^-2πi/3When gamma is 2 pi/3, a not logic gate is realized; when alpha is 1, beta is e^-4πi/3When gamma is 2 pi/3, the NAND logic gate is realized; when α ═ 1, β ═ 1, γ ═ 2 π/3; implementing a NOR logic gate; when alpha is 1, beta is-e^-2πi/3When gamma is 2 pi/3, an exclusive or logic gate is realized; when alpha is 1, beta is e^-2πi/3And when gamma is 2 pi/3, an exclusive-nor logic gate is realized. In each logic gate implemented by the above scheme, when the input logic states are different, the output SPPs intensities of the same output logic state are consistent.

Compared with the prior art, the invention has the outstanding advantages that:

(1) the size of the rectangular nanometer slot antenna is only hundred nanometers, and the distance between the position of the output port and the nanometer slot antenna is only dozens of to hundred nanometers, so that the total size of the device is hundred nanometers, and the integration is convenient. (2) Compared with the logic gate reported in the paper [ Nanoscale 10.9(2018): 4523-; in addition, in each logic gate realized by the invention, when the input logic states are different, the output intensity of the same output logic state is consistent, which is very beneficial to the cascade design of a plurality of logic gates in practical application.

(IV) description of the drawings

FIG. 1 is a schematic diagram of a sub-wavelength general linear logic gate with binary phase shift keying coding and a realization method thereof.

FIG. 2 is a diagram of simulation results obtained by a sub-wavelength general linear logic gate of binary phase shift keying coding and an implementation method thereof. (a) And (b) respectively represent the spatial distribution result of the amplitude mode values of the SPPs on the upper surface of the nano metal film 2 when the polarization direction of the incident light is parallel to the x axis and the y axis, and the dotted line represents the position of the rectangular nano groove.

FIG. 3 is a graph of the dependence of the OR logic gate output logic states "1" and "0" on the output intensity and their contrast with the wavelength calculated by the finite element method.

FIG. 4 is a graph of the dependence of the output intensities and their contrasts on the wavelength, calculated by the finite element method, corresponding to the logic states "1" and "0" of the logic gate output.

(V) detailed description of the preferred embodiments

The present invention will be specifically described below by taking an or gate and an and gate as examples.

Example 1: or a logic gate.

As shown in fig. 1, the or logic gate of the present embodiment includes a substrate 1, a nanometal film 2, a rectangular nano-groove 3, input signal lights 4-1 and 4-2, excited SPPs 5, and an output port 6. Input signal light is vertically incident from the lower surface of the substrate 1, SPPs are excited in the rectangular nanometer groove 3 and are transmitted on the surface of the nanometer metal film, and different SPPs strength values at an output port define different output logic states. A smaller value of the SPPs intensity at the output port represents an output logic state "0", and a larger value of the SPPs intensity at the output port represents an output logic state "1".

In an or logic gate, when the input logic state is (0,0), the output logic state is "0"; when the input logic states are (1,0), (0,1) and (1,1), the output logic state is "1". To improve the contrast between the SPPs intensities corresponding to the output logic states "0" and "1", the output intensity corresponding to the output logic state "0" should be as small as possible, and the output intensity corresponding to the output logic state "1" should be as large as possible. Since the excited SPPs are weakest when the polarization state of the optical field is linear polarization in the x direction, we take the intensity of the output SPPs of the superimposed optical fields of signal light 4-1 and 4-2 as the logic state "0". It is easy to know that the polarization state of the input signal light superimposed light field corresponding to the input logic state (0,0) is linear polarization in the x direction when α ═ β, and therefore α ═ β is an optimum condition for obtaining the output "0" state, and at this time, the weakest SPPs output intensity 4F | α η can be obtained_x|². For the output logic state "1", the output SPPs strength is required to be as large as possible, since |. eta._x|＜＜|η_yAt this time, SPPs excited by the y-polarization component in the superimposed optical field of the two signal lights will dominate in the output SPPs. Thus, η in the output SPPs is ignored_xThe output intensities corresponding to the input logic states (1,0), (0,1) and (1,1) can be approximately expressed as F | η |_y|²|-αe^-iγ+β|²,F|η_y|²|-α+βe^iγ|²And F | η_y|²|-αe^-iγ+βe^iγ|². Therefore, in order to ensure that the output intensities corresponding to the logic state "1" are consistent when the input logic states are different, we can obtain the conditional equation | - α e^-iγ+β|＝|-α+βe^iγ|＝|-αe^-iγ+βe^iγAnd | ≠ 0. By synthesizing the conditions of the output logic states "0" and "1", we finally obtain the total conditional equation of the OR logic gate as | - α e^-iγ+β|＝|-α+βe^iγ|＝|-αe^-iγ+βe^iγ| ≠ 0 and α ═ β. One particular set of solutions for the above conditional equations is: α ═ 1, β ═ 1, and γ ═ 2 π/3. The output intensity corresponding to the output logic state "0" is 4F | α η_x|²And the output intensity corresponding to the output logic state "1" is approximately-3F | η_y|²Where the symbols "" denote about equal.

Under the conditions of specific solutions of alpha being 1, beta being 1 and gamma being 2 pi/3, the dependence of the output SPPs intensity with the wavelength of different input logic states (0,0), (1,0), (0,1) and (1,1) is calculated by numerical simulation by using a finite element method, namely an intensity value 4F | alpha eta_x|²,F|α(η_x-iη_y)e^-iγ+β(η_x+iη_y)|²,F|α(η_x-iη_y)+β(η_x+iη_y)e^iγ|²And F | α (η)_x-iη_y)e^-iγ+β(η_x+iη_y)e^iγ|²Dependence on wavelength, and contrast between output intensities corresponding to output logic states "1" and "0". The following condition variables are preferred in the calculation: the substrate material is silicon dioxide, the thickness of the substrate is 100nm, the nano metal film is a gold film, the thickness of the gold film is 50nm, the length, width and depth of the nano groove are respectively L-200 nm, w-50 nm and h-50 nm, and the output port is taken at a position 50nm right below the center of the nano groove (namely in the negative y-axis direction). The calculated normalization results are shown in fig. 3. The SPPs intensity values for the input logic state (0,0), i.e., the output logic state "0", are multiplied by 10⁴The latter result. In addition, the calculation results show that the intensity values of the three SPPs corresponding to the input logic states (1,0), (0,1) and (1,1) are approximately equal, and the three curves coincide (it is indicated that the three output intensities corresponding to the output logic state "1" are indeed consistent when the input logic states are different, and they are approximately equal to-3F | η |, as per the above_y|²Discussion of (d) and is therefore uniformly represented by only one curve in the figure. The result shows that the contrast between the output intensities corresponding to the output logic states "1" and "0" is greater than 20dB in the ultra-wideband range of 700-.

In summary, the special solutions for implementing an or logic gate are α ═ 1, β ═ 1, and γ ═ 2 pi/3; the input logic state (0,0), i.e., the output logic state "0", corresponds to an output intensity of 4F | α η_x|²The output intensities corresponding to the output logic state "1" under different input logic states (1,0), (0,1) and (1,1) can be approximately equal, about &3F|η_y|²(ii) a Under the obtained calculation parameters, the contrast between the output intensities corresponding to the output logic states "1" and "0" is greater than 20dB in the ultra-wideband range of 700-1200 nm.

Example 2: and logic gates.

As shown in fig. 1, the and logic gate of the present embodiment includes a substrate 1, a nanometal film 2, a rectangular nano-groove 3, input signal lights 4-1 and 4-2, excited SPPs 5, and an output port 6. Input signal light is vertically incident from the lower surface of the substrate 1, SPPs are excited in the rectangular nanometer groove 3 and are transmitted on the surface of the nanometer metal film, and different SPPs strength values at an output port define different output logic states. A smaller value of the SPPs intensity at the output port represents an output logic state "0", and a larger value of the SPPs intensity at the output port represents an output logic state "1".

In an and logic gate, when the input logic states are (0,0), (1,0) and (0,1), the output logic state is "0"; when the input logic state is (1,1), the output logic state is "1". Since it is impossible for the three input logic states (0,0), (1,0) and (0,1) to simultaneously make the superimposed light field of the input signal light x-polarized, in order to ensure that the input logic states do not simultaneously output the three output intensities corresponding to logic state "0" consistently, the three superimposed light fields corresponding to the three input logic states (0,0), (1,0) and (0,1) must be appropriate superpositions of the x and y polarization states. In this case, the output SPPs is dominated by SPPs excited by the y-polarization component. Following a discussion entirely similar to or logic gates, one may arrive at a special solution to implement and logic gates as: α is 1, β is e^-πi/3And gamma is 2 pi/3. It can also be obtained that the output intensity of SPPs corresponding to the output logic state '0' is approximately equal to-F | eta_y|²And the output strength of SPPs corresponding to the output logic state "1" is approximately 4F | eta_y|². In addition, under the above-mentioned special solution conditions, the output intensities corresponding to the logic states "1" and "0" of the logic gate output and the dependency of their contrasts on the wavelength change were calculated using a finite element method, the calculation parameters were the same as those of the or logic gate in example 1, and the calculation results are shown in fig. 4. As can be seen from the figure, in the ultra-wideband range of 700-1200nm, the logic state is outputThe contrast between the output intensities corresponding to "1" and "0" is about 4: 1.

In summary, the special solutions of and logic gates are realized as α ═ 1 and β ═ e^-πi/3γ is 2 π/3; the output intensities of SPPs corresponding to an output logic state "0" in different input logic states are approximately equal, approximately ∼ F | η_y|²And the output strength of SPPs corresponding to the output logic state "1" is approximately 4F | eta_y|²(ii) a Under the obtained calculation parameters, the contrast ratio between the output intensities corresponding to the output logic states "1" and "0" is about 4:1 in the ultra-wideband range of 700-.

Similar analysis can be applied to the remaining five logic gates. Finally, the values of α, β, and γ for the seven logic gates can be summarized, and the information of the output SPPs intensities corresponding to different input logic states and the intensity contrast between the output logic states "1" and "0" in the seven logic gates is shown in the following table. The SPPs intensity contrast between the output logic states "1" and "0" in the table is the result obtained under the same calculation parameters as in examples 1 and 2, and corresponds to a wavelength range of 700-.

While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. The invention provides a sub-wavelength general linear logic gate of binary phase shift keying coding and a realization method thereof, which is characterized in that: the sub-wavelength universal linear logic gate of binary phase shift keying coding comprises a substrate 1, a nano metal film 2, a rectangular nano groove 3, input signal light 4-1 and 4-2, an excited surface plasma wave (SPPS)5 and an output port 6, and the specific implementation method is as follows: two beams of circularly polarized light with different circular polarization states are vertically input from the lower part of a substrate to be used as input signal light, and the '1' and '0' of an input logic state are defined by regulating and controlling the phase shift of the input signal, namely the input logic state is coded by binary phase shift keying; inputting circular polarization signal light to excite SPPs in the rectangular nanometer groove 3, and transmitting the SPPs on the surface of the nanometer metal film; and selecting a specific area in the transmission direction of the specific SPPs as an output port, and defining different output logic states through different SPPs strength values at the output port.

2. The sub-wavelength general linear logic gate of binary phase shift keying coding and the realization method thereof according to claim 1, characterized in that: the two beams of circularly polarized signal light with different circular polarization states are coherent, overlapped in space and equal in amplitude.

3. The sub-wavelength general linear logic gate of binary phase shift keying coding and the realization method thereof according to claim 1, characterized in that: the nano metal film on the substrate can be a gold film or a silver film.

4. The sub-wavelength general linear logic gate of binary phase shift keying coding and the realization method thereof according to claim 1, characterized in that: the substrate material may be silicon or silicon dioxide.