CN112217625A - SC-FDE timing coarse synchronization implementation method and device based on FPGA - Google Patents

SC-FDE timing coarse synchronization implementation method and device based on FPGA Download PDF

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CN112217625A
CN112217625A CN202011295097.5A CN202011295097A CN112217625A CN 112217625 A CN112217625 A CN 112217625A CN 202011295097 A CN202011295097 A CN 202011295097A CN 112217625 A CN112217625 A CN 112217625A
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纪苏远
张明利
李阿明
施菊
周戌初
马景馨
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Shanghai Radio Equipment Research Institute
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/042—Detectors therefor, e.g. correlators, state machines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes
    • H04L27/2601—Multicarrier modulation systems
    • H04L27/2647—Arrangements specific to the receiver only
    • H04L27/2655—Synchronisation arrangements
    • H04L27/2656—Frame synchronisation, e.g. packet synchronisation, time division duplex [TDD] switching point detection or subframe synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes
    • H04L27/2601—Multicarrier modulation systems
    • H04L27/2647—Arrangements specific to the receiver only
    • H04L27/2655—Synchronisation arrangements
    • H04L27/2662—Symbol synchronisation
    • H04L27/2663—Coarse synchronisation, e.g. by correlation

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Abstract

The invention discloses a method and a device for realizing timing coarse synchronization of SC-FDE based on FPGA, wherein the method comprises the steps that S1, a data cache module respectively sends input data which are not delayed and input data which are delayed to a related window energy calculation module and a delay related energy calculation module; s2, the delay correlation energy calculation module processes the input data which are not delayed and the input data which are delayed to obtain the correlation coefficient of the simplified input data which are not delayed and the simplified input data which are delayed; s3, the energy value of the received data in the length of the delay window is calculated by a related window energy calculating module; s4, the frame search module counts the number of points of the measurement function continuously larger than the threshold value, and finds out the initial position of the data frame.

Description

SC-FDE timing coarse synchronization implementation method and device based on FPGA
Technical Field
The invention belongs to the field of aerospace measurement and control and digital communication, and particularly relates to a method and a device for realizing SC-FDE (single carrier-frequency domain equalization) timing coarse synchronization based on an FPGA (field programmable gate array).
Background
Single carrier frequency domain equalization (SC-FDE) is a better anti-multipath fading technology, and compared with Orthogonal Frequency Division Multiplexing (OFDM), it has the advantages of low peak-to-average power ratio, insensitivity to carrier phase offset, etc., and in recent years, it has gained wide attention and application in wireless communication systems. In the SC-FDE system, the accuracy of timing synchronization is always the key content of research, and directly influences the performance of the SC-FDE system.
Document 1 (ney-wei, jin-hong, severe cold, MIMO-OFDM system time synchronization algorithm research and implementation [ J ]. communication technology, 2016, (03)) utilizes correlation of repeated training sequences before and after as a measurement function, the algorithm is relatively simple, and the calculation amount of the algorithm can be significantly reduced by adopting sliding window accumulation calculation. However, due to the strong correlation between adjacent metrology function values, a flat effect of the metrology function may result, and the synchronization accuracy may be low. To overcome the platform effect, document 2 (study and implementation of the time synchronization algorithm of wannpeng, zhangsen, luxiaka MIMO-OFDM system [ J ]. computer and network, 2012, (12)) proposes a training sequence structure of mirror symmetry type, which has a symmetric structure from middle to both sides, so that the correlation of the synchronization metric function becomes very low, the timing accuracy is high, but the calculation amount of the algorithm cannot be reduced by adopting sliding window accumulation calculation, so the calculation amount is much higher than that of document 1. Document 3 (chen, zhao national bui, cheng zheng, timing synchronization research of single carrier frequency domain equalization technology [ J ]. university of zhejiang (engineering edition), 2007, (03)) utilizes correlation of repeated cyclic prefixes as a measurement function, although timing accuracy is high, the algorithm is relatively complex and not favorable for hardware implementation. Patent 1 (timing synchronization method based on MIMO # OFDM system, CN201611222722.7, 2017) proposes a timing synchronization method based on MIMO-OFDM system, which defines timing metrics of fine synchronization and coarse synchronization by using short training sequences, and determines arrival of each path of packet data by using results of the fine synchronization and the coarse synchronization, but cannot adopt simplified methods such as sliding window accumulation and amplitude simplification. Patent 2 (burst OFDM timing synchronization method based on conjugate training sequence, CN201810654969.9, 2018) proposes a timing synchronization method of OFDM system, which realizes correct detection of the start position of a frame in case of sending multi-frame data. Timing accuracy is high, but a simplified method cannot be used to save hardware overhead. Patent 3 (low-complexity high-performance OFDM timing synchronization algorithm, CN201110299793.8, 2011) proposes a low-complexity high-performance OFDM timing synchronization algorithm, where the OFDM timing synchronization algorithm is to construct a timing metric function with higher stability, and the timing performance is superior to the conventional algorithm, but the algorithm complexity is higher than the conventional algorithm, which is not favorable for hardware implementation.
Disclosure of Invention
The invention aims to provide a method and a device for realizing SC-FDE (single carrier-frequency domain equalization) timing coarse synchronization based on an FPGA (field programmable gate array), aiming at reducing hardware overhead and operation complexity by adopting technologies such as sliding window accumulation, amplitude simplification and the like in the implementation process of the FPGA and effectively realizing a timing synchronization function under the conditions of reducing the operation complexity and reducing the hardware overhead.
In order to achieve the purpose, the invention is realized by the following technical scheme:
an implementation method of SC-FDE timing coarse synchronization based on FPGA is characterized by comprising the following steps:
s1, the data buffer module respectively sends the input data which is not delayed and the input data which is delayed to the correlation window energy calculation module and the delay correlation energy calculation module;
s2, the delay correlation energy calculation module processes the input data which are not delayed and the input data which are delayed to obtain the correlation coefficient of the simplified input data which are not delayed and the simplified input data which are delayed;
s3, the energy value of the received data in the length of the delay window is calculated by a related window energy calculating module;
s4, the frame search module counts the number of points of the measurement function continuously larger than the threshold value, and finds out the initial position of the data frame.
The step S2 includes:
s2.1, a delay correlation calculation unit calculates the correlation coefficient of the input data which is not delayed and the input data after delay, and synchronously outputs the two groups of data;
s2.2, accumulating the current correlation coefficient and the delayed correlation coefficient by a correlation accumulation calculating unit;
s2.3, the amplitude simplifying and calculating unit solves the amplitude after the correlation value accumulation to obtain a delay correlation value | Cn|。
The step S3 includes:
s3.1, the energy value calculation unit performs conjugate multiplication on the received data and the received data to obtain an energy value of the received data within the length of the delay window;
s3.2, the energy value accumulation calculating unit accumulates the energy values of the received data to obtain a window energy value PnAnd the window energy value P is calculatednSent to the frame search module.
The step S4 specifically includes:
by comparing metric functions mnAnd a threshold value ThIf the metric function m is reached, judging whether the data frame arrivesnGreater than a threshold value ThThen judging that the data frame arrives:
Figure BDA0002785152200000031
an SC-FDE timing coarse synchronization implementation device based on FPGA comprises: the device comprises a data caching module, a correlation window energy calculating module and a delay correlation energy calculating module;
the data cache module respectively sends input data which is not delayed and input data which is delayed to the related window energy calculation module and the delay related energy calculation module;
the delay correlation energy calculation module processes the input data which are not delayed and the input data which are delayed to obtain the correlation coefficient of the simplified input data which are not delayed and the simplified input data which are delayed;
the related window energy calculation module calculates the energy value of the received data in the length of the delay window;
the frame search module counts the number of points of which the measurement function is continuously larger than a threshold value, and finds out the initial position of the data frame.
The delay correlation energy calculation module comprises:
the delay correlation calculation unit is used for calculating the correlation coefficient of the input data which is not delayed and the input data after delay and synchronously outputting the two groups of data;
the correlation accumulation calculating unit accumulates the current correlation coefficient and the delayed correlation coefficient;
the amplitude simplifying and calculating unit is used for solving the amplitude after the correlation value accumulation to obtain a delay correlation value | Cn|。
The correlation window energy calculation module comprises:
the energy value calculating unit is used for carrying out conjugate multiplication on the received data and the received data to obtain an energy value of the received data within the length of the delay window;
an energy value accumulation calculating unit for accumulating the energy values of the received data to obtain a window energy value PnAnd the window energy value P is calculatednSent to the frame search module.
Compared with the prior art, the invention has the following advantages:
in the FPGA implementation process, the hardware overhead and the operation complexity are reduced by adopting the technologies of sliding window accumulation, amplitude simplification and the like. The simulation result verifies the usability of the algorithm in the actual hardware environment, and the timing synchronization function can be effectively realized under the conditions of reducing the operation complexity and reducing the hardware overhead.
Drawings
FIG. 1 is a block diagram of an SC-FDE system;
FIG. 2 is a diagram showing a structure of a leader sequence of SC-FDE;
FIG. 3 is a structural diagram of an implementation apparatus for SC-FDE timing coarse synchronization based on FPGA according to the present invention;
FIG. 4 is a diagram of a coarse synchronization algorithm simulation of the present invention;
fig. 5 is a simulation diagram of the probability of correct detection of the coarse synchronization algorithm.
Detailed Description
The present invention will now be further described by way of the following detailed description of a preferred embodiment thereof, taken in conjunction with the accompanying drawings.
As shown in fig. 1, binary input data is first convolution-encoded, then QAM mapped, and data stream segments are inserted into a preamble training sequence (UW), and finally digital-to-analog converted after shaping and filtering. The receiving end performs digital down-conversion on the received data passing through the channel, performs time-frequency synchronization and channel estimation by using a special frame structure through analog-to-digital conversion, converts the received data without the prefix into a frequency domain by taking a block as a unit through FFT, performs frequency domain equalization by using Channel State Information (CSI) obtained by channel estimation, recovers the frequency domain to a time domain through IFFT, and finally obtains the transmitted data through QAM demapping and Viterbi decoding.
As shown in fig. 2, the preamble sequence of SC-FDE includes two parts, a short preamble and a long preamble. The short preamble consists of 8 repeated short training symbols a, each having 32 sampling points. The whole short preamble has 256 sampling points, and can complete the functions of Automatic Gain Control (AGC), coarse synchronization, coarse frequency offset estimation and the like. The long preamble consists of 4 repetitions of a long training symbol C, each having 64 sampling points. The whole long preamble has 256 sampling points, and can be used for fine synchronization, fine frequency offset estimation, channel estimation and the like. Both the short and long preambles are composed of CAZAC sequences.
An SC-FDE timing coarse synchronization implementation method based on FPGA comprises the following steps:
s1, the data buffer module respectively sends the input data which is not delayed and the input data which is delayed to the correlation window energy calculation module and the delay correlation energy calculation module;
s2, the delay correlation energy calculation module processes the input data which are not delayed and the input data which are delayed to obtain the correlation coefficient of the simplified input data which are not delayed and the simplified input data which are delayed;
s3, the energy value of the received data in the length of the delay window is calculated by a related window energy calculating module;
s4, the frame search module counts the number of points of the measurement function continuously larger than the threshold value, and finds out the initial position of the data frame.
The data buffer module is implemented by a shift register, and since the buffer module needs to output valid data as well as input data for the next-stage module, the buffer module can be implemented by two shift registers with respective lengths of 32 and 96.
The first stage shift register mainly outputs the current input data which is not delayed and the input data which is delayed to a subsequent module. The energy calculation modules in the subsequent modules require input data that is not currently delayed, while the delay-dependent energy calculation modules require input data that is not currently delayed and input data that is delayed by 32 bits. The synchronous output of the current data and the delayed data can be easily realized by using the register.
The second stage of shift register is mainly used for buffering the short training sequence in order to output the complete data frame. The rough synchronization algorithm uses the cross-correlation value of adjacent short training sequences as a metric function, and the number of points whose metric function is greater than a threshold value needs to be kept at a certain length, and the present embodiment is set to keep the length of 50 points. Assuming that no delay through the shift register is passed, when the frame search module detects that the number of consecutive points whose metric function is greater than the threshold is equal to 50, two short training sequences have been shifted out of the first segment of the shift register, which affects the performance of the subsequent module. We set the length of the second segment of the shift register to 96, which prevents the short midamble from shifting out.
The step S2 includes:
s2.1, a delay correlation calculation unit calculates the correlation coefficient of the input data which is not delayed and the input data after delay, and synchronously outputs the two groups of data;
s2.2, accumulating the current correlation coefficient and the delayed correlation coefficient by a correlation accumulation calculating unit;
step S2.3, the amplitude simplified computing unit solves the accumulated correlation valuesObtaining the time delay correlation value | C by the amplituden|。
Specifically, the following formula is used:
Figure BDA0002785152200000061
in the formula, CnDenotes the correlation coefficient, rnN is the serial number of the data sampling point for the received baseband digital sequence,
Figure BDA0002785152200000065
is rnL is the sliding window length. Let Cn＝an+jbnThen, then
Figure BDA0002785152200000066
Figure BDA0002785152200000067
The step S3 includes:
s3.1, the energy value calculation unit performs conjugate multiplication on the received data and the received data to obtain an energy value of the received data within the length of the delay window;
s3.2, the energy value accumulation calculating unit accumulates the energy values of the received data to obtain a window energy value PnAnd the window energy value P is calculatednTo a frame search module, wherein
Figure BDA0002785152200000062
In the formula, rnN is the serial number of the data sampling point for the received baseband digital sequence,
Figure BDA0002785152200000068
is rnL is the sliding window length.
Calculating a metric function mnThen the metric function m of the time delay correlation algorithmnComprises the following steps:
Figure BDA0002785152200000063
wherein, | CnI represents the magnitude of the correlation coefficient, PnIs the window energy value. If the decision variable m is implemented directly in hardwarenA divider is needed and to avoid the use of a divider, a simplified algorithm shown in the following formula can be used. Threshold value ThSet to 0.5, a right shift of one bit may be used to achieve a multiplication of 0.5 by PnThus, the hardware circuit is simplified.
|Cn|>Pn×Th＝0.5Pn＝(Pn>>1)
The step S4 specifically includes:
by comparing metric functions mnAnd a threshold value ThIf the metric function m is reached, judging whether the data frame arrivesnGreater than a threshold value ThThen judging that the data frame arrives:
Figure BDA0002785152200000064
wherein T ish＝50。
As shown in fig. 3, an SC-FDE timing coarse synchronization implementation apparatus based on FPGA includes: the device comprises a data caching module, a correlation window energy calculating module and a delay correlation energy calculating module;
the data cache module respectively sends input data which is not delayed and input data which is delayed to the related window energy calculation module and the delay related energy calculation module;
the delay correlation energy calculation module processes the input data which are not delayed and the input data which are delayed to obtain the correlation coefficient of the simplified input data which are not delayed and the simplified input data which are delayed;
the related window energy calculation module calculates the energy value of the received data in the length of the delay window;
the frame search module counts the number of points of which the measurement function is continuously larger than a threshold value, and finds out the initial position of the data frame.
The delay correlation energy calculation module comprises:
the delay correlation calculation unit is used for calculating the correlation coefficient of the input data which is not delayed and the input data after delay and synchronously outputting the two groups of data;
and the correlation accumulation calculating unit accumulates the current correlation coefficient and the delayed correlation coefficient, when the delayed correlation value arrives, firstly, the correlation value is sent to a 32-bit shift register with the length, then, currently input correlation data and the delayed 32-bit correlation data are synchronously output through the shift register, and finally, the two data are sent to an accumulation window. The calculation formula of the accumulation window is
Figure BDA0002785152200000071
In the above formula, sum is the sum of sums,
Figure BDA0002785152200000072
as a result of the current correlation coefficient,
Figure BDA0002785152200000073
is the correlation coefficient after 32 stages of delay through the shift register.
The amplitude simplifying and calculating unit is used for solving the amplitude after the correlation value accumulation to obtain a delay correlation value | CnTaking absolute values of the real part and the imaginary part of the correlation value, and then adding the absolute values of the real part and the imaginary part of the correlation value.
The correlation window energy calculation module comprises:
the energy value calculating unit is used for carrying out conjugate multiplication on the received data and the received data to obtain an energy value of the received data within the length of the delay window;
an energy value accumulation calculating unit for accumulating the energy values of the received data to obtain a window energy value PnAnd the window energy value P is calculatednSent to frame searchA cable module.
Specifically, similar to the correlation calculation in the delay correlation value calculation module, the energy value calculation module performs conjugate multiplication on the received data and the energy value, so as to obtain the energy value of the received data within the length of the delay window. Similar to the correlation value accumulation in the delay correlation value calculation module, the energy value accumulation module mainly completes the accumulation of the energy value. The energy of the correlation window does not need to be calculated in amplitude, so that the output data needs to be subjected to delay processing in order to be synchronously output to the frame search module with the delay correlation value calculation module. After the energy value accumulation operation is finished, the result is firstly sent to a cache module for caching, and then the delayed data is sent to a frame search module.
As shown in fig. 4, to avoid the occurrence of false determination, it can be determined that a data frame arrives only when the number of points exceeding the set threshold is counted and kept at a certain length, that is, the number of points of the metric function above the preset threshold is continuously kept at a certain length, and at this time, even if the random noise is large, the accuracy of the coarse synchronization is not affected. Firstly, the set simulation conditions are as follows: the length of the short training sequence is 32 points, the AWGN channel, and the signal-to-noise ratio is 5 dB.
As shown in fig. 5, the accuracy of the time coarse synchronization is 0.9 when the signal-to-noise ratio is 10dB, and the accuracy of the time coarse synchronization is 1 when the signal-to-noise ratio is 20dB, so that the FPGA implementation method of the SC-FDE timing coarse synchronization algorithm provided herein can effectively implement the timing synchronization function under the conditions of reducing the operation complexity and reducing the hardware overhead.
While the present invention has been described in detail with reference to the preferred embodiments, it should be understood that the above description should not be taken as limiting the invention. Various modifications and alterations to this invention will become apparent to those skilled in the art upon reading the foregoing description. Accordingly, the scope of the invention should be determined from the following claims.

Claims (7)

1. An SC-FDE timing coarse synchronization implementation method based on FPGA is characterized by comprising the following steps:
s1, the data buffer module respectively sends the input data which is not delayed and the input data which is delayed to the correlation window energy calculation module and the delay correlation energy calculation module;
s2, the delay correlation energy calculation module processes the input data which are not delayed and the input data which are delayed to obtain the correlation coefficient of the simplified input data which are not delayed and the simplified input data which are delayed;
s3, the energy value of the received data in the length of the delay window is calculated by a related window energy calculating module;
s4, the frame search module counts the number of points of the measurement function continuously larger than the threshold value, and finds out the initial position of the data frame.
2. The method for implementing the coarse timing synchronization of the SC-FDE based on the FPGA of claim 1, wherein the step S2 comprises:
s2.1, a delay correlation calculation unit calculates the correlation coefficient of the input data which is not delayed and the input data after delay, and synchronously outputs the two groups of data;
s2.2, accumulating the current correlation coefficient and the delayed correlation coefficient by a correlation accumulation calculating unit;
s2.3, the amplitude simplifying and calculating unit solves the amplitude after the correlation value accumulation to obtain a delay correlation value | Cn|。
3. The method for implementing the coarse timing synchronization of the SC-FDE based on the FPGA of claim 2, wherein the step S3 comprises:
s3.1, the energy value calculation unit performs conjugate multiplication on the received data and the received data to obtain an energy value of the received data within the length of the delay window;
s3.2, the energy value accumulation calculating unit accumulates the energy values of the received data to obtain a window energy value PnAnd the window energy value P is calculatednSent to the frame search module.
4. The method for implementing the timing coarse synchronization of the SC-FDE based on the FPGA of claim 3, wherein the step S4 specifically includes:
by comparing metric functions mnAnd a threshold value ThIf the metric function m is reached, judging whether the data frame arrivesnGreater than a threshold value ThThen judging that the data frame arrives:
Figure FDA0002785152190000021
5. an SC-FDE timing coarse synchronization realizing device based on FPGA is characterized by comprising: the device comprises a data caching module, a correlation window energy calculating module and a delay correlation energy calculating module;
the data cache module respectively sends input data which is not delayed and input data which is delayed to the related window energy calculation module and the delay related energy calculation module;
the delay correlation energy calculation module processes the input data which are not delayed and the input data which are delayed to obtain the correlation coefficient of the simplified input data which are not delayed and the simplified input data which are delayed;
the related window energy calculation module calculates the energy value of the received data in the length of the delay window;
the frame search module counts the number of points of which the measurement function is continuously larger than a threshold value, and finds out the initial position of the data frame.
6. The apparatus of claim 5, wherein the delay correlation energy calculating module comprises:
the delay correlation calculation unit is used for calculating the correlation coefficient of the input data which is not delayed and the input data after delay and synchronously outputting the two groups of data;
the correlation accumulation calculating unit accumulates the current correlation coefficient and the delayed correlation coefficient;
amplitude simplificationA calculating unit for solving the accumulated amplitude of the correlation values to obtain a delayed correlation value | Cn|。
7. The apparatus as claimed in claim 6, wherein the correlation window energy calculating module comprises:
the energy value calculating unit is used for carrying out conjugate multiplication on the received data and the received data to obtain an energy value of the received data within the length of the delay window;
an energy value accumulation calculating unit for accumulating the energy values of the received data to obtain a window energy value PnAnd the window energy value P is calculatednSent to the frame search module.
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