CN112216330A - Method for performing memory refresh of non-volatile memory cells - Google Patents

Abstract

A method for performing a memory refresh of a non-volatile memory cell. The invention relates to a method for performing a memory refresh of a non-volatile memory cell, wherein it is checked (210) whether one or more memory regions of the memory cell have an error, wherein if during the checking (210) it is determined that at least one memory region of the memory cell has an error, a refresh time point (220) is determined according to a predefined criterion, at which a memory refresh should be performed on at least one memory region having an error, and wherein a memory refresh (230) is performed on the at least one memory region having an error when a specific refresh time point is reached.

Description

Method for performing memory refresh of non-volatile memory cells

Technical Field

The present invention relates to a method for performing a memory refresh (speichereffrischung) of a non-volatile memory cell, as well as to a computing unit and a computer program for performing the method.

Background

A non-volatile random access memory (NVRAM) is used to store data persistently. Although a non-volatile memory cell retains its memory content even without current supply, the memory content may evaporate sooner or later depending on the type. This applies both with and without voltage supply. Therefore, the non-volatile memory cells must also be refreshed from time to time ("refresh").

Therefore, in the case of a non-volatile memory cell, a so-called refresh, i.e., a memory refresh, is performed on the memory contents stored in the non-volatile memory cell at certain time intervals to retain the memory contents. Here, the memory contents are read and the corresponding memory area is rewritten again using the read memory contents.

Disclosure of Invention

According to the present invention, a method for performing a memory refresh of a non-volatile memory cell, as well as a computing unit and a computer program for performing the method are proposed with the features of the independent claims. Advantageous embodiments are the subject matter of the dependent claims and the following description.

Within the scope of the method, it is checked whether one or more memory regions of the memory unit have an error in each case.

These memory areas may in particular be memory locations or memory locations, in particular the smallest or smallest possible unit or the smallest addressable unit of said memory locations. For example, a bit or a word of bits or data may be stored in each of these memory areas as the smallest addressable unit.

In the present context, an error which indicates a volatilization of the memory contents stored in the memory area is to be understood in particular as an error of the memory area. The detected errors thus indicate in particular that volatilization has occurred or is likely to occur in the respective erroneous memory regions, and therefore the respective erroneous memory regions require in particular a memory refresh in order to avoid data loss. The error detection can be performed, for example, by a checksum or by a hardware-provided integrity check.

If it is determined during the checking that at least one memory region of the memory cells has an error, a refresh time point is determined according to a predefined criterion, at which a memory refresh should be carried out on the at least one memory region having an error. A memory refresh is then performed on the at least one defective memory region when a specific refresh time point is reached. During the memory refresh, the memory contents of the erroneous memory area are suitably read and overwritten with the read memory contents.

The method therefore comprises in particular a monitoring step or an analysis step for identifying and identifying faulty memory regions or memory cells, and furthermore in particular an algorithm for determining an optimum correction or refresh time point, and also suitably a correction mechanism for performing said refresh.

During such a memory refresh of a memory region, it is mostly not possible to access the memory region conventionally, mostly neither reading nor writing. Thus, if the faulty memory area should be accessed during a memory refresh in normal operation, for example because the implemented process wants to access the memory contents stored in the faulty memory area, or because the program code stored in the faulty memory area should be implemented, a delay or even an error in the processing of the process or task may occur. Such delays can have a negative effect on normal operation, leading to high runtime losses and even to the inability to correctly execute the functions to be implemented by said normal operation.

Such delays can have particularly critical effects, particularly in real-time systems, where it is crucial to ensure that a process or task is processed before a particular point in time. For example, in the case of real-time systems in vehicles, such delays or loss of operating time can lead to specific functions of the vehicle no longer being implemented correctly or even possibly failing.

Expediently, the refresh time is determined within the scope of the method such that no such delay, loss of operating time or even errors can occur by the memory refresh. The predefined criterion thus takes into account, in particular, how errors of normal operation can occur by means of a memory refresh and how these errors can be avoided. In particular, with this method, it is thus possible to avoid errors in normal operation by means of a memory refresh and the function no longer being implemented correctly or even failing.

For example, it may be taken into account within the scope of the predefined criteria whether a normal operation, a start-up (so-called spin-up) or a shut-down (so-called idle-up) of the computing unit comprising the memory unit is currently performed. If the checking for errors is performed, for example, during the start-up or shut-down of the computing unit, the identified faulty memory regions can expediently be refreshed immediately, since critical functions are not usually listed and the memory cells are not accessed during these start-up or shut-down phases. In this case, the current or next possible point in time is therefore expediently determined as the refresh point in time.

If an error is detected during normal operation of the computing unit comprising the memory unit, the process or task to be implemented in the computing unit can be taken into account within the scope of the predefined criterion. For example, a process or a flowchart may be considered in which the time points at which a process or task should be performed are stored. In particular, a time point at which no further processes or tasks should be carried out or at least only a small number of further processes or tasks should be carried out can be determined as a refresh time point and thus provide an open time window for performing the memory refresh.

The checking of defective memory regions of the memory cells has no or at least almost no temporal influence, in particular on the processing of the process, so that the checking can also be carried out appropriately in normal operation, without delays, running time losses or errors occurring. In particular, the check can therefore be carried out at predefined check intervals or, where appropriate, also continuously during normal operation. The check interval may in particular be selected according to system requirements with respect to a time range in which the entire memory cell should be checked. If a faulty memory region is identified during the check, this can be reported, in particular, to a higher-level instance or function, for example an operating system or a management program, which then determines the refresh time point.

According to a preferred embodiment, if a point in time that meets the predefined criterion cannot be found, it is checked again after a predefined time interval and/or on request whether the point in time meets the predefined criterion. For example, in the case of a currently high load, it may happen, if necessary, that a point in time at which the memory refresh can be carried out cannot be found currently according to the predefined criteria. In this case, it is expedient to recheck periodically or upon request or upon message whether and if so when the refresh can be performed. In particular, the point in time is checked after the predefined time interval or upon request, respectively, until a suitable refresh point in time can be found which meets the predefined criteria.

According to a particularly advantageous embodiment, the real-time requirements to be met are taken into account as the predetermined criterion. The refresh time is expediently selected such that the real-time requirement is met even if a memory refresh is carried out and in particular no impairment in function occurs. For this purpose, load and/or instantaneous time requirements and/or processes to be carried out in real time may preferably be taken into account. In the case of a high load or a large number of processes to be executed in real time, a point in time after the number of processes has been processed may be selected as a refresh point in time, whereby the time requirements or real-time requirements for these processes may be satisfied.

In particular, the memory refresh can also be carried out immediately if the real-time requirements are not met and, for example, the process is not carried out in real time, and the current or instantaneous point in time can be determined as the refresh point in time.

For example, it is also possible to suspend the system for the duration of the memory refresh. In the case of such a system, the instantaneous time is expediently likewise determined as the refresh time. In this case, the system can expediently be halted after the identification of the faulty memory region, the refresh can be performed immediately, and the system can then resume normal operation again.

It is advantageous to consider as the predetermined criterion whether a predetermined time interval has elapsed since the last correction performed. If necessary, there is a risk of error situations, for example task overflows, in the case of refreshes performed directly or shortly one after the other. It can thus be ensured by the criterion that the predefined time interval always elapses as a safety buffer after the memory refresh has been performed, in order to avoid such an error situation.

The error type of the at least one memory area is preferably taken into account as the predefined criterion. For example, the severity of the errors may be evaluated here, and, for example, a distinction may be made between critical errors that require as fast a refresh as possible and non-critical errors that do not require an immediate refresh. Such a critical error may be, for example, a 2-bit error or an error that can just as well be corrected. For such errors, in particular the next possible point in time can be determined as the refresh point in time.

For example, the non-critical error may be a single bit error. In particular, a refresh may be first put aside if a non-critical error is identified, and may wait until a certain number of such non-critical errors have been identified, for example. The respective defective memory regions can then be suitably collectively refreshed. This has the following advantages on the one hand: multiple errors can be handled together, which can be run-time efficient, and on the other hand can wait with error correction or refresh until a state occurs in which refresh can be performed extensively without loss of functionality, such as during shutdown.

Preferably, a predetermined point in time at which a memory refresh is permitted is taken into account as the predetermined criterion. These predetermined points in time may be determined, for example, before the memory unit or a computing unit comprising the memory unit is put into operation, for example, during a planning or design phase, for example, by means of static analysis. For example, a schedule or flow chart may be created for the compute unit and its processor core(s) during such a design phase, where a particular point in time for performing a memory refresh may be predetermined. Expediently, the time next to the predetermined time points can be determined as the refresh time point when an error is detected.

Preferably, when the memory refresh is performed and further accesses to the at least one erroneous memory region should be performed, for example further accesses to a task, the further accesses are diverted to further memory cells in which the memory contents of the erroneous memory region are redundantly stored. The other memory unit may be, for example, a spare memory unit in which the respective memory content is protected, so that data or program code is doubly saved. The corresponding memory contents can thus also be accessed during a memory refresh without delay or loss of run time.

In particular, before putting into operation, it is determined during the planning or design phase which memory contents are stored redundantly in the further memory units or in the spare memory. For example, all memory contents may be redundantly stored, or only particular memory contents may be stored, such as those whose refreshing may have a significant impact. For example, if the refreshing of the respective memory region lasts 1ms, tasks lasting 1ms or tasks lasting 2ms, for example, may be significantly affected. In contrast, a task lasting 100ms is hardly noticeable at all.

Preferably, the memory contents of the erroneous memory area are copied into other memory cells. If further accesses should be made to at least one defective memory region during the execution of the memory refresh, the further accesses are preferably diverted to the further memory cells. For example, the other memory unit may be a so-called Overlay memory, i.e. a writable memory, which replaces normally non-writable memory by a mechanism. For example, if an error is detected by hardware or by software, a new mechanism can be activated which copies the memory contents of the memory region concerned into the separate overlay memory. After this copying action, the accesses to the faulty memory area are suitably diverted to the other memory units, for example by a Memory Management Unit (MMU) in the processor core, which performs address translation prior to the bus access, or by the flash memory itself, for example when the overlay memory is directly connected to the flash memory. Once this diversion is activated, the memory refresh can be performed without affecting the system. After the refresh is complete, the steering can be overridden, as appropriate, and the memory contents read from the memory cells again.

In a particularly advantageous manner, the invention is suitable for memory cells which are constructed as phase change memories. In such Phase Change Memories (PCMs), in particular, the phase change in a particular alloy is used for storing information. In particular, the change in resistance of the respective phase change material is used here, wherein the phase change material mostly has a high resistance in the amorphous phase and mostly has a low resistance in the crystalline phase. Chalcogenide alloys are mostly used as phase change materials.

The memory unit is advantageously used in a computing unit of a vehicle, in particular in a control unit, for example for controlling an internal combustion engine, an electric motor, a transmission, an ABS, an ESP, etc., or for example in a so-called body computer of a vehicle, for controlling and monitoring components of a body electronics system and the functions thereof. In the worst case, a loss of memory content in such a computing unit of the vehicle may lead to a failure of the vehicle function, which may be a high safety risk. For example, a sudden failure of an engine control device can pose a hazard to occupants of the vehicle and other traffic participants, and even result in the driver losing control of the vehicle. The method is therefore particularly advantageously suitable for memory cells in the vehicle region, in particular for phase change memories, in order to avoid a loss of the memory content, which could lead to a safety risk in the operation of the vehicle.

The computing unit according to the invention, for example a control device of a motor vehicle, is in particular programmed to carry out the method according to the invention.

The implementation of the method according to the invention in the form of a computer program or a computer program product with program code for executing all method steps is also advantageous, since this results in particularly low costs, in particular if the control device which is implemented is also used for other tasks and is therefore present anyway. Suitable data carriers for providing the computer program are in particular magnetic, optical and electrical memories, such as a hard disk, flash memory, EEPROM, DVD, etc. The program may also be downloaded via a computer network (internet, intranet, etc.).

Further advantages and configurations of the invention emerge from the description and the drawings.

The invention is schematically illustrated in the drawings on the basis of embodiments and is described below with reference to the drawings.

Drawings

Fig. 1 schematically shows a control device of a motor vehicle, which control device is designed to carry out a preferred embodiment of the method according to the invention.

Fig. 2 schematically shows a preferred embodiment of the method according to the invention as a block diagram.

Fig. 3 schematically shows a timing diagram that can be determined during the course of a preferred embodiment of the method according to the invention.

Fig. 4 schematically shows a timing diagram that can be determined during the course of a preferred embodiment of the method according to the invention.

Fig. 5 schematically shows a timing diagram that can be determined during the course of a preferred embodiment of the method according to the invention.

Detailed Description

In fig. 1, a control device of a vehicle is schematically shown and indicated with 100. For example, the control apparatus 100 may be an engine control apparatus for controlling an internal combustion engine of the vehicle.

The control device 100 comprises a processor unit 110, which processor unit 110 may be configured, for example, as a multicore processor having a plurality of processor cores. The control device 100 also comprises a non-volatile memory unit 120, which non-volatile memory unit 120 is particularly preferably designed as a Phase Change Memory (PCM).

The memory unit 120 includes a large number of different memory areas 121. Although only three such memory regions 121 are shown in FIG. 1 for clarity, it should be understood that the memory unit 120 may include other suitable numbers of memory regions. These memory areas 121 are in each case a memory location or a memory position, in particular the smallest addressable unit of the memory unit 120, in which, for example, a word or data word consisting of a plurality of bits is respectively stored.

During the normal operating mode, the processor unit 110 executes a process for controlling the engine of the vehicle, for example in order to determine the injection time or the amount of fuel to be injected. To this end, certain processes or tasks are performed by the processor unit 110 in real time. For example, data can be stored in the memory unit 120, which are necessary for carrying out these processes or tasks and thus for determining the injection time and the fuel quantity to be injected.

Although non-volatile memory cells, such as memory cell 120, retain their memory content even in the absence of a current supply, the memory content may, in time, volatilize. This applies both with and without voltage supply. To avoid data loss due to such volatilization, it is important to perform memory refresh on the memory cells 120 periodically.

For this purpose, the control device 100 is designed, in particular in program technology, as a preferred embodiment for carrying out the method according to the invention, which is schematically illustrated as a block diagram in fig. 2.

In step 210, it is checked by the processor unit 110 whether one or more memory areas 121 of the memory unit 120 have errors. In particular, it is checked for each memory cell 121 of the memory cells 120 whether a criterion is fulfilled which indicates a data loss or volatilization, for example because a checksum error is detected.

The checking 210 of the defective memory region is expediently repeated at predefined time intervals, which is denoted by reference numeral 211. Since this check has no or at least little temporal influence, in particular on the processing of the process by the processor unit 110, it is expediently carried out during normal operation of the control device 100. In particular, the check 210 may be performed continuously during normal operation.

If it is determined during the check 210 that at least one memory area of the memory unit 120 has an error, a refresh time point is determined in step 220, according to a predefined criterion, at which a memory refresh should be performed on the at least one memory area having an error.

In particular, the real-time requirements to be met are taken into account as the pre-given criteria and the refresh time point is determined in such a way that the respective real-time requirements of the process to be executed by the processor unit 110 can be met even if the memory refresh is performed.

For this purpose, the current load of the processor unit 110 may also be taken into account as the predefined criterion, for example based on a process or a flowchart which specifies which processes or tasks are to be processed by the processor unit 110 at what point in time. Suitably, as a refresh point in time, a point in time is determined at which no or at least almost no further processes or tasks are carried out by the processor unit 110.

For example, in the case of a currently high load of the processor unit 110, it may happen that, in step 220, a point in time at which the memory refresh can be performed without a delay or loss of running time of the processor unit 110 cannot currently be found according to the predefined criterion. In this case, which is denoted by reference numeral 221, it is checked again after a predefined time interval whether a point in time can be found which meets the predefined criterion and thus the memory refresh should be performed at this point in time.

When the specified refresh time point is reached, a memory refresh is carried out in step 230 on the at least one defective memory region by reading the memory contents stored in the respective defective memory region and rewriting them into the respective memory region.

Examples of preferred embodiments of the method according to the invention are shown in fig. 3 to 5, based on time diagrams, respectively, wherein the horizontal axes respectively represent the time t.

In these figures, the blocks, respectively denoted with reference numeral 210, represent checking whether at least one memory area 121 of the memory unit 120 has an error, as explained previously with reference to fig. 2.

In fig. 3, 4 and 5, the start-up or cranking of the control device 100 is indicated by 301, 401 and 501, respectively, the normal operation is indicated by 302, 402 and 502, respectively, and the idling or turning-off is indicated by 303, 403 and 503, respectively.

As can be seen in fig. 3, 4 and 5, the check is performed once during start-up and once during shut-down, respectively, and a plurality of checks are performed at regular time intervals during normal operation.

In the example shown, during start- up 301, 401 and 501, respectively, a check is performed and an error of the memory area is identified. Since no critical functions have been implemented in the control device 100 and no memory cells 120 have been accessed during the start-up, the respective faulty memory areas are immediately refreshed, respectively, which is represented by blocks 310, 410 and 510, respectively.

Accordingly, an error is also exemplarily recognized during the shut-down 303, 403 and 503, respectively, wherein here too the respective erroneous memory region is immediately refreshed, as indicated by blocks 330, 440 and 530, respectively, since the memory cell 120 is no longer accessed during the shut-down.

In fig. 3, it is also exemplarily assumed that an erroneous memory region is identified at time t1 during normal operation 302 of the control device 100. However, this defective memory area is not refreshed immediately, but the point in time t2 is determined as the refresh point in time at which the refresh should be performed, thereby not causing a limitation on the real-time capability of the control device 100. At time point t1, for example, reporting to an upper level instance, such as an operating system or hypervisor, that a corresponding memory refresh should be performed at refresh time point t2, which is represented by block 321.

Upon reaching the refresh time point, the corresponding upper level instance instructs the refresh to be performed, which is represented by block 322. The refresh is then performed, as represented by block 323.

If the control device 100 does not implement the procedure in real time, for example, the identified defective memory regions can also be refreshed immediately during normal operation, as is shown, for example, in fig. 4.

At time t3, an error is identified and a memory refresh is immediately performed according to block 420. At time t4, for example, a defective memory area is likewise identified. Here, the upper level instance is first reported, which then authorizes an immediate refresh 432, according to block 431.

According to a preferred embodiment, it can further be provided that in the case of a non-critical error, instead of performing the refresh immediately and not individually, a common multiple refresh is performed, as is shown by way of example in fig. 5.

Such non-critical errors may be individual bit errors, for example. When such non-critical errors are identified, it may be appropriate to first wait until a certain number of non-critical errors are identified before performing a refresh.

This is shown in fig. 5 by way of example, in which a first non-critical error is detected at time t5 during normal operation of the control unit 100 and is reported to the superordinate instance in accordance with block 521. At time t6, a second non-critical error is identified and reported to the upper-level instance according to block 522. Furthermore, at time t7 a third non-critical error is identified and reported to the upper-level instance according to block 523.

In block 523, the upper-level instance determines time t8 as the refresh time at which the respective defective memory regions with the three non-critical errors should be refreshed jointly. The memory refresh is performed at refresh time point t8, as per block 524.

Claims (13)

1. Method for performing a memory refresh of a non-volatile memory cell (120),

wherein it is checked (210) whether one or more memory areas (121) of the memory unit (120) have errors,

wherein, if it is determined during the checking (210) that at least one memory region (121) of the memory cells (120) has an error, a refresh time point (220) is determined according to a predetermined criterion, at which a memory refresh should be performed on the at least one memory region (121) having an error, and

wherein a memory refresh (230) is performed on the at least one defective memory region (121) when a specific refresh time point is reached.

2. Method according to claim 1, wherein if a point in time meeting the pre-given criteria cannot be found, it is rechecked after a pre-given time interval and/or upon request whether the point in time meets the pre-given criteria (211).

3. Method according to claim 1 or 2, wherein real-time requirements to be met, in particular load and/or instantaneous time requirements and/or processes to be performed in real time, are taken into account as the pre-given criteria.

4. Method according to one of the preceding claims, wherein it is taken into account as the predefined criterion whether a predefined time interval has elapsed since the last executed memory refresh.

5. Method according to one of the preceding claims, wherein the type of error of the at least one memory area is taken into account as the predefined criterion.

6. Method according to any of the preceding claims, wherein a predetermined point in time at which a memory refresh is allowed is considered as the pre-given criterion.

7. Method according to one of the preceding claims, wherein when the memory refresh is performed and an access to the at least one erroneous memory region (121) should be performed, the access is diverted to other memory cells in which the memory content of the erroneous memory region is redundantly deposited.

8. Method according to any of the preceding claims, wherein the memory contents of the erroneous memory region (121) are copied into other memory cells, and wherein, if an access should be made to the at least one erroneous memory region during the execution of the memory refresh, the access is diverted to the other memory cells.

9. The method of any preceding claim, wherein the memory cell (120) is a phase change memory.

10. The method according to any one of the preceding claims, wherein the memory unit (120) is used in a computing unit (100) of a vehicle, in particular in a control device (100).

11. Computing unit (100) designed to perform all the method steps of the method according to any one of the preceding claims.

12. Computer program which, when executed on a computing unit (100), causes the computing unit (100) to perform all method steps of the method according to any one of claims 1 to 10.

13. A machine readable storage medium having stored thereon a computer program according to claim 12.

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