CN1122030A - Apparatus and method for series connection of graph processing devices - Google Patents
Apparatus and method for series connection of graph processing devices Download PDFInfo
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- CN1122030A CN1122030A CN 94115284 CN94115284A CN1122030A CN 1122030 A CN1122030 A CN 1122030A CN 94115284 CN94115284 CN 94115284 CN 94115284 A CN94115284 A CN 94115284A CN 1122030 A CN1122030 A CN 1122030A
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Abstract
The cascade device of graphic processors comprises timing sequence generator, pixel synchronizer, level comparator, mode selector, cascade controller and colour code output device. Even graphic processors comprising one master and other secondaries are cascaded and the master processor provides pixel and field synchronous signal for secondary processors. The colour code output sequence is controlled by cascade control signal based on the result of comparing cascade level codes. The colour codes sequentially output from graphic processors are collected on colour code bus.
Description
The present invention relates to a kind of stringer and method of graphic processing facility.
Usually the graphics capability of graphic processing facility can be subjected to the restriction of its hardware configuration, and therefore after its hardware configuration was fixing, its graphics capability just was difficult to improve again.In addition, graphic processing facility of the prior art can't be accomplished plural serial connection processing mostly, otherwise is the processing that can't do again after the serial connection on the level.Therefore, can't disposal system processing power special graph treatment effect in addition.
In view of this, an object of the present invention is in the graphics process demand to provide the space of expansion during greater than the maximum processing capability of hardware.
Another object of the present invention is that the function of each graphic processing facility of serial connection can be identical, so just various particular processing functions all must not focused on the wafer.
The purpose of this invention is to provide a kind of series-mounting and device between the different graphic treating apparatus, the graphic processing circuit (IC) that will have this stringer is connected in series, and uses the graphics capability that strengthens total system.
The stringer of a kind of graphic processing facility provided by the invention, in order to being connected in series a main graphic treating apparatus and at least one time graphic processing facility, comprising:
One sequential generation device in order to producing required control timing of various graphics process and synchronizing signal, and is wanted to produce or to receive a pixel synchronizing signal and a figure field sync signal, makes the scanning sequence can be synchronous with each graphic processing facility;
One pixel synchronous device in order to according to aforementioned pixel synchronizing signal, makes the pixel synchronizing signal of the colour coding of each graphic processing facility and layer code and aforementioned main graphic treating apparatus synchronous;
One level comparison means,, and will send its prime graphic processing facility to through the layer code of the higher level that relatively obtains and compare by the layer code of a graphic processing facility of aforementioned pixel synchronous device output with by the level of the layer code of one-level graphic processing facility output thereafter in order to relatively;
One serial connection control device, in order to receiving aforementioned level comparison means, the layer code of the layer code of output and the output of pixel synchronous device, and control the output of colour coding according to this;
One colour coding output unit, in order to receiving the colour coding data by aforementioned pixel synchronous device output, and whether the control signal control that is subjected to aforementioned serial connection control module output exports the colour coding data with decision.
Series-mounting provided by the invention, comprised following step: (1) is at first with plural graphic processing facility serial connection, promptly as shown in Figure 1, set one of them and be the main graphic treating apparatus, other be time graphic processing facility, and provide a pixel synchronizing signal and a figure field sync signal inferior graphic processing facility to other by the main graphic treating apparatus; (2) utilize the layer code of a serial connection to begin to carry out layer code relatively by the graphic processing facility of last two-stage in regular turn, again that level is higher layer code offers the previous stage graphic processing facility and carries out level relatively; (3), utilize a control signal that is connected in series to control the colour coding output order of each graphic processing facility again according to level result relatively; (4) colour coding that each graphic processing facility is exported in regular turn all is pooled on the colour coding bus.
In order to be illustrated more clearly in method of the present invention, device and characteristics, it is as follows that conjunction with figs. describes preferred embodiment in detail now:
The simple declaration of accompanying drawing:
Fig. 1 is the block scheme of serial connection mode of the present invention;
Fig. 2 is the block scheme of a graphic processing facility structure;
Fig. 3 is the block scheme of a sequential generation device structure;
Fig. 4 is the sequential chart in the timing sequence generating device;
Fig. 5 is the block scheme of stringer of the present invention;
Fig. 6 is the circuit diagram of a preferred embodiment of stringer of the present invention;
Fig. 7 is the circuit diagram of another preferred embodiment of stringer of the present invention;
Fig. 8 is the graphic of a display result of the present invention;
Fig. 9 is the graphic of another display result of the present invention.
See also Fig. 1, serial connection mode of the present invention is that a plurality of graphic processing facilities are connected in series, and sets one of them for main graphic treating apparatus 10, and other then is respectively graphic processing facility 20, graphic processing facility 21 etc. for the second time for the first time.By the scanning sequence of main graphic treating apparatus 10 control total systems synchronously.Therebetween and utilize the layer code 11,12 and 13 of serial connection to control the depth of field of each figure, thus the front and back order of the figure that produced of different graphic treating apparatus can control by software.And the layer code of the figure that is produced when the different graphic treating apparatus is when identical, and it is basic puts in order promptly and to be arranged in regular turn to the graphic processing facility of last level by the graphic processing facility of prime.It utilizes a serial connection signal 14,15 and 16 to control colour coding 17 outputs of each graphic processing facility simultaneously, the colour coding output of each graphic processing facility can be connected on the same group of bus, and in the cycle length of a pixel clock 18, export with the colour coding that a graphic processing facility is arranged only.And if the code of the just color of its colour coding output then needs to convert rgb signal to via a palette 30 again.
Generally speaking, make the plural different graphic treating apparatus can parallel processing, at first just must solve the stationary problem between the different graphic treating apparatus.The present invention utilizes two synchronizing signals of different nature to solve stationary problem between the different graphic treating apparatus, that is: a pixel synchronizing signal 18, with so that between colour coding output and layer code synchronously; With a figure field sync signal 19, with so that scanning sequence is synchronous, it is one subsynchronous that each graphic processing facility is all done before back or beginning are finished in each figure field, so it can utilize the initial value of setting each figure field with the relevant signal of vertical cycle.Aforesaid pixel synchronizing signal 18 and figure field sync signal 19 all are to be sent by main graphic treating apparatus 10, and each time graphic processing facility 20 and 21 is just adjusted the processing sequential of its inside according to this synchronizing signal.
See also Fig. 2, a common employed graphic processing facility of electronic game machine comprises following several sections: a sequential generation device 40, in order to produce required synchronizing signal of a TV and control timing signal; One system control unit 42 is in order to the interface between a conduct and a control system (not shown), the operator scheme of may command graphic processing facility; At least one graphic operation unit 44 is in order to be converted to graphic color consistent with scanning sequence and luminance signal with various graphic parameters; One power and position control module 46 in order to when a plurality of graphic operations unit is arranged, is judged the order of colour coding output.
In the present invention, in order to be connected in series a plurality of graphic processing facilities, so must make each graphic processing facility synchronous earlier.See also Fig. 3, the timing sequence generating device among the present invention comprises: basic signal generator 50 for the moment, and in order to receiving the clock signal of an input, and use and produce the required basic clock signal (dotclck) of a graphics process; One horizontal counter 51, the time that the basic clock signal that produces in order to the aforementioned time-base signal generator 50 of foundation calculates a horizontal scanning line; One horizontal demoder 52 in order to receiving the leveler logarithmic data HD by 51 outputs of aforementioned levels counter, and is decoded into required horizontal control timing HCCK of various graphics process and synchronizing signal HS with the leveler logarithmic data; One vertical counter 53 is in order to figure of horizontal cycle signal HPS calculating time of foundation aforementioned levels demoder 52 outputs; One vertical demoder 54 in order to receiving the vertimeter logarithmic data VD by aforementioned vertical counter 53 outputs, and is decoded into the required vertical control timing VCCK of various graphics process and a synchronizing signal VS and a vertical blanking signal (Vblank) with the vertimeter logarithmic data; One major-minor system synchronization device 60, in order to utilizing a major-minor system to select signal SD to decide the role of a graphic processing facility in total system, that is the output of the vertical blanking signal (Vblank) of the basic clock signal that produces of the basic at that time signal generator 50 of control and 54 outputs of vertical demoder whether.Wherein, aforementioned major-minor system synchronization device 60 comprises: a pixel synchronizing signal output-controlling device 57, can be a ternary output and go into impact damper (tri-state I/O buffer), select basic clock signal that signal controlling produces with decision clock signal generator 50 as input one pixel synchronizing signal in pixel synchronizing signal (pixel clock) or the autonomous graphic processing facility in order to be subjected to the major-minor system; One figure field sync signal output-controlling device 56, also can be a ternary output and go into impact damper, in order to be subjected to the major-minor system select signal controlling with decision output by the vertical blanking signal (Vblank) of aforementioned vertical demoder 54 outputs as input one figure field sync signal in figure field sync signal or the autonomous graphic processing facility; One positive edge detector 55, (the positive edge of (Vblank) obtains a setting signal (prese) to set aforementioned levels counter 51 and vertical counter 53 initial value in each figure field by aforementioned vertical blanking signal.The method of its setting is to utilize two or 58 and 59 to set horizontal initial value and vertical initial value respectively, sees also Fig. 4, the sequential chart of the circuit of Fig. 4 displayed map 3.So, when it was the main graphic treating apparatus, pixel synchronizing signal and vertical blanking signal (Vblank) were output, and when it be time graphic processing facility, pixel synchronizing signal and vertical blanking signal (Vblank) were to import.Pixel synchronizing signal offers level and relatively reaches colour coding output and make synchronous usefulness, and the still basic clock signal of employing generation of the minimum time unit of the inner employed pixel of graphic processing facility itself.
See also Fig. 5, the stringer of graphic processing facility of the present invention is in order to be connected in series a main graphic treating apparatus and at least one time graphic processing facility, and it does the control that colour coding is exported after can placing power and position control module shown in Figure 2 46.This stringer comprises: a sequential generation device 40, in order to produce required control timing of various graphics process and synchronizing signal, and want to produce or to receive a pixel synchronizing signal and a figure field sync signal, make the scanning sequence can be synchronous with each graphic processing facility; One pixel synchronous device 70, in order to pixel synchronizing signal (pixel clock) according to aforementioned timing sequence generating device 40, make the pixel synchronizing signal of the colour coding of each graphic processing facility and layer code and aforementioned main graphic treating apparatus synchronous, it can be made of one group of D flip-flop; One level comparison means 72, in order to relatively by the layer code of a graphic processing facility of aforementioned pixel synchronous device 70 outputs with by the level between the layer code (level-in) of one-level graphic processing facility output thereafter, and will send its prime graphic processing facility to through the layer code (level-out) of the higher level that relatively obtains and compare, wherein each layer code comprises depth queuing and transparent two kinds of data of figure; One mode selector 74, in order to receive, be subjected to mode select signal CM control again to select the overlapping pattern (being illustrated again after a while) of level between the different graphic treating apparatus by the layer code TPIC of aforementioned pixel synchronous device 70 outputs and the layer code of aforementioned level comparison means 72 outputs; One serial connection control device 76 reaches the level comparative result CASENI that is exported by the prime graphic processing facility in order to the level comparative result that receives by 74 outputs of previous mode selecting arrangement, and controls the output of colour coding according to this; One colour coding output unit 78, can be an impact damper, in order to receive colour coding data by aforementioned pixel synchronous device 70 outputs, and whether the control signal CCOE control that is subjected to aforementioned serial connection control module 76 outputs exports the colour coding data with decision, the also even existing output of prime graphic processing facility, then close itself colour coding output and notice back level graphic processing facility and close colour coding output, itself will export if the prime graphic processing facility is not exported, then opening aforementioned colour coding output unit does not export by colour coding output and notice back level graphic processing facility, again if prime graphic processing facility and equal no-output itself then notify back level graphic processing facility to do to export judgement.
See also Fig. 6, Fig. 6 is a side circuit of stringer of the present invention, and it can carry out the processing of four layers of depth of field.Wherein, pixel synchronous device 70 is made of the two-stage D flip-flop, and the clock signal DOTCK of the first order is the pixel period signal that the timing sequence generating device of itself is produced, and partial clock signal PIXCK is the pixel synchronizing signal for sending here from the main graphic treating apparatus then.In addition, aforementioned level comparison means 72 comprises: two group decoding devices 721 and 722, in order to receive the layer code IL[0 of a graphic processing facility itself respectively], IL[1] and the IT and the layer code EPL[0 of one-level graphic processing facility thereafter], EPL[1] and EPT, and with its decoding so that compare, the truth table of decoding device is as shown in the table:
TSP L1 L0 0[3] 0[2] 0[1] 0[0]
0 0 0 1 0 0 0
0 0 1 0 1 0 0
0 1 0 0 0 1 0
0 1 1 0 0 0 1
1 * * 0000 because layer code contains transparent data, therefore when its when being transparent (TSP=1), decoding device is output as zero; One comparison means 723 is in order to receive the hierarchical data LL[3 through decoding of aforementioned two graphic processing facilities: 0] and EL[3: 0], and compared; One selecting arrangement 724, the layer code output in order to according to the comparative result of aforementioned comparison means 723 that level is higher compares to offer its prime graphic processing facility again.See also Fig. 7, in aforementioned level comparison means 72, also can use a subtracter 725 to replace decoding device 721 and 722 and comparison means 723 among Fig. 6, and judge size with positive negative value.
Please consult Fig. 6 again, wherein, the result of serial connection control module 76 use mode selectors 74 gained and the level comparative result CASENI of prime graphic processing facility output control the output of colour coding, and CASENI is the CASENO from the previous stage graphic processing facility.And mode selector 74 be before utilizing a mode select signal CM by internal processes control to select level relatively (being the transparent data of itself) or relatively after the result, if the result after selecting level relatively, then be to be the foundation of main graphics hierarchy arrangement with layer code, if the transparent data of itself before selecting relatively, then be that the serial connection sequence with graphic processing facility is that main graphics hierarchy is arranged foundation.Both results such as Fig. 8 and shown in Figure 9, Fig. 8 are to be the foundation that main graphics hierarchy is arranged with layer code, and Fig. 9 then is that the serial connection sequence with graphic processing facility is the foundation that main graphics hierarchy is arranged.Wherein, image 91 and 92 is the result of two graphic operation unit output in the main graphic treating apparatus, and the layer code of image 91 is 2, and the layer code of image 92 is 1; Image 93 and 94 are the result of two graphic operation unit output in time graphic processing facility, and the layer code of image 93 is 2, and the layer code of image 94 is 1.In Fig. 8, the result of image 95 for showing that its level is arranged, it is respectively image 92, image 94, image 91 and image 93 in proper order.And in Fig. 9, the result that its level is arranged, the order of image 96 then is image 92, image 91, image 94 and image 93.
Though the present invention discloses as above with a preferred embodiment, so it is not in order to qualification the present invention, so protection scope of the present invention is as the criterion when looking the accompanying Claim scope person of defining.
Claims (10)
1, a kind of stringer of graphic processing facility in order to be connected in series a main graphic treating apparatus and at least one time graphic processing facility, is characterized in that, wherein, comprising:
One sequential generation device in order to producing required control timing of various graphics process and synchronizing signal, and is wanted to produce or to receive a pixel synchronizing signal and a figure field sync signal, makes the scanning sequence can be synchronous with each graphic processing facility;
One pixel synchronous device in order to according to aforementioned pixel synchronizing signal, makes the pixel synchronizing signal of the colour coding of each graphic processing facility and layer code and aforementioned main graphic treating apparatus synchronous;
One level comparison means,, and will send its prime graphic processing facility to through the layer code of the higher level that relatively obtains and compare by the layer code of a graphic processing facility of aforementioned pixel synchronous device output with by the level of the layer code of one-level graphic processing facility output thereafter in order to relatively;
One serial connection control device, in order to receiving aforementioned level comparison means, the layer code of the layer code of output and the output of pixel synchronous device, and control the output of colour coding according to this;
One colour coding output unit, in order to receiving the colour coding data by aforementioned pixel synchronous device output, and whether the control signal control that is subjected to aforementioned serial connection control module output exports the colour coding data with decision.
2, device as claimed in claim 1 is characterized in that, wherein, aforementioned timing sequence generating device comprises:
Basic signal generator for the moment in order to receiving the clock signal of an input, and is used and is produced the required basic clock signal of a graphics process;
One horizontal counter, the time of calculating a horizontal scanning line in order to the basic clock signal that produces according to aforementioned time-base signal generator;
One horizontal demoder in order to receiving the leveler logarithmic data by the output of aforementioned levels counter, and is decoded into various graphics process required horizontal control timing and synchronizing signal with the leveler logarithmic data;
One vertical counter is in order to figure of horizontal cycle calculated signals time of foundation aforementioned levels demoder output;
One vertical demoder in order to receiving the vertimeter logarithmic data by aforementioned vertical counter output, and is decoded into required vertical control timing of various graphics process and synchronizing signal with the vertimeter logarithmic data;
One major-minor system synchronization device, in order to the output of a vertical blanking signal of controlling basic clock signal that aforementioned time-base signal generator produces and aforementioned vertical demoder output whether.
3, device as claimed in claim 1 is characterized in that, wherein, aforementioned level comparison means comprises:
Two group decoding devices, in order to the layer code that receives a graphic processing facility respectively and the layer code of one-level graphic processing facility thereafter, and with its decoding so that compare;
One comparison means in order to receive the hierarchical data through decoding of aforementioned two graphic processing facilities, and is compared;
One selecting arrangement, the layer code output in order to according to the comparative result of aforementioned comparison means that level is higher compares to offer its prime graphic processing facility again.
4, device as claimed in claim 1 is characterized in that, wherein, aforementioned level comparison means comprises:
One subtracter reaches the layer code of one-level graphic processing facility thereafter in order to the layer code that receives a graphic processing facility respectively, and it is subtracted each other;
One selecting arrangement, in order to the result who subtracts each other according to aforementioned subtracter, and the layer code that level is higher output compares to offer its prime graphic processing facility again.
5, device as claimed in claim 1, it is characterized in that, more comprise a mode selector, in order to receive, be subjected to mode select signal control again to select the overlapping pattern of level between the different graphic treating apparatus by the layer code of aforementioned pixel synchronous device output and the layer code of aforementioned level comparison means output.
6, device as claimed in claim 2 is characterized in that, wherein, aforementioned major-minor system synchronization device comprises:
One pixel synchronizing signal output-controlling device selects signal controlling to import pixel synchronizing signal with the basic clock signal that the aforementioned time-base signal generator of decision output produces as pixel synchronizing signal or in aforementioned main graphic treating apparatus in order to be subjected to a major-minor system;
One figure field sync signal output-controlling device, in order to be subjected to the major-minor system select signal controlling with decision output by a vertical blanking signal of aforementioned vertical demoder output as the figure field sync signal or in aforementioned main graphic treating apparatus input figure field sync signal;
One positive edge detector obtains a setting signal to set aforementioned levels counter and the vertical counter initial value in each figure field from the positive edge of aforementioned vertical blanking signal.
7, a kind of serial connection mode of graphic processing facility is characterized in that, comprises the steps:
(I) with a plurality of graphic processing facilities serial connection, to set one of them and be the main graphic treating apparatus, other be inferior graphic processing facility, and provides a pixel synchronizing signal and a figure field sync signal inferior graphic processing facility to other by the main graphic treating apparatus;
(II) utilize the layer code of a serial connection to make each graphic processing facility carry out level relatively;
(III), utilize a control signal that is connected in series to control the colour coding output order of each graphic processing facility again according to level result relatively;
(IV) colour coding that each graphic processing facility is exported in regular turn all is pooled on the colour coding bus.
8, method as claimed in claim 7 is characterized in that, wherein, aforementioned layer code is that it comprises graphics hierarchy data and transparent data in order to the depth of field of definition figure
9, method as claimed in claim 7, it is characterized in that, wherein, the comparative sequence of aforementioned serial connection layer code is that the graphic processing facility by last two-stage begins to carry out layer code relatively, more higher layer code is offered the previous stage graphic processing facility and carries out the level comparison.
10, method as claimed in claim 7, it is characterized in that, wherein, the control sequence of aforementioned serial connection control signal is the graphic processing facility by the foremost one-level, result according to the level comparison judges whether colour coding will be exported, if will export the colour coding output that then need close one-level graphic processing facility thereafter,, judge according to the result of level comparison whether colour coding will be exported if do not export then again graphic processing facility by the back one-level.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN94115284A CN1042678C (en) | 1994-09-16 | 1994-09-16 | Apparatus and method for series connection of graph processing devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN94115284A CN1042678C (en) | 1994-09-16 | 1994-09-16 | Apparatus and method for series connection of graph processing devices |
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| Publication Number | Publication Date |
|---|---|
| CN1122030A true CN1122030A (en) | 1996-05-08 |
| CN1042678C CN1042678C (en) | 1999-03-24 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN94115284A Expired - Lifetime CN1042678C (en) | 1994-09-16 | 1994-09-16 | Apparatus and method for series connection of graph processing devices |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106293591A (en) * | 2015-06-23 | 2017-01-04 | 罗姆股份有限公司 | Time schedule controller, the use electronic equipment of time schedule controller, the processing method of view data |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0740252B2 (en) * | 1986-03-08 | 1995-05-01 | 株式会社日立製作所 | Multi-processor system |
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1994
- 1994-09-16 CN CN94115284A patent/CN1042678C/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106293591A (en) * | 2015-06-23 | 2017-01-04 | 罗姆股份有限公司 | Time schedule controller, the use electronic equipment of time schedule controller, the processing method of view data |
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| Publication number | Publication date |
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| CN1042678C (en) | 1999-03-24 |
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Expiration termination date: 20140916 Granted publication date: 19990324 |