CN112202413B - Multi-beam phased array miniaturized asymmetric power synthesis network structure and calibration method - Google Patents

Multi-beam phased array miniaturized asymmetric power synthesis network structure and calibration method Download PDF

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CN112202413B
CN112202413B CN202011076785.2A CN202011076785A CN112202413B CN 112202413 B CN112202413 B CN 112202413B CN 202011076785 A CN202011076785 A CN 202011076785A CN 112202413 B CN112202413 B CN 112202413B
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power
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CN112202413A (en
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贾海昆
邓伟
池保勇
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Chengdu Borui Microelectronics Technology Co.,Ltd.
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Beijing Borui Microelectronics Technology Co ltd
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    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03GCONTROL OF AMPLIFICATION
    • H03G3/00Gain control in amplifiers or frequency changers
    • H03G3/20Automatic control
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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    • Y02D30/70Reducing energy consumption in communication networks in wireless communication networks

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Abstract

The invention discloses a multi-beam phased array miniaturized asymmetric power synthesis network structure and a calibration method, which belong to the field of integrated circuit design. The miniaturized asymmetric power synthesis network comprises 16 paths of inputs and 4 paths of outputs, wherein each 4 paths of power synthesis to 1 path of power synthesis adopts an asymmetric structure, and the middle of the power synthesis network is connected together by adopting a coupling transmission line; on the chip, four sets of coupled transmission lines are arranged horizontally. The invention uses the asymmetric full-connection power synthesis network to reduce the wiring complexity and occupied chip area of the power synthesis network, and uses the calibration technique to compensate the mismatch introduced asymmetrically, thus realizing the compact power synthesis network. In order to reduce the area of the phased array power synthesis network, the area of a chip is reduced, and the cost is reduced.

Description

Multi-beam phased array miniaturized asymmetric power synthesis network structure and calibration method
Technical Field
The invention belongs to the field of integrated circuit design. In particular to a multi-beam phased array miniaturized asymmetric power synthesis network structure and a calibration method.
Background
In the existing phased array design, the power synthesis network is formed by cascading two-to-one power synthesizers in a multistage symmetrical mode, the wiring is complex in the mode, a large amount of chip area is occupied, and meanwhile, the loss of each stage of power synthesizers is overlapped, so that the overall loss is overlarge. An example of a symmetrical fully connected power combining network applied to a four antenna four beam phased array is given in fig. 1, wherein the specific arrangement of four sets of coupled transmission lines in horizontal arrangement is that a 1# antenna, a 2# antenna and a 4# antenna are sequentially arranged on the left side of a chip; the right side of the chip is correspondingly and sequentially provided with a 1# transmitting passage, a 2# transmitting passage and a 4# transmitting passage; are connected by four groups of coupling transmission lines respectively. The wiring has become very complex, and the number of antennas or the number of reception paths has further increased, and the wiring thereof has become more complex.
Disclosure of Invention
The invention aims to provide a multi-beam phased array miniaturized asymmetric power synthesis network structure and a calibration method, which are characterized in that the miniaturized asymmetric power synthesis network comprises 16 paths of inputs and 4 paths of outputs, wherein the power synthesis of 1 path of output in each 4 paths of inputs to 4 paths of outputs adopts an asymmetric structure, and the middle of the power synthesis is connected together by adopting a coupling transmission line; on the chip, four sets of coupled transmission lines are arranged horizontally.
On the chip, the four groups of coupling transmission lines are horizontally arranged, namely, 16 paths of inputs are divided into one group every 4 paths, and 1 path of inputs in each group is correspondingly connected with 1 path of outputs of 4 paths; namely, a certain 1-way input in the 1 st-4 th-way inputs is correspondingly connected with a certain 1-way output of the 4-way outputs through a coupling transmission line; some 1 way input in 5 th to 8 th way inputs is connected with some 1 way output of 4 way outputs correspondingly through coupling transmission line; some 1 way input in 9 th to 12 way inputs is connected with some 1 way output of 4 way output through coupling transmission line and some 1 way input in 13 th to 16 way inputs is connected with some 1 way output of 4 way output through coupling transmission line.
A calibration method for a multi-beam phased array miniaturized asymmetric power synthesis network comprises the following steps: comprises the following steps of
1) Establishing a phase mismatch calibration device among all paths, connecting the phase shifters with the variable gain amplifier in parallel, and connecting the phase shifters with 4 paths, wherein the input ends of the four phase shifters are respectively connected through coupling transmission lines, a buffer stage is connected between a first path and a second path, and input power is added to the input end of the buffer stage; the output ends of the variable gain amplifiers of the 1 st path and the 2 nd path are connected, and the output ends of the variable gain amplifiers of the 3 rd path and the 4 th path are connected, and then the variable gain amplifiers of the 1 st path and the 2 nd path are connected with a power synthesizer and a power tester;
2) Only opening the 1 st input path and the 2 nd input path, injecting certain power, observing a voltage value given by the power detector at the output end, setting a control code of the 1 st phase shifter of the 1 st input path to zero, and adjusting the 2 nd phase shifter in the 2 nd input path to ensure that the output voltage value of the power detector reaches the maximum; when the two paths of signals are overlapped in phase, the output power is maximum, and the phases of the 1 st path of input and the 2 nd path of input are considered to be aligned, and the phase shift value in the 2 nd path of input is the offset code;
3) Only opening the 1 st input path and the 2 nd input path, and obtaining a phase shifter bias code in the 4 th input path in the same way as the step 2);
4) Opening all 16 paths of input channels, injecting certain power, and simultaneously adjusting a 3# phase shifter and a 4# phase shifter on the basis of the bias code to ensure that the output voltage value of a power detector reaches the maximum; at this time, the phase calibration can be considered to be completed, and the phase shift value of each input path is the bias code of each phase shifter;
5) After calibration is completed, each phase shifter obtains a group of bias codes; when beam direction control is performed, a beam direction control code is superimposed on the offset code; since the beam direction is only related to the adjacent phase shift between channels, the bias code does not affect the control of the beam direction.
The invention has the advantages that the wiring complexity and occupied chip area of the power synthesis network are reduced by using the asymmetric full-connection power synthesis network, and the mismatch introduced by the asymmetry is compensated by adopting the calibration technology, so that the compact power synthesis network is finally realized. In order to reduce the area of the phased array power synthesis network, the area of a chip is reduced, and the cost is reduced.
Drawings
Fig. 1 is a schematic diagram of a symmetrical fully-connected power combining network.
Fig. 2 is a schematic diagram of an asymmetric fully connected power combining network.
Fig. 3 is a schematic diagram of phase mismatch alignment between the various paths.
Detailed Description
The invention provides a multi-beam phased array miniaturized asymmetric power synthesis network structure and a calibration method, and the structure and the calibration method are described below with reference to the accompanying drawings.
Fig. 2 is a schematic diagram of an asymmetric fully connected power combining network. The miniaturized asymmetric power synthesis network comprises 16 paths of inputs and 4 paths of outputs, wherein each 4 paths of power synthesis to 1 path of power synthesis adopts an asymmetric structure, and the middle of the power synthesis network is connected together by adopting a coupling transmission line; on the chip, four sets of coupled transmission lines are arranged horizontally.
On the chip, the four groups of coupling transmission lines are horizontally arranged, namely, 16 paths of inputs are divided into one group every 4 paths, and 1 path of inputs in each group is correspondingly connected with 1 path of outputs of 4 paths; namely, a certain 1-way input in the 1 st-4 th-way inputs is correspondingly connected with a certain 1-way output of the 4-way outputs through a coupling transmission line; some 1 way input in 5 th to 8 th way inputs is connected with some 1 way output of 4 way outputs correspondingly through coupling transmission line; some 1 way input in 9 th to 12 way inputs is connected with some 1 way output of 4 way output through coupling transmission line and some 1 way input in 13 th to 16 way inputs is connected with some 1 way output of 4 way output through coupling transmission line.
A calibration method for a multi-beam phased array miniaturized asymmetric power synthesis network comprises the following steps: the method comprises the following steps:
1) Establishing a phase mismatch calibration device between all paths, as shown in a phase mismatch calibration schematic diagram between all paths in FIG. 3, wherein phase shifters are connected with a variable gain amplifier in parallel in the figure, and then 4 paths of phase shifters are connected in parallel, wherein input ends of the four phase shifters of the 1# phase shifter, the 2# phase shifter, the 3# phase shifter and the 4# phase shifter are respectively connected through coupling transmission lines, a buffer stage is connected between a first path of variable gain amplifier and a second path of variable gain amplifier, and input power is added to the input ends of the buffer stage; the output ends of the variable gain amplifiers of the 1 st path and the 2 nd path are connected, and the output ends of the variable gain amplifiers of the 3 rd path and the 4 th path are connected, and then the variable gain amplifiers of the 1 st path and the 2 nd path are connected with a power synthesizer and a power tester;
2) Only opening the 1 st input path and the 2 nd input path, injecting certain power, observing a voltage value given by the power detector at the output end, setting a control code of the 1 st phase shifter of the 1 st input path to zero, and adjusting the 2 nd phase shifter in the 2 nd input path to ensure that the output voltage value of the power detector reaches the maximum; when the two paths of signals are overlapped in phase, the output power is maximum, and the phases of the 1 st path of input and the 2 nd path of input are considered to be aligned, and the phase shift value in the 2 nd path of input is the offset code;
3) Only opening the 1 st input path and the 2 nd input path, and obtaining a phase shifter bias code in the 4 th input path in the same way as the step 2);
4) Opening all 16 paths of input channels, injecting certain power, and simultaneously adjusting a 3# phase shifter and a 4# phase shifter on the basis of the bias code to ensure that the output voltage value of a power detector reaches the maximum; at this time, the phase calibration can be considered to be completed, and the phase shift value of each input path is the bias code of each phase shifter;
5) After calibration is completed, each phase shifter obtains a group of bias codes; when beam direction control is performed, a beam direction control code is superimposed on the offset code; since the beam direction is only related to the adjacent phase shift between channels, the bias code does not affect the control of the beam direction.

Claims (2)

1. A multi-beam phased array miniaturized asymmetric power synthesis network structure, the miniaturized asymmetric power synthesis network comprising 16 inputs and 4 outputs; the power synthesis method is characterized in that power synthesis of 1 output in 4 outputs is of an asymmetric structure, and the middle of the power synthesis is connected together by adopting a coupling transmission line; on the chip, four groups of coupling transmission lines are horizontally arranged; dividing 16 paths of input into a group every 4 paths, wherein 1 path of input in each group is correspondingly connected with 1 path of input of 4 paths; namely, a certain 1-way input in the 1 st-4 th-way inputs is correspondingly connected with a certain 1-way output of the 4-way outputs through a first coupling transmission line; some 1 way input in 5 th to 8 th inputs is correspondingly connected with some 1 way output of 4 way outputs through the second coupling transmission line; some 1 way input in 9 th to 12 way inputs is connected with some 1 way output of 4 way outputs through the third coupling transmission line correspondingly, and some 1 way input in 13 th to 16 way inputs is connected with some 1 way output of 4 way outputs through the fourth coupling transmission line correspondingly.
2. A multi-beam phased array miniaturized asymmetric power combining network architecture calibration method as claimed in claim 1: the method comprises the following steps:
1) Establishing a phase mismatch calibration device among all paths, connecting the phase shifters with the variable gain amplifier in parallel, and connecting the phase shifters with 4 paths, wherein the input ends of the four phase shifters are respectively connected through coupling transmission lines, a buffer stage is connected between a first path and a second path, and input power is added to the input end of the buffer stage; the output ends of the variable gain amplifiers of the 1 st path and the 2 nd path are connected, and the output ends of the variable gain amplifiers of the 3 rd path and the 4 th path are connected, and then the variable gain amplifiers of the 1 st path and the 2 nd path are connected with a power synthesizer and a power tester;
2) Only opening the 1 st input path and the 2 nd input path, injecting certain power, observing a voltage value given by the power detector at the output end, setting a control code of the 1 st phase shifter of the 1 st input path to zero, and adjusting the 2 nd phase shifter in the 2 nd input path to ensure that the output voltage value of the power detector reaches the maximum; when the two paths of signals are overlapped in phase, the output power is maximum, and the phases of the 1 st path of input and the 2 nd path of input are considered to be aligned, and the phase shift value in the 2 nd path of input is the offset code;
3) Only opening the 1 st input path and the 2 nd input path, and obtaining a phase shifter bias code in the 4 th input path in the same way as the step 2);
4) Opening all 16 paths of input channels, injecting certain power, and simultaneously adjusting a 3# phase shifter and a 4# phase shifter on the basis of the bias code to ensure that the output voltage value of a power detector reaches the maximum; at this time, the phase calibration can be considered to be completed, and the phase shift value of each input path is the bias code of each phase shifter;
5) After calibration is completed, each phase shifter obtains a group of bias codes; when beam direction control is performed, a beam direction control code is superimposed on the offset code; since the beam direction is only related to the adjacent phase shift between channels, the bias code does not affect the control of the beam direction.
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CN114389663B (en) * 2021-12-08 2024-07-09 清华大学 Phased array beam forming network
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CN1204874A (en) * 1997-06-30 1999-01-13 索尼国际(欧洲)股份有限公司 Wide band printed phased array antenna for microwave and mm-wave applications
CN101578737A (en) * 2006-11-10 2009-11-11 昆特尔科技有限公司 Phased array antenna system with electrical tilt control
CN107785665A (en) * 2014-06-30 2018-03-09 华为技术有限公司 A kind of row phased array antenna of mixed structure double frequency dualbeam three
CN110114937A (en) * 2016-12-27 2019-08-09 雷声公司 Circuit and technology for no via hole beam-shaper
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