CN112187394B - Method and system for generating SFD time stamp based on Ethernet synchronous code - Google Patents
Method and system for generating SFD time stamp based on Ethernet synchronous code Download PDFInfo
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Abstract
The invention relates to a method for generating SFD based on Ethernet synchronous codeA method and a system for inter-stamping belong to the technical field of communication and solve the problem of uncertainty caused by delay introduced by an Ethernet physical layer; measuring the distance MII_DIS between a frame start delimiter SFD of a PTP packet head on an MII interface and a synchronous code block AM; determining a Serdes channel in which a frame start delimiter SFD is positioned; the Serdes channel is one of a plurality of channels included on the Serdes interface; converting the distance MII_DIS into a distance SD_DIS1 between a start of frame delimiter SFD on the Serdes channel and a synchronous code block AM; determining that data in a plurality of channels of the Serdes interface are interleaved according to bits to obtain a final distance SD_DIS; detecting the time TS of a synchronization code block AM on a Serdes interface AM The method comprises the steps of carrying out a first treatment on the surface of the According to time TS AM And the distance sd_dis to obtain the start of frame delimiter SFD timestamp TS on the Serdes interface SFD . The time stamp generated by the invention overcomes the uncertainty brought by the time stamp introduced by the PCS and the FEC core, so that the time stamp is more accurate.
Description
Technical Field
The invention relates to the technical field of communication, in particular to a method and a system for generating an SFD time stamp based on an Ethernet synchronous code.
Background
Today's society has been moving into the information age, with the widespread popularity of distributed networks and the development of next generation communication technologies (5G networks), many devices and applications will have a stringent requirement for clock synchronization, and it is more necessary to provide a more accurate clock to devices in a network system to achieve high-precision time synchronization. IEEE1588 is a network time synchronization protocol by which simple clock synchronization of master and slave devices can be achieved, but it is difficult to improve accuracy to the order of nanoseconds. Because of the complexity of the design implementation of the ethernet physical layer, PCS and FEC can introduce uncertain time delays such as insertion of a synchronous data block AM (alignment marker), check code production of FEC, transmission, asynchronous FIFO, etc. The delays introduced by these designs all affect the accuracy of the measurement.
Disclosure of Invention
In view of the above analysis, the present invention aims to disclose a method and a system for generating an SFD timestamp based on an ethernet synchronization code, which solve the problem of uncertainty caused by delay introduced by an ethernet physical layer.
The invention discloses a method for generating SFD time stamp based on Ethernet synchronous code, comprising the following steps:
measuring the distance MII_DIS between a frame start delimiter SFD of a PTP packet head on an MII interface and a synchronous code block AM;
determining a Serdes channel in which a frame start delimiter SFD is positioned; the Serdes channel is one of a plurality of channels included on a Serdes interface;
converting the distance MII_DIS into a distance SD_DIS1 between a frame start delimiter SFD on the Serdes channel and a synchronous code block AM;
determining a final distance sd_dis of the Serdes interface, wherein sd_dis=n×sd_dis1; the final data on the Serdes interface is obtained by interleaving data in the channels according to bits; n is the interleaving ratio of the Serdes interface;
detecting the time TS of a synchronization code block AM on a Serdes interface AM ；
According to the time TS AM And said distance sd_dis gets a start of frame delimiter SFD timestamp TS on the Serdes interface SFD The method comprises the steps of carrying out a first treatment on the surface of the Wherein TS SFD ＝TS AM +SD_DIS×UI, which is the time required per transmission of one Serdes symbol on a Serdes interface.
Further, the measurement of the distance mii_dis is performed in the PCS layer, and measured in the transmission direction or the reception direction;
in the transmission direction, the measurement of the distance mii_dis includes:
the method comprises the steps of finding a frame start delimiter SFD at an MII side, carrying out SFD indication identification, and transmitting the SFD indication identification to an AM insertion module of a PCS layer along with data;
inserting a synchronous code block AM in an AM insertion module to perform synchronous code AM indication identification;
measuring clock periods of the phase difference between the AM indication mark and the SFD indication mark; converting the phase-difference clock period to a distance mii_dis;
in the receiving direction, the measurement of the distance mii_dis includes:
finding a synchronous code block AM in an AM remove module of the PCS layer, and carrying out synchronous code AM indication identification; transmitting the AM indication identifier to the MII along with the data;
when the SFD is found on the MII interface, SFD indication identification is carried out;
measuring clock periods of the SFD indication mark and the AM indication mark which are different in the MII interface; the clock period of the phase difference is converted to a distance MII DIS.
Further, the distance mii_dis on the MII interface of the ethernet in the 25G-400G rate range is:
25G：MII_DIS＝(Nt–1)×64+MII_OFFSET×32–8；
40G/50G：MII_DIS＝(Nt–1)×64+MII_OFFSET×64–8；
100G：MII_DIS＝(Nt–1)×2×64+MII_OFFSET×64–8；
200G：MII_DIS＝(Nt–1)×4×64+MII_OFFSET×64–8；
400G：MII_DIS＝(Nt–1)×8×64+MII_OFFSET×64–8；
nt is the OFFSET of the start bit of the frame start delimiter SFD on the MII interface of 64-bit width, where the AM indication identifier and the SFD indication identifier differ by a clock period.
Further, in the ethernet network including RS-FEC, determining the Serdes channel where the start of frame delimiter SFD is located includes:
according to only one Serdes channel, performing distance conversion, and calculating a distance caused by the number of bits CW_N of the FEC code words and a distance LEFT_257B caused by the bit number of less than one complete FEC code word;
according to the formula sd_lane= (left_257 b%10= 0)? (LEFT_257B/10)% R (LEFT_257B-
10+1)% R; judging the number of the frame start delimiter SFD falling on the Serdes channel; where R is the number of Serdes LANEs, sd_lane is the number of Serdes LANEs, which starts from 1, and SFD falls on the last LANE when sd_lane=0.
Further, each FEC codeword comprises an mxn-bit data block, the number of bits of the FEC codeword, cw_n=mii_dis/m/N, retains the whole bits of cw_n;
distance left_257 b=tc_nx257+ (left_64b-4×64×tc_n) + (left_64b%256= 0;
where left_64b=mii_dis-cw_n×m×n; tc_n=left_64b/4/64.
Further, a distance sd_dis1 between a start of frame delimiter SFD on the Serdes channel and a synchronization code block AM;
SD_DIS1＝CW_DIS1+LEFT_DIS1；
where cw_dis1=cw_n×l/R; left_dis1= (left_257B/10/R) ×10 detects the first pattern+left_257b%10 of the sync block AM on the Serdes interface;
l is the bit number of the FEC codeword, and R is the Serdes channel number.
Further, in a 100G/40G AUI mode of the Ethernet without RS-FEC, a physical layer interface of the 40G AUI mode is provided with 4 PCS channels, and the 100G AUI mode is provided with 20 PCS channels;
when the distance conversion is carried out, the data blocks are distributed to 4 or 20 PCS channels; determining that the SFD falls on a certain PCS channel according to the following formula;
40G：PCS_LANE＝MII_DIS％64＝＝0？(MII_DIS/64)％4:(MII_DIS/64+1)％4；
100G：PCS_LANE＝MII_DIS％64＝＝0？(MII_DIS/64)％20:(MII_DIS/64+1)％20；
the distance sd_dis between the SFD and the sync code block on the PCS channel containing the SFD is pcs_dis:
40G：
PCS_DIS＝MII_DIS/(64×4)×66+(MII_DIS％(64×4)＝＝00:(MII_DIS％64？66:MII_DIS％64))；
100G：
PCS_DIS＝MII_DIS/(64×20)×66+(MII_DIS％(64×20)＝＝00:(MII_DIS％64？66:MII_DIS％64))；
further, the final distance sd_dis is:
100GAUI4：SD_DIS＝PCS_DIS×5–(PCS_LANE％5＝＝00:5-PCS_LANE％5)；
100GAUI10：SD_DIS＝PCS_DIS×2–(PCS_LANE％2＝＝00:2-PCS_LANE％2)；
the 100G AUI4 interweaves 5 pieces of pcs lane data to a serdes lane in a round-robin mode; 100G AUI10 interleaves 2 pieces of pcs lane data onto one serdes lane in a round-robin fashion.
Further, detecting the first pattern of the synchronous code block AM on the Serdes interface, and recording the time TS of the current synchronous code block AM when the lowest bit of the first pattern appears on the Serdes interface AM The method comprises the steps of carrying out a first treatment on the surface of the SD_Rx [ k ] at a position where pattern of the sync code block AM appears on the Serdes interface]Bit time; correcting the time of the synchronous code block AM to TS AM +k×UI。
The invention also discloses a system for generating SFD time stamp according to the method, which comprises the following steps:
the distance measurement module is used for measuring the distance MII_DIS between the frame start delimiter SFD of the PTP packet head on the MII interface and the synchronous code block AM;
the distance conversion module is used for converting the distance MII_DIS into a distance SD_DIS between a frame start delimiter SFD on the Serdes interface and the synchronous code block AM;
specifically, in the distance conversion module, determining a Serdes channel in which the frame start delimiter SFD is located; the Serdes channel is one of a plurality of channels included on a Serdes interface; converting the distance MII_DIS into a distance SD_DIS1 between a frame start delimiter SFD on the Serdes channel and a synchronous code block AM; determining a final distance sd_dis of the Serdes interface, wherein sd_dis=n×sd_dis1; the final data on the Serdes interface is obtained by interleaving data in the channels according to bits; n is the interleaving ratio of the Serdes interface;
a time detection module for detecting the time TS of the synchronous code block AM on the Serdes interface AM ；
A time stamp calculation module for calculating a time TS AM And the distance sd_dis to obtain the start of frame delimiter SFD timestamp TS on the Serdes interface SFD The method comprises the following steps: TS (transport stream) SFD ＝TS AM +SD_DIS×UI, where UI is the time required for each Serdes symbol to be transmitted over the Serdes interface.
The invention can realize at least one of the following beneficial effects:
the present invention addresses the delays that data may introduce through the physical layer PCS/FEC, including uncertainties in several aspects,
periodically inserting AM or CM (Alignment/coding Marker);
inserted check symbol (parity symbol) of RS-FEC;
skew and skew variation between multiple Serdes lanes;
compensating the clock frequency;
other factors (for 100G/200G/400G, the location of the initial SFD is not necessarily aligned to the first Serdes lane0; the transmission module; and the delay introduced by the FEC encoder/decoder buffer, etc.);
the invention can eliminate uncertainty of time stamp generation introduced by PCS and FEC cores;
and compensating the deviation of sampling clock stamps brought by crossing clock domains, so that the clock sampling delay of a compensated loop is reduced by 1/2.
Drawings
The drawings are only for purposes of illustrating particular embodiments and are not to be construed as limiting the invention, like reference numerals being used to refer to like parts throughout the several views.
FIG. 1 is a schematic diagram of a system connection for generating Ethernet high-precision time stamps in the present embodiment;
fig. 2 is a flowchart of an ethernet high-precision timestamp generation method in the present embodiment;
fig. 3 is a schematic diagram of clock cycle calculation principle of phase difference between AM and SFD in the transmission direction in the present embodiment;
fig. 4 is a schematic diagram of clock cycle calculation principle of phase difference between the receiving directions AM and SFD in the present embodiment;
fig. 5 is a diagram showing an example of the locations where the 40G-400G ethernet SFD appears over the MII interface in the present embodiment;
fig. 6 is a diagram showing an example of a location where the 25G ethernet SFD appears over the MII interface in the present embodiment;
FIG. 7 is a diagram of compensation cross-clock sampling in the present embodiment;
fig. 8 is a schematic diagram showing the connection of the ethernet high-precision timestamp generating system according to the present embodiment.
Detailed Description
Preferred embodiments of the present invention are described in detail below with reference to the attached drawing figures, which form a part of the present application and, together with the embodiments of the present invention, serve to explain the principles of the invention.
The PCS and FEC of the ethernet physical layer PHY may introduce an uncertainty delay, and in order to eliminate the uncertainty delay, the closer the system generates the timestamp to the physical layer, the more accurate. The start of frame delimiter SFD (start frame delimiter) of the PTP frame is converted from its appearance on the MII side to its position on the Serdes interface, thereby achieving the purpose of identifying the SFD of the PTP frame at the Serdes interface of the physical layer and generating a time stamp for eliminating the delay. As shown in fig. 1, the uppermost physical layer PHY is connected with the RS layer by an MII interface, and the lowermost PHY is by a Serdes interface.
The start of frame delimiter SFD is scrambled and possibly assigned to multiple Serdes lanes as it passes through the PCS, so it is difficult to identify the original frame on the Serdes interface. The pattern of the sync block AM (alignment marker) is fixed, however, it occurs periodically and does not participate in the scrambling process, so the sync block AM can be found on the Serdes interface. Thus, the synchronization code block AM can be used as a reference point at the Serdes interface, and once the time when the synchronization code block AM leaves or reaches the Serdes interface and the distance between AM and SFD are obtained, the time when the SFD leaves or reaches the Serdes interface can be calculated.
Since the SFD is difficult to find on the Serdes interface, it is difficult to measure the distance between the SFD and the AM even if the time is obtained that the start point of the synchronization code block AM is on the Serdes interface. The method disclosed by the embodiment solves the problem by measuring the distance between the SFD and the AM at the MII interface and then calculating the distance between the SFD and the AM on the Serdes interface by an algorithm, and generates an Ethernet High-precision time stamp HETS (High-accurate Ethernet Time Stamping).
The embodiment discloses a method for generating an SFD timestamp based on an Ethernet synchronization code, which comprises the following steps as shown in fig. 2:
step S1, measuring the distance MII_DIS between a frame start delimiter SFD of a PTP packet head on an MII interface and a synchronous code block AM;
step S2, converting the distance MII_DIS into a distance SD_DIS between a frame start delimiter SFD on a Serdes interface and a synchronous code block AM;
specifically, determining a Serdes channel in which a frame start delimiter SFD is located; the Serdes channel is one of a plurality of channels included on a Serdes interface;
converting the distance MII_DIS into a distance SD_DIS1 between a frame start delimiter SFD on the Serdes channel and a synchronous code block AM;
determining a final distance sd_dis of the Serdes interface, wherein sd_dis=n×sd_dis1; the final data on the Serdes interface is obtained by interleaving the plurality of Serdes channel data according to bits; n is the interleaving ratio of the Serdes interface;
step S3, detecting the time TS of the synchronous code block AM on the Serdes interface AM ；
Step S4, according to time TS AM And the distance sd_dis to obtain the start of frame delimiter SFD timestamp TS on the Serdes interface SFD The method comprises the following steps: TS (transport stream) SFD ＝TS AM +SD_DIS×UI, where UI is the time required for each Serdes symbol to be transmitted over the Serdes interface.
Specifically, the measurement of the distance mii_dis includes measurement in a transmission direction and measurement in a reception direction;
in the transmission direction, as shown in fig. 3, the PCS layer data flows through a 64/66B encoder (encoder), a scrambler (scrambler), a synchronization code block insertion module (Am insertion), a decoder (transcoder), a transmission (gecarbox), and the like. There will be a delay of about 2 clock cycles in each module. So in order to measure the distance between SFD and AM more accurately, when MII finds SFD, it will send the SFD indication mark to the downstream module along with data beat to the AM insertion module. A fixed pattern of synchronization code blocks (AM pattern) are inserted into the data in the AM insertion module, and an AM indication identifier is given. Since the indication signal of the SFD is also transferred to the AM insertion module, we can measure the clock period difference between the AM indication and the SFD indication in the same reference module. And reconverts to their distance over the MII interface by clock cycles.
In the receiving direction, as shown in fig. 4, the synchronization code block AM is usually removed before reaching the MII interface, but to know the relative positional relationship of SFD and AM, the AM pattern must be preserved until the MII interface. Therefore, in this embodiment, the AM remote module finds the synchronization code block AM, performs the synchronization code AM indication identifier, and transmits the AM indication identifier to the interface from the downstream module to the MII along with the data. Because the SFD is a fixed pattern on the interface of the MII, it is easier to find. When the SFD of the PTP is found on the MII interface, SFD indication identification is carried out, and the SFD indication and the AM indication are measured for clock periods which are different in the MII interface; the clock period of the phase difference is converted to a distance MII DIS.
The preamble (preamble) and SFD are transmitted consecutively in octets (octets) on the MII lane, as specified in the 802.3 protocol. For 40G-400G, the first preamble octet is replaced with a start control and aligned to MII lane0. The preamble is transmitted over Lane1 through Lane2, and Lane7 transmits SFD as shown in FIG. 5. So the location where the SFD appears above the MII interface would be on MII lane 7.
For 25G, there are 4 lanes on the MII interface as in FIG. 6, data transfer on the MII interface is similar to 40G-400G, and SFD would appear on lane 3.
Only one MII lane will be occupied in the 25G/40G/50G mode, so SFD will only appear on the currently transmitted MII lane. But 100G/200G/400G would occupy more than one MII lane, so the location of the SFD may appear on other lanes. It is therefore necessary to calculate the offset of the SFD occurring at the MII and calculate the distance of the SFD according to different rate modes. The following table gives one possible example of the presence of SFD on different MII lanes from 25G to 400G.
Assume that the AM indication identifier and the SFD indication identifier differ by a clock period of Nt on the MII interface, and that the OFFSET of the start bit of the SFD on the MII port which is 64-bit wide is MII_OFFSET. The distance mii_dis of SFD and AM over the MII interface for the 25G-400G rate is then:
25G：MII_DIS＝(Nt–1)×64+MII_OFFSET×32–8；
40G/50G：MII_DIS＝(Nt–1)×64+MII_OFFSET×64–8；
100G：MII_DIS＝(Nt–1)×2×64+MII_OFFSET×64–8；
200G：MII_DIS＝(Nt–1)×4×64+MII_OFFSET×64–8；
400G：MII_DIS＝(Nt–1)×8×64+MII_OFFSET×64–8。
since the first bit of SFD always appears on either the 3 rd or 7 th byte, 8 is subtracted from the MII_DIS calculation on the MII_OFFSET full of MII port to ensure accuracy of the distance MII_DIS.
In the distance conversion of step S2, the data flows in the MII interface to the Serdes interface through the PCS/FEC function modules, which introduce uncertain delays as follows:
the 1.64/66B encoder adds 2 bits to the 64-bit MII block data;
transcoding will delete 7 bits in every 4 66B blocks;
the parity bits of RS codes, RS (528,514) will increase 140 bits, RS (544,514) will increase 300 bits, RS (257,272) will increase 150 bits;
serdes Lane number. Because SFDs may be assigned to any one of the serdes lanes, it is necessary to know on which lane the start of the SFD is located;
5. ethernet rate. At different rate modes, the data will have different interleaving, multiplexing, and allocation modes, which will affect where the SFD start bit appears on the Serdes lane.
The present embodiment compensates back for the uncertainty mentioned above, and estimates the distance between the SFD and AM at MII to the SFD position on the Serdes channel.
Specifically, in the Ethernet including RS-FEC, the distance MII_DIS is converted into the distance SD_DIS:
SD_DIS＝CW_DIS+LEFT_DIS；
wherein CW_DIS is the distance caused by the whole number of bits of the number of FEC code words in the distance conversion process; LEFT DIS is the distance caused by the number of bits of less than one complete FEC codeword in the distance conversion process.
Further, the number of FEC codewords is cw_n; each FEC codeword contains an mxn-bit data block, then cw_n=mii_dis/m/N, reserving the whole number of bits of cw_n;
when data is transmitted over only one Serdes channel, the distance CW_DIS is: cw_dis=cw_n×l; l is the bit number of the FEC codeword.
Further, the insertion position of the synchronization code block AM is at the head of the FEC codeword, where the bit number left_64b of less than one complete FEC codeword is: left_64b=mii_dis-cw_nxm×n;
the LEFT_64B comprises 257-bit transmission code data blocks, each 257-bit transmission code data block comprises 4X 64-bit data blocks, the number of the 257-bit transmission code data blocks TC_N=LEFT_64B/4/64 in the LEFT_64B, and the integer digits of TC_N are reserved;
distance LEFT 257B is calculated from the number of 257-bit transport data blocks:
LEFT_257B＝TC_N×257+(LEFT_64B–4×64×TC_N)+ (LEFT_64B％256＝＝00:1)；
LEFT dis=left 257B when data is transferred over only one Serdes lane.
Further, where the Serdes interface includes a plurality of Serdes lanes,
1) According to only one Serdes channel, performing distance conversion, and calculating a distance caused by the number of bits CW_N of the FEC code words and a distance LEFT_257B caused by the number of bits of less than one complete FEC code word;
2) Judging that the frame start delimiter SFD falls on a certain Serdes channel of the Serdes interface according to the number of Serdes channels and the distance LEFT-257B;
at the Serdes interface of 50G-100G ethernet, according to the formula sd_lane= (left_257 b%10+=0)? (LEFT_257B/10)% R (LEFT_257B/10+1)% R; judging the number of the frame start delimiter SFD falling on the Serdes channel; where R is the number of Serdes LANEs, sd_lane is the number of Serdes LANEs, which starts from 1, and SFD falls on the last LANE when sd_lane=0.
3) On the Serdes channel, calculating CW_DIS and LEFT_DIS according to the coding format of the RS-FEC;
CW_DIS＝CW_N×L/R；
LEFT_DIS＝(LEFT_257B/10/R)×10+LEFT_257B％10；
where L is the bit number of the FEC codeword and R is the number of channels of Serdes.
Specifically, in a 100G/40G AUI mode without RS-FEC, a 40G AUI mode physical layer interface has 4 PCS channels, and a 100G AUI mode has 20 PCS channels;
when the distance conversion is carried out, the data blocks are distributed to 4 or 20 PCS channels; determining that the SFD falls on a certain PCS channel according to the following formula;
40G：PCS_LANE＝MII_DIS％64＝＝0？(MII_DIS/64)％4:(MII_DIS/64+1)％4；
100G：PCS_LANE＝MII_DIS％64＝＝0？(MII_DIS/64)％20:(MII_DIS/64+1)％20；
the distance sd_dis between the SFD and the sync code block on the PCS channel containing the SFD is pcs_dis:
40G：
PCS_DIS＝MII_DIS/(64×4)×66+(MII_DIS％(64×4)＝＝00:(MII_DIS％64？66:MII_DIS％64))；
100G：
PCS_DIS＝MII_DIS/(64×20)×66+(MII_DIS％(64×20)＝＝00:(MII_DIS％64？66:MII_DIS％64))。
the following section will specifically describe a distance conversion algorithm in the ethernet 25G-400G rate mode.
1. 25G distance conversion
The 25G inserted sync block CM (Codeword Marker) is the same form and function as the other rate sync block AM, except for the naming.
Let the number of FEC codewids of the phase difference between SFD and sync block CM be cw_n. Each codewiord contains 80 x 64-bit data blocks, then cw_n=mii_dis/64/80, reserving the whole digits of cw_n.
Because the insertion position of the CM is always at the head of the FEC codec, the bit number left_64b of less than one complete codec is: left_64b=mii_dis-cw_nx80×64.
Each 257-bit transport code data block contains 4 x 64-bit data blocks, the number of 257-bit transport code data blocks tc_n: for tc_n=left_64b/4/64, the integer digits of tc_n are reserved.
The number of bits left_257B remaining after the transfer is: left_257 b=tc_n×257+ (left_64b-4×64×tc_n) + (left_64b%256= 00:1), the last 1 bit in the formula is because of the 1 bit overhead per new franscode.
Since only one Serdes channel is used at the 25GBASE-R rate, the code distance CW_DIS from CM is: cw_dis=cw_n×5280.
The remaining distance left_dis other than cw_dis is: left_dis=left_257B.
Based on the above calculation result, the distance sd_dis between SFD and CM on the Serdes interface is finally: sd_dis=cw_dis+left_dis.
2. 50G distance conversion (calculated by default with RS-FEC (544, 514) and RS (528, 514))
Let the number of FEC codewids that differ between SFD and AM be cw_n. Each codewiord contains 80 x 64-bit data blocks, cw_n=mii_dis/64/80, reserving the whole digits of cw_n. Under the FEC-RS (272, 257) algorithm, each codewid contains 40×64-bit data blocks, cw_n=mii_dis/64/40, reserving the whole digits of cw_n.
Because the insertion position of the AM is always at the head of the FEC codec, the bit number left_64b of less than one complete codec is: left_64b=mii_dis-cw_n×80×64 under FEC-RS (272, 257) algorithm, left_64b=mii_dis-cw_n×40×64.
Each 257-bit transport code data block contains 4 x 64-bit data blocks, the number of 257-bit transport code data blocks tc_n: for tc_n=left_64b/4/64, the integer digits of tc_n are reserved.
The number of bits left_257B remaining after the transfer is: left_257 b=tc_n×257+ (left_64b-4×64×tc_n) + (left_64b%256= 00:1), the last 1 bit in the formula is because of the 1 bit overhead per new franscode.
50G BASE-R2 has 2 serdes lanes, and data is distributed to two serdes lanes in the form of a round-robin in 10-bit FEC symbol units. The Serdes Lane where SFD would occur is
SD_LANE,SD_LANE＝(LEFT_257B％10＝＝0)？(LEFT_257B/10)％2: (LEFT_257B/10+1)％2。
It should be noted that sd_lane starts from 1, if the calculation result of sd_lane is 0, it means that SFD falls on the last LANE.
On a certain Serdes lane, the SFD of the different FEC-RS algorithms differs from AM by a distance CW_DIS of codeword of:
RS(544,514):CW_DIS＝CW_N×5440/2；
RS(528,514):CW_DIS＝CW_N×5280/2；
RS(272,257):CW_DIS＝CW_N×2720/2。
the remaining distance left_dis other than cw_dis is: left_dis= (left_257B/20) ×10+left_257b%10;
based on the above calculation result, the distance sd_dis between SFD and CM is equal to the sum of the distances sd_dis: sd_dis=cw_dis+left_dis.
In 50G BASE-R1 mode, 2 Serdes Lane data will be bit interleaved into 1 Serdes Lane, so the final SD_DIS is SD_DIS=2× (CW_DIS+LEFT_DIS)
3. 100G distance conversion (calculated by default with RS-FEC (544, 514) and RS (528, 514))
Let the number of FEC codewids that differ between SFD and AM be cw_n. Each codewiord contains 80 x 64-bit data blocks, cw_n=mii_dis/64/80, reserving the whole digits of cw_n. Under the FEC-RS (272, 257) algorithm, each codewid contains 40×64-bit data blocks, cw_n=mii_dis/64/40, reserving the whole digits of cw_n.
Because the insertion position of the AM is always at the head of the FEC codec, the bit number left_64b of less than one complete codec is: left_64b=mii_dis-cw_nx80x64 under FEC-RS (272, 257) algorithm, left_64b=mii_dis-cw_nx40x64;
each 257-bit transport code data block contains 4 x 64-bit data blocks, the number of 257-bit transport code data blocks tc_n: for tc_n=left_64b/4/64, the integer digits of tc_n are reserved.
The number of bits left_257B remaining after the transfer is: left_257 b=tc_nx257+ (left_64b-4×64×tc_n) + (left_64b%256= 00:1);
the last 1 bit added to the formula is because each new franscode is1 bit more overhead.
100G BASE-KR4 has 4 Serdes lanes, and data is distributed to 4 Serdes lanes in 10-bit FEC symbols, round-robin fashion. SFD will occur at Serdes LANE as d_lane= (left_257 b%10+=0)? (LEFT_257B/10)% 4 (LEFT_257B/10+1)% 4S.
It should be noted that sd_lane starts from 1, if the calculation result of sd_lane is 0, it means that SFD falls on the last LANE.
On a certain Serdes lane, the SFD of the different FEC-RS algorithms differs from AM by a distance CW_DIS of codeword of:
RS(544,514):CW_DIS＝CW_N×5440/4；
RS(528,514):CW_DIS＝CW_N×5280/4；
RS(272,257):CW_DIS＝CW_N×2720/4。
the remaining distance left_dis other than cw_dis is: left_dis= (left_257B/40) ×10+left_257b%10;
based on the above calculation result, the distance sd_dis between SFD and CM is equal to the sum of the distances sd_dis: sd_dis=cw_dis+left_dis.
In 100G BASE-KR2/CR2 mode, 4 Serdes lanes of data are interleaved bit-wise to 2 Serdes lanes, so the final sd_dis is sd_dis=2× (cw_dis+left_dis).
4. 200G/400G distance conversion (calculated by default with RS-FEC (544, 514))
Let the number of FEC codes that differ between SFD and AM be cw2_n. Every 2 codewid contains 2×80×64-bit data blocks, cw2_n=mii_dis/64/80/2, reserving the whole digits of cw2_n. Under the FEC-RS (272, 257) algorithm, every 2 codewid contains 2×40×64-bit data blocks, cw2_n=mii_dis/64/40/2, reserving the whole digits of cw2_n.
Because the insertion position of AM is always at the head of FEC codec, the bit number left_64b of less than 2 complete codewords is: left_64b=mii_dis-cw2_nx80x64×2 under FEC-RS (272, 257) algorithm, left_64b=mii_dis-cw2_nx40×64×2.
Each 257-bit transport code data block contains 4 x 64-bit data blocks, the number of 257-bit transport code data blocks tc_n: for tc_n=left_64b/4/64, the integer digits of tc_n are reserved.
The number of bits left_257B remaining after the transfer is: left_257 b=tc_n×257+ (left_64b-4×64×tc_n) + (left_64b%256= 00:1), the last 1 bit in the formula is because of the 1 bit overhead per new franscode.
200G and 400G data are distributed to 8 (200G) and 16 (400G) servers in the form of round-robin in units of 10-bit FEC symbols. The Serdes LANE of which group the SFD will occur is LANE_DIST_N,
200G:LANE_DIST_N＝(LEFT_257B％80＝＝0)？LEFT_257B/80: LEFT_257B/80+1；
400G:LANE_DIST_N＝(LEFT_257B％160＝＝0)？LEFT_257B/160: LEFT_257B/160+1；
the SFD IS assumed to fall on codewordA when is_cwa= 1. Is_cwa= 0, and sfd falls on codewidb. Is_cwa IS calculated as follows: is_cwa= (left_ 257B%20>10or LEFT_257B%20 = 0)? 0:1;
the Serdes Lane where SFD will occur is SD_LANE, which is calculated by the steps of: firstly, obtaining the number of the serdes LANE groups where the SFD is located from LANE_DIST_N, and if the number of the serdes LANE groups is in an odd number group (serdes LANE distribution is arranged according to the form of coded ABAB), solving the remainder of the number of the serdes LANE groups to calculate the serdes LANE where the SFD is located. If in even groups (serdes lane distribution arranged in terms of coded BABA): when IS_CWA IS1, the remainder IS calculated for the number of serdes Lane, and the serdes Lane+1 where SFD IS located IS calculated. When IS_CWA IS 0, the remainder IS calculated for the number of serdes Lane, and the serdes Lane-1 where SFD IS located IS calculated. The distribution of Serdes Lane is calculated in units of symbols (10 bits), and all (LEFT_257B/10) are calculated by adding one symbol to less than 1 symbol (LEFT_257B/10+1).
The specific formula is as follows:
200G:SD_LANE＝
(LANE_DIST_N％2＝＝1)？
((LEFT_257B％10＝＝0)？(LEFT_257B/10)％8:(LEFT_257B/10+1)％8):
((LEFT_257B％10＝＝0)？(IS_CWA？(LEFT_257B/10)％8+1:
((LEFT_257B％160＝＝0)？8-1:(LEFT_257B/10)％8–1)):
(IS_CWA？(LEFT_257B/10+1)％8+1:
(((LEFT_257B/10+1)％16＝＝08-1:(LEFT_257B/10+1)％8-1)))；
400G:SD_LANE＝
(LANE_DIST_N％2＝＝1)？
((LEFT_257B％10＝＝0)？(LEFT_257B/10)％16:(LEFT_257B/10+1)％16):
((LEFT_257B％10＝＝0)？(IS_CWA？(LEFT_257B/10)％16+1:
((LEFT_257B％320＝＝0)？16-1:(LEFT_257B/10)％16–1)):
(IS_CWA？(LEFT_257B/10+1)％16+1:
(((LEFT_257B/10+1)％32＝＝016-1:(LEFT_257B/10+1)％16-1)))；
it should be noted that sd_lane starts from 1, if the calculation result of sd_lane is 0, it means that SFD falls on the last LANE.
On a certain Serdes lane, the SFD and AM of different RS-FEC algorithms differ from each other by a distance CW_DIS of codeword of:
200G RS(544,514):CW_DIS＝CW2_N×5440*2/8；
200G RS(272,257):CW_DIS＝CW2_N×2720*2/8；
400G RS(544,514):CW_DIS＝CW2_N×5440*2/16；
400G RS(272,257):CW_DIS＝CW2_N×2720*2/16。
the remaining distance left_dis other than cw_dis is:
200G:LEFT_DIS＝(LEFT_257B/80)×10+LEFT_257B％10；
400G:LEFT_DIS＝(LEFT_257B/160)×10+LEFT_257B％10。
based on the above calculation result, the distance sd_dis between SFD and AM is equal to the sum of the distances sd_dis: sd_dis=cw_dis+left_dis.
In 200G BASE-R4 and 400GR8 modes, the data of the serdes lane will be interleaved into 4 (200G) and 8 (400G) serdes lanes per bit, so the final SD_DIS is SD_DIS=2× (CW_DIS+LEFT_DIS).
5. 100G/40G AUI mode distance conversion
The 40G/100G AUI is RS-FEC free, so the distance conversion is different from the algorithm described above. The 40G AUI mode physical layer interface has 4 pcs Lane, and the 100G AUI mode has 20 pcs Lane. The 66-bit data block is distributed to 4 or 20 pcs in the manner of round-robin. Let SFD appear on PCS _ LANE,
40G:PCS_LANE＝MII_DIS％64＝＝0？(MII_DIS/64)％4:(MII_DIS/64+ 1)％4；
100G:PCS_LANE＝MII_DIS％64＝＝0？(MII_DIS/64)％20:(MII_DIS/64+ 1)％20；
it should be noted that sd_lane starts from 1, if the calculation result of sd_lane is 0, it means that SFD falls on the last LANE.
Setting the distance between the SFD and the AM on the PCS Lane as PCS_DIS;
40G∶PCS_DIS＝MII_DIS/(64×4)×66+(MII_DIS％(64×4)＝＝ 00:(MII_DIS％6466∶MII_DIS％64))；
100G∶PCS_DIS＝MII_DIS/(64×20)×66+(MII_DIS％(64×20)＝＝ 00:(MII_DIS％6466∶MII_DIS％64))；
there are another 2 PMA interleaving schemes for the 100G AUI mode. 100G AUI4 will interleave 5 pieces of pcs lane data onto one serdes lane in a round-robin fashion. 100G AUI10 will interleave 2 pieces of pcs Lane data onto one serdes Lane in a round-robin fashion. The final SFD is therefore at a distance SD_DIS from AM on the serdes Lane of:
100G AUI4:SD_DIS＝PCS_DIS×5–(PCS_LANE％5＝＝00∶5-PCS_LANE％5)；
100G AUI10:SD_DIS＝PCS_DIS×2–(PCS_LANE％2＝＝00∶2-PCS_LANE％2)。
the distance sd_dis (in bits) between SFD and AM at the Serdes lane at different rates can be calculated by the algorithm described above.
When pattern of the first AM is detected on the Serdes interface, time TS of the sync code block AM is detected on the Serdes interface AM At this time, the current time TS (AM) is recorded. Because the AM pattern appears above the Serdes interface in a location that is not necessarily aligned to the lowest order of the Serdes. If this is found, HETS needs to correct the start bit of AM pattern. For example, a 32-bit wide serdes interface SD_RX [31:0]Suppose that the start bit of AM pattern appears at SD_RX [6 ]](6 th bit of Serdes interface), in which case the timestamp TS (AM) of the HETS sample AM would be modified to TS (AM) +6xUI, UI (bit interval) is the time in ps required per transfer of one Serdes Symbol over the Serdes interface.
The corresponding UI values for the different rate modes are listed in the table below:
in summary, the ethernet timestamp generation method provided in this embodiment eliminates the delay that the data may introduce uncertainty through the physical layer PCS/FEC as mentioned above, mainly including the following aspects:
periodically inserting AM or CM (Alignment/coding Marker);
inserted check symbol (parity symbol) of RS-FEC;
skew and skew variation between multiple Serdes lanes;
compensating the clock frequency;
other factors (for 100G/200G/400G, the location of the initial SFD is not necessarily aligned to the first Serdes lane0; the transmission module; and the delay introduced by the FEC encoder/decoder buffer, etc.);
the path delays (in ns) for the worst case at different rates are listed in the table below. By using the method of the present embodiment, uncertainty in the time stamp generation introduced by the PCS and FEC core is eliminated.
In addition to this, there is a deviation of the sampling clock stamps across the clock domain. Because the location of the sampling AM timestamp is at the Serdes interface, the clock frequency under the Serdes interface is set as HSS_CLK, and the system clock frequency is SYS_CLK. The timestamp under SYS_CLK needs to be sampled after the AM pattern is found on the Serdes interface, the operation across the clock domain introduces a sampling delay of at most 1 SYS_CLK. The HETS will subtract half the delay of SYS_CLK to compensate for the delay introduced across clock samples as shown in FIG. 7. The sample delay of the TX and RX loops before compensation will be 2ns, the post-compensation loop sample delay is reduced by 1/2, only 1ns.
The embodiment also discloses a timestamp generation system according to the above ethernet timestamp generation method, as shown in fig. 8, including:
the distance measurement module is used for measuring the distance MII_DIS between the frame start delimiter of the PTP packet head on the MII interface and the synchronous code block;
the distance conversion module is used for converting the distance MII_DIS into the distance SD_DIS between the frame start delimiter on the Serdes interface and the synchronous code block;
in a distance conversion module, determining a Serdes channel in which a frame start delimiter SFD is positioned; the Serdes channel is one of a plurality of channels included on a Serdes interface; converting the distance MII_DIS into a distance SD_DIS1 between a frame start delimiter SFD on the Serdes channel and a synchronous code block AM; determining a final distance sd_dis of the Serdes interface, wherein sd_dis=n×sd_dis1; the final data on the Serdes interface is obtained by interleaving the plurality of Serdes channel data according to bits; n is the interleaving ratio of the Serdes interface;
time detection moduleBlock for detecting the time TS of a synchronization code block on the Serdes interface AM ；
A time stamp calculation module for calculating a time TS AM And distance sd_dis to get SFD timestamp TS on the Serdes interface SFD The method comprises the following steps: TS (transport stream) SFD ＝TS AM +SD_DIS×UI, where UI is the time required for each Serdes symbol to be transmitted over the Serdes interface.
The technical details and the beneficial effects of the timestamp generation system are basically the same as those of the Ethernet timestamp generation method, and are not described in detail herein.
The present invention is not limited to the above-mentioned embodiments, and any changes or substitutions that can be easily understood by those skilled in the art within the technical scope of the present invention are intended to be included in the scope of the present invention. The present invention is not limited to the above-mentioned embodiments, and any changes or substitutions that can be easily understood by those skilled in the art within the technical scope of the present invention are intended to be included in the scope of the present invention.
Claims (9)
1. A method for generating SFD time stamps based on an ethernet synchronization code, comprising:
measuring the distance MII_DIS between a frame start delimiter SFD of a PTP packet head on an MII interface and a synchronous code block AM;
determining a Serdes channel in which a frame start delimiter SFD is positioned; the Serdes channel is one of a plurality of channels included on a Serdes interface;
converting the distance MII_DIS into a distance SD_DIS1 between a frame start delimiter SFD on the Serdes channel and a synchronous code block AM;
determining a final distance sd_dis of the Serdes interface, wherein sd_dis=n×sd_dis1; the final data on the Serdes interface is obtained by interleaving data in the channels according to bits; n is the interleaving ratio of the Serdes interface;
at the Serdes interfaceTime TS of up-detection of sync code block AM AM ；
According to the time TS AM And said distance sd_dis gets a start of frame delimiter SFD timestamp TS on the Serdes interface SFD The method comprises the steps of carrying out a first treatment on the surface of the Wherein TS SFD ＝TS AM +SD_DIS×UI, which is the time required for each Serdes symbol to be transmitted on the Serdes interface;
the measurement of the distance MII_DIS is performed in a PCS layer, and is measured in a transmission direction or a receiving direction;
in the transmission direction, the measurement of the distance mii_dis includes:
the method comprises the steps of finding a frame start delimiter SFD at an MII side, carrying out SFD indication identification, and transmitting the SFD indication identification to an AM insertion module of a PCS layer along with data;
inserting a synchronous code block AM in an AM insertion module to perform synchronous code AM indication identification;
measuring clock periods of the phase difference between the AM indication mark and the SFD indication mark; converting the phase-difference clock period to a distance mii_dis;
in the receiving direction, the measurement of the distance mii_dis includes:
finding a synchronous code block AM in an AM remove module of the PCS layer, and carrying out synchronous code AM indication identification; transmitting the AM indication identifier to the MII along with the data;
when the SFD is found on the MII interface, SFD indication identification is carried out;
measuring clock periods of the SFD indication mark and the AM indication mark which are different in the MII interface; the clock period of the phase difference is converted to a distance MII DIS.
2. The method for generating an SFD timestamp based on the Ethernet synchronization code as recited in claim 1,
the distance mii_dis on the MII interface of the ethernet in the 25G-400G rate range is:
25G：MII_DIS＝(Nt–1)×64+MII_OFFSET×32–8；
40G/50G：MII_DIS＝(Nt–1)×64+MII_OFFSET×64–8；
100G：MII_DIS＝(Nt–1)×2×64+MII_OFFSET×64–8；
200G：MII_DIS＝(Nt–1)×4×64+MII_OFFSET×64–8；
400G：MII_DIS＝(Nt–1)×8×64+MII_OFFSET×64–8；
nt is the OFFSET of the start bit of the frame start delimiter SFD on the MII interface of 64-bit width, where the AM indication identifier and the SFD indication identifier differ by a clock period.
3. The method for generating an SFD timestamp based on the Ethernet synchronization code as recited in claim 2,
in an ethernet network including RS-FEC, determining a Serdes channel in which a start of frame delimiter SFD is located, including:
according to only one Serdes channel, performing distance conversion, and calculating a distance caused by the number of bits CW_N of the FEC code words and a distance LEFT_257B caused by the number of bits of less than one complete FEC code word;
according to the formula sd_lane= (left_257 b%10= 0)? (LEFT_257B/10)% R (LEFT_257B/10+1)% R; judging the number of the frame start delimiter SFD falling on the Serdes channel; where R is the number of Serdes LANEs, sd_lane is the number of Serdes LANEs, which starts from 1, and SFD falls on the last LANE when sd_lane=0.
4. The method for generating an SFD timestamp based on an Ethernet synchronization code as recited in claim 3,
each FEC codeword comprises an mxn-bit data block, the number of FEC codewords having an integer number of bits cw_n=mii_dis/m/N, the integer number of bits of cw_n being reserved;
distance left_257 b=tc_n×257+ (left_64b-4×64×tc_n) + (left_64b%256= 00:1);
where left_64b=mii_dis-cw_n×m×n; tc_n=left_64b/4/64.
5. The method for generating an SFD timestamp based on an Ethernet synchronization code as recited in claim 4, wherein a start of frame delimiter SFD on said Serdes channel is a distance SD_DIS1 from a synchronization code block AM;
SD_DIS1＝CW_DIS1+LEFT_DIS1；
where cw_dis1=cw_n×l/R; left_dis1= (left_257B/10/R) ×10+left_257b%10;
l is the bit number of the FEC codeword, and R is the Serdes channel number.
6. The method for generating an SFD timestamp based on the Ethernet synchronization code as recited in claim 2,
in a 100G/40G AUI mode of the Ethernet without RS-FEC, a physical layer interface of the 40G AUI mode is provided with 4 PCS channels, and the 100G AUI mode is provided with 20 PCS channels;
when the distance conversion is carried out, the data blocks are distributed to 4 or 20 PCS channels; determining that the SFD falls on a certain PCS channel according to the following formula;
40G：PCS_LANE＝MII_DIS％64＝＝0？(MII_DIS/64)％4:(MII_DIS/64+1)％4；
100G：PCS_LANE＝MII_DIS％64＝＝0？(MII_DIS/64)％20:(MII_DIS/64+1)％20；
the distance sd_dis between the SFD and the sync code block on the PCS channel containing the SFD is pcs_dis:
40G：
PCS_DIS＝MII_DIS/(64×4)×66+(MII_DIS％(64×4)＝＝00:(MII_DIS％6466:MII_DIS％64))；
100G：
PCS_DIS＝MII_DIS/(64×20)×66+(MII_DIS％(64×20)＝＝00:(MII_DIS％6466:MII_DIS％64))。
7. the method for generating an SFD timestamp based on the Ethernet synchronization code as recited in claim 6,
the final distance sd_dis is:
100GAUI4：SD_DIS＝PCS_DIS×5–(PCS_LANE％5＝＝00:5-PCS_LANE％5)；
100GAUI10：SD_DIS＝PCS_DIS×2–(PCS_LANE％2＝＝00:2-PCS_LANE％2)；
the 100G AUI4 interweaves 5 pieces of pcs lane data to a serdes lane in a round-robin mode; 100G AUI10 interleaves 2 pieces of pcs lane data onto one serdes lane in a round-robin fashion.
8. The method for generating an SFD timestamp based on the Ethernet synchronization code as recited in claim 1,
detecting a first pattern of a synchronous code block AM on a Serdes interface, and recording the time TS of the current synchronous code block AM when the lowest bit of the first pattern appears on a Serdes interface AM The method comprises the steps of carrying out a first treatment on the surface of the Location sd_rx [ k ] when pattern of sync code block AM appears on Serdes interface sd_rx]When the bit is, the time of the synchronous code block AM is corrected to TS AM +kUI, k is the kth bit of the Serdes interface.
9. A system of a method of generating SFD time stamps based on ethernet synchronization codes according to any of claims 1-8, comprising:
the distance measurement module is used for measuring the distance MII_DIS between the frame start delimiter SFD of the PTP packet head on the MII interface and the synchronous code block AM;
the distance conversion module is used for converting the distance MII_DIS into a distance SD_DIS between a frame start delimiter SFD on the Serdes interface and the synchronous code block AM;
determining a Serdes channel in which a frame start delimiter SFD is positioned; the Serdes channel is one of a plurality of Serdes channels included on a Serdes interface; converting the distance MII_DIS into a distance SD_DIS1 between a frame start delimiter SFD on the Serdes channel and a synchronous code block AM; determining a final distance sd_dis of the Serdes interface, wherein sd_dis=n×sd_dis1; the final data on the Serdes interface is obtained by interleaving the plurality of Serdes channel data according to bits; n is the interleaving ratio of the Serdes interface;
a time detection module for detecting the time TS of the synchronous code block AM on the Serdes interface AM ；
A time stamp calculation module for calculating a time TS AM And the distance sd_dis to obtain the start of frame delimiter SFD timestamp TS on the Serdes interface SFD The method comprises the following steps: TS (transport stream) SFD ＝TS AM +SD_DIS x UI, where UI is the time required for each transmission of a Serdes symbol over the Serdes interface.
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